TC2320TG-G

TC2320 N- and P-Channel Enhancement-Mode Dual MOSFET Features ► ► ► ► ► ► ► Low threshold Low on resistance Low input capacitance Fast switching speeds Freedom from secondary breakdown Low input and output leakage Independent, electrically isolated N- and Pchannels General Description The Supertex TC2320TG consists of a high voltage, low threshold N- and P-channel MOSFET in an SO-8 package. These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► ► Medical ultrasound transmitters High voltage pulsers Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interface Ordering Information Device Package Options 8-Lead SOIC (Narrow Body) TC2320 TC2320TG-G BVDSS/BVDGS (V) RDS(ON) (max) (Ω) N-Channel 200 P-Channel -200 N-Channel 7.0 P-Channel 12 -G indicates package is RoHS compliant (‘Green’) Pin Configuration DRAIN_P DRAIN_P DRAIN_N DRAIN_N Absolute Maximum Ratings Parameter Drain to source voltage Drain to gate voltage Gate to source voltage Operating and storage temperature Soldering temperature* Value BVDSS BVDGS ±20V -55°C to +150°C +300°C GATE_P SOURCE_P GATE_N SOURCE_N 8-Lead SOIC (TG) Product Marking Y YWW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. C2320 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging 8-Lead SOIC (TG) TC2320 N-Channel Electrical Characteristics (@ 25°C unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVGS(th) IGSS Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate body leakage 200 0.6 - 300 2.0 -4.5 100 1.0 10.0 1.0 8.0 7.0 1.0 110 60 23 20 15 25 25 1.8 - V V mV/ C nA µA µA mA A O VGS = 0V, ID = 100µA VGS = VDS, ID = 1.0mA VGS = VDS, ID = 1.0mA VGS = ±20V, VDS = 0V VGS = 0V, VDS = 100V VGS = 0V, VDS = Max rating VGS = 0V, TA = 125OC VDS = 0.8 Max Rating VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150mA VGS = 10V, ID = 1.0A VGS = 4.5V, ID =150mA VDS = 25V, ID = 200mA VGS = 0V, VDS = 25V, f = 1.0MHz IDSS Zero gate voltage drain current - ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time 0.6 1.2 150 - Ω %/ C mmho O pF ns VDD =25V, ID = 150mA, RGEN = 25Ω VGS = 0V, ISD = 200mA VGS = 0V, ISD = 200mA V ns Notes: 1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. N- Channel Switching Waveforms and Test Circuit 10V VDD RL OUTPUT 90% INPUT 0V 10% t(ON) PULSE GENERATOR t(OFF) tr td(OFF) tF RGEN td(ON) VDD 10% 10% INPUT D.U.T. OUTPUT 0V 90% 90% 2 TC2320 P-Channel Electrical Characteristics (@ 25°C unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVGS(th) IGSS IDSS Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate body leakage Zero gate voltage drain current -200 -1.0 -0.25 -0.75 100 - -0.7 -2.1 10 8.0 250 75 20 10 300 -2.4 4.5 -100 -10 -1.0 15 12 1.7 125 85 35 10 15 20 15 -1.8 - V V mV/OC nA µA mA A VGS = 0V, ID = -2.0mA VGS = VDS, ID = -1.0mA VGS = VDS, ID = -1.0mA VGS = ±20V, VDS = 0V VGS = 0V, VDS = Max rating VGS = 0V, TA = 125OC, VDS = 0.8 Max Rating VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.5V, ID = -100mA VGS = -10V, ID = -200mA VGS = -10V, ID =-200mA VDS = -25V, ID = -200mA VGS = 0V, VDS = -25V, f = 1.0MHz ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time Ω %/OC mmho pF ns --- V ns VGS = 0V, ISD = -0.5A VGS = 0V, ISD = -0.5A Notes: 1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. P- Channel Switching Waveforms and Test Circuit 0V 10% INPUT -10V PULSE GENERATOR 90% t(OFF) tr td(OFF) tF INPUT RGEN D.U.T. Output RL 10% t(ON) td(ON) 0V 90% OUTPUT VDD 90% 10% VDD 3 TC2320 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch D 8 E E1 Note 1 (Index Area D/2 x E1/2) L θ1 L2 Gauge Plane 1 L1 θ Seating Plane Top View A Note 1 View B View B h h A A2 Seating Plane A1 e b Side View A View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A 1.35 1.75 A1 0.10 0.25 A2 1.25 1.50 b 0.31 0.51 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 L1 1.04 REF L2 0.25 BSC θ 0O 8 O θ1 5O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TC2320 A102607 4