TC6320TG

TC6320 N- and P- Channel Enhancement-Mode Dual MOSFET Features ► ► ► ► ► ► ► Low threshold Low on resistance Low input capacitance Fast switching speeds Freedom from secondary breakdown Low input and output leakage Independent, electrically isolated N- and Pchannels General Description The Supertex TC6320 consists of high voltage low threshold N-channel and P-channel MOSFETs in an SO8 package. Both MOSFETs have integrated gate-source resistors and gate-source zener diode clamps which are desired for high voltage pulser applications. The TC6320 is a complimentary, high-speed, high voltage, gate-clamped N- and P-channel MOSFET pair in an SO-8 package. These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► Medical ultrasound transmitters High voltage pulsers Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Ordering Information Device TC6320 Package Options 8-Lead SOIC (Narrow Body) TC6320TG TC6320TG-G BVDSS/BVDGS N-Channel 200V P-Channel -200V RDS(ON) (MAX) N-Channel 7.0Ω P-Channel 8.0Ω -G indicates package is RoHS compliant (‘Green’) Pin Configuration S1 1 2 3 4 P-Channel N-Channel 8 7 6 5 D1 D1 D2 D2 Absolute Maximum Ratings Parameter Drain to source voltage Drain to gate voltage Operating and storage temperature Soldering temperature1 Value BVDSS BVDGS -55°C to +150°C +300°C G1 S2 G2 Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note 1. Distance of 1.6mm from case for 10 seconds. SO-8 Package (top view) TC6320 N- Channel Electrical Characteristics (T = 25°C unless otherwise specified) J Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVGS(th) RGS ΔRGS VZGS ΔVZGS IDSS Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate-Source Shunt Resistor Change in RGS with Temperature Gate-Source Zener Voltage Change in VZGS with Temperature Zero gate voltage drain current 200 1.0 10 13.2 1.0 2.0 400 - - 2.0 -4.5 50 TBD 25 TBD V V mV/OC KΩ %/OC V mV/OC µA mA A VGS = 0V, ID = 2.0mA VGS = VDS, ID = 1.0mA VGS = VDS, ID = 1.0mA IGS = 100µA IGS = 100µA IGS = 2.0mA IGS = 2.0mA VDS = Max rating, VGS = 0V VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150mA VGS = 10V, ID = 1.0A VGS = 4.5V, ID =150mA VDS = 25V, ID = 200mA VGS = 0V, VDS = 25V, f = 1MHz 300 10.0 1.0 8.0 7.0 1.0 110 60 23 10 15 20 15 1.8 - ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time Ω %/OC mmho pF ns VDD =25V, ID = 1.0A, RGEN = 25Ω VGS = 0V, ISD = 0.5A VGS = 0V, ISD = 0.5A V ns Notes: 1.All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. N- Channel Switching Waveforms and Test Circuit 10V Input 0V 10% t(ON) td(ON) VDD Output 0V 90% 90% 10% tr t(OFF) td(OFF) tf 10% Input 90% Pulse Generator RGEN VDD RL OUTPUT D.U.T 2 TC6320 P- Channel Electrical Characteristics (T = 25°C unless otherwise specified) J Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVGS(th) RGS ΔRGS VZGS ΔVZGS IDSS Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate-source shunt resistor Change in RGS with temperature Gate-source zener voltage Change in RGS with temperature Zero gate voltage drain current -200 -1.0 10 13.2 -1.0 -2.0 400 - 300 -2.4 4.5 50 TBD 25 TBD -10 -1.0 10 8.0 1.0 200 55 30 10 15 20 15 -1.8 - V V mV/OC KΩ %/OC V mV/OC µA mA A VGS = 0V, ID = -2.0µA VGS = VDS, ID = -1.0mA VGS = VDS, ID = -1.0mA IGS = 100µA IGS = 100µA IGS = -2mA IGS = -2mA VDS = Max rating, VGS = 0V VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.5V, ID = -150mA VGS = -10V, ID = -1.0A VGS = -10V, ID =-200mA VDS = -25V, ID = -200mA VGS = 0V, VDS = -25V, f = 1MHz ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time Ω %/OC mmho pF ns VDD = -25V, ID = -1.0A, RGEN = 25Ω VGS = 0V, ISD = -0.5A VGS = 0V, ISD = -0.5A V ns Notes: 1.All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. P- Channel Switching Waveforms and Test Circuit 0V Input -10V 90% t(ON) td(ON) 0V Output VDD tr 90% 10% t(OFF) td(OFF) 90% RL 10% VDD tf Input OUTPUT RGEN D.U.T 10% Pulse Generator 3 TC6320 8-Lead SO (TG) Package Outline 4.90 ± 0.10 8 6.00 ± 0.20 3.90 ± 0.10 Note 2 1 Top View 0.17 - 0.25 1.75 MAX 1.25 MIN 5° - 15° (4 PLCS) 45° 0.25 - 0.50 Note 2 0° - 8° 0.10 - 0.25 1.27BSC 0.40 - 1.27 0.31 - 0.51 Side View Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. End View (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TC6320 C112106 4