TN0604_07

TN0604 N-Channel Enhancement-Mode Vertical DMOS FET Features ► ► ► ► ► ► ► ► Low threshold — 1.6V max. High input impedance Low input capacitance — 140pF typical Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. The Quad-Array package (20-Lead SOW (WG)) uses four independent DMOS transistors which provide four independent channels. Applications ► ► ► ► ► ► ► Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches Ordering Information BVDSS/BVDGS (V) RDS(ON) max (Ω) ID(ON) min (A) VGS(th) max (V) Package Options TO-92 TN0604N3-G - 20-Lead SOW TN0604WG-G 40 40 0.75 1.0 4.0 4.0 1.6 1.6 -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Gate-to-source voltage Operating and storage temperature Soldering temperature* Value BVDSS BVDGS ±20V -55OC to +150OC 300OC Pin Configurations SOURCE DRAIN GATE DRAIN1 DRAIN1 DRAIN1 GATE1 SOURCE1 SOURCE2 GATE2 DRAIN2 DRAIN2 DRAIN2 DRAIN4 DRAIN4 DRAIN4 GATE4 SOURCE4 SOURCE3 GATE3 DRAIN3 DRAIN3 DRAIN3 TO-92 (N3) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. 20-Lead SOW (WG) Product Marking Top Marking YYWW TN 0604W G LLLLLLLLLL Product Marking TN 0604 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging TO-92 (N3) Bottom Marking CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 20-Lead SOW (WG) TN0604 Thermal Characteristics Package TO-92 (N3) 20-Lead SOW (WG) (continuous)(1) (A) ID (pulsed) (A) ID Power Dissipation @TA = 25OC (W) θjc ( C/W) O θja ( C/W) O IDR(1) (A) IDRM (A) 0.7 1.0 4.6 4.0 0.74 1.5 125 - 170 84 0.7 1.0 4.6 4.0 Notes: (1) ID (continuous) is limited by max rated Tj . Electrical Characteristics (@25 C unless otherwise specified) O Sym BVDSS VGS(th) ΔVGS(th) IGSS IDSS Parameter Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate body leakage Zero gate voltage drain current Min 40 0.6 1.5 4.0 TO-92/ 20-Lead SOW 0.5 TO-92 20-Lead SOW Typ -3.8 2.1 7.0 1.0 0.6 0.5 0.8 140 75 25 1.2 300 Max 1.6 -4.5 100 10 1.0 1.6 0.75 1.0 0.75 190 110 50 10 6.0 25 20 1.8 - Units V V O Conditions VGS = 0V, ID = 2.0mA VGS = VDS, ID= 1.0mA VGS = ± 20V, VDS = 0V VGS = 0V, VDS = Max Rating VGS = 0V, VDS = 0.8 Max Rating, TA = 125°C VGS = 5.0V, VDS = 20V VGS = 10V, VDS = 20V VGS = 5.0V, ID = 0.75A mV/ C VGS = VDS, ID= 2.5mA nA µA mA A ID(ON) ON-state drain current Static drain-to-source ON-state resistance RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr Ω %/OC VGS = 10V, ID = 1.5A VGS = 10V, ID = 1.5A VGS = 0V, VDS = 20V, f = 1.0MHz VDD = 20V, ID = 0.5A, RGEN = 25Ω Change in RDS(ON) with temperature Forward transductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time mmho VDS = 20V, ID = 1.5A pF ns V ns VGS = 0V, ISD = 1.5A VGS = 0V, ISD = 1.0A Notes: (1) All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) (2) All A.C. parameters sample tested. Switching Waveforms and Test Circuit 10V VDD RL OUTPUT 90% INPUT 0V 10% t(ON) PULSE GENERATOR t(OFF) tr td(OFF) tF RGEN td(ON) VDD 10% 10% INPUT D.U.T. OUTPUT 0V 90% 90% 2 TN0604 Typical Performance Curves Output Characteristics 10 10 Saturation Characteristics 8 VGS = 10V 8 VGS = ID (amperes) ID (amperes) 6 9V 8V 6 10V 9V 8V 4 7V 6V 4 7V 6V 2 5V 4V 2 5V 4V 3V 0 0 10 20 30 40 50 3V 0 0 2 4 6 8 10 VDS (volts) Transconductance vs. Drain Current 2.0 2.0 VDS (volts) Power Dissipation vs. Case Temperature VDS = 25V DS GFS (siemens) PD (watts) TA = -55°C 1.0 TA = 25°C TA = 125°C TO-92 1.0 0 0 1 2 3 4 5 6 7 0 0 25 50 75 100 125 150 ID (amperes) Maximum Rated Safe Operating Area 10 1.0 TC (° C) Thermal Response Characteristics Thermal Resistance (normalized) TO-92 (pulsed) 0.8 ID (amperes) 1.0 0.6 TO-92 (DC) 0.1 0.4 0.2 T O-92 TC = 25°C PD = 1W T C = 25 ° C 0.01 0.1 1 10 100 0 0.001 0.01 0.1 1 10 VDS (volts) tp (seconds) 3 TN0604 Typical Performance Curves (cont.) BVDSS Variation with Temperature 2.0 1.1 On-Resistance vs. Drain Current VGS = 5V BVDSS (normalized) RDS(ON) (ohms) VGS = 10V 1.0 1.0 0.9 0 -50 0 50 100 150 0 5.0 10.0 Tj (°C) Transfer Characteristics 10 ID (amperes) V(th) and RDS Variation with Temperature 1.4 1.4 VDS = 25V 8 VGS(th) (normalized) ID (amperes) 6 = - ° 55 TA C = °C 25 1.2 V(th) @ 1mA 1.2 TA 4 1.0 R DS @ 10V, 1.5A 1.0 = 5 12 °C 0.8 0.8 TA 2 0.6 0 0 2 4 6 8 10 -50 0 50 100 150 0.6 VGS (volts) Capacitance vs. Drain-to-Source Voltage 200 10 Tj (°C) Gate Drive Dynamic Characteristics f = 1MHz 150 8 C ISS VDS = 10V C (picofarads) VGS (volts) 170 pF 6 170 pF 100 COSS 50 4 VDS = 40V CRSS 2 0 0 10 20 30 40 0 0 1.0 2.0 3.0 4.0 5.0 VDS (volts) QG (nanocoulombs) 4 RDS(ON) (normalized) TN0604 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L b e1 e C Front View Side View E1 E 1 2 3 Bottom View Symbol MIN Dimension (inches) NOM MAX Drawings not to scale. A .170 .210 b .014 .022 C .014 .022 D .175 .205 E .125 .165 E1 .080 .105 e .095 .105 e1 .045 .055 L .500 - 5 TN0604 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch D 20 θ1 E1 Note 1 (Index Area 0.25D x 0.75E1) 1 E L2 Gauge Plane L L1 θ Seating Plane Top View A View B View B h A A2 e Seating Plane h Note 1 A1 b A Side View View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension NOM (mm) MAX A 2.15 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 D 12.60 12.80 13.00 E 9.97 10.30 10.63 E1 7.40 7.50 7.60 e 1.27 BSC h 0.25 0.75 L 0.40 1.27 L1 1.40 REF L2 0.25 BSC θ 0 8 O θ1 5O 15O O JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN0604 A102507 6