TN2425TG

TN2425TG Low Threshold Dual N-Channel Enhancement-Mode Vertical DMOS FET Features ► ► ► ► ► ► ► ► Dual N-channel device Low threshold – 2.0V max. High input impedance Low input capacitance – 200pF Fast switching speeds Low caps ON resistance Free from secondary breakdown Low input and output leakage General Description The Supertex TN2425TG is a dual low threshold enhancement mode (normally off) transistor utilizing a vertical DMOS structure and Supertex’s well proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► Logic level interfaces – ideal for TTL and CMOS Solid state relays Medical ultrasound pulsers Analog switches General purpose line drivers Telecom switches Ordering Information Device TN2425TG Package Option 8-Lead SOIC (Narrow Body) TN2425TG BVDSS/BVDGS 250V RDS(ON) (max) 3.5Ω VGS(th) (max) 2.0V ID(ON) (min) 1.8A Absolute Maximum Ratings Parameter Drain to source voltage Drain to gate voltage Gate to source voltage Thermal resistance, Junction to drain lead Operating and storage temperature Soldering temperature1 Value BVDSS BVDGS ±20V 50°C/W Pin Configuration S1 1 8 D1 G1 2 7 D1 S2 -55°C to +150°C +300°C 3 6 D2 G2 4 5 D2 Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note 1. Distance of 1.6mm from case for 10 seconds. 8-Lead SOIC (top view) TN2425TG Electrical Characteristics (each device, T =25°C unless otherwise specified) J Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVMatch ΔVGS(th) IGSS IDSS Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature VGS(th) change with temperature Gate body leakage current Zero gate voltage drain current 250 0.6 1.5 1.8 300 - 115 30 10 5 10 25 5 300 2.0 25 -5.0 100 10 1.0 5.0 3.5 20 1.4 5 5 200 100 40 25 25 25 15 25 35 15 1.8 - V V mV mV/OC nA µA mA A Ω % %/ C mmho % % pF O VGS = 0V, ID = 250µA VGS = VDS, ID = 1mA VGS = VDS, ID = 1mA, TA = 10OC - 80OC VGS = VDS, ID = 1mA VGS = ±20V, VDS = 0V VDS = Max rating, VGS = 0V VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC VGS = 6.0V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 300mA VGS = 10V, ID = 400mA VGS = 10V, ID = 400mA VGS = 10V, ID = 400mA VDS = 15V, ID = 400mA VDS = 15V, ID = 50mA VGS = 15V, ID = 1.50A VGS = 0V, VDS = 25V, f = 1MHz ID(ON) RDS(ON) RMATCH ΔRDS(ON) GFS GFSMATCH CISS COSS CRSS CISSMATCH COSSMATCH CRSSMATCH td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Channel to channel RDS(ON) matching Change in RDS(ON) with temperature Forward transconductance Channel to channel GFS matching Input capacitance Common source output capacitance Reverse transfer capacitance Channel to channel CISS matching Channel to channel COSS matching Channel to channel CRSS matching Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time % VGS = 0V, VDS = 25V, f = 1MHz ns VDD = 25V, ID = 500mA, RGEN = 25Ω VGS = 0V, ISD = 500mA VGS = 0V, ISD = 500mA V ns Notes: 1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. Switching Waveforms and Test Circuit 10V VDD RL OUTP 90% INPUT 0V 10% t(ON) PULSE GENERATOR t(OFF) tr td(OFF) tF RGEN td(ON) VDD 10% 10% INPUT D.U.T. OUTPUT 0V 90% 90% 2 TN2425TG Typical Performance Curves Output Characteristics 5 3.0 Saturation Characteristics 4 2.5 VGS = 10V 8V 6V 5V ID (Amperes) ID (Amperes) VGS = 10V 8V 6V 5V 2.0 4V 1.5 3 2 4V 1.0 3V 1 3V 2.5V 0 0 10 20 30 40 50 0.5 2.5V 0.0 0 2 4 6 8 10 VDS (Volts) Transconductance vs. Drain Current 1.0 T A =-55 OC 0.8 V DS =15V 1.2 BV @ 250A VDS (Volts) BVDSS Variation with Temperature BVDSS (Normalized) 1.1 GFS (siemens) T A =25 OC 0.6 T A =125 OC 0.4 1.0 0.9 0.2 0.0 0.0 0.5 1.0 1.5 2.0 0.8 -50 0 50 100 150 ID (Amperes) On Resistance vs. Drain Current 10 3.0 TJ ( C) O Transfer Characteristics TA = 25OC 8 VGS = 4.5V 2.5 RDS(ON) (ohms) ID (Amperes) 2.0 TA = -55OC 1.5 TA = 125OC 6 4 VGS = 10V 2 1.0 0.5 0 VDS = 25V 0 1 2 3 4 5 0.0 0 2 4 6 8 10 ID (Amperes) 3 VGS (Volts) TN2425TG Typical Performance Curves (cont.) VGS(TH) and RDS(ON) w/ Temperature 2.0 1.8 RDS(ON) @ 10V, 0.5A Capacitance vs. Drain Source Voltage 1.8 200 f = 1MHz RDS(ON) (normalized) VGS(th) (normalized) C (picofarads) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -50 0 50 100 VGS(th) @ 1mA 1.5 150 CISS 100 1.2 0.9 50 COSS CRSS 0.6 150 0 0 10 20 30 40 50 TJ (OC) Gate Drive Dynamic Characteristics 10 ID = 480mA VDS (Volts) 8 VDS=10V VGS (volts) 6 VDS=40V 453pF 4 2 128pF 0 0.0 1.0 2.0 3.0 4.0 5.0 QG (nanocoulombs) 4 TN2425TG 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90 ± 0.10 8 6.00 ± 0.20 3.90 ± 0.10 Note 2 1 Top View 0.17 - 0.25 1.75 MAX 1.25 MIN 5° - 15° (4 PLCS) 45° 0.25 - 0.50 Note 2 0° - 8° 0.10 - 0.25 1.27BSC 0.40 - 1.27 0.31 - 0.51 Side View Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. End View (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN2425TG NR111506 5