TN2540ND

TN2540 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FET Features ► ► ► ► ► ► ► ► Low threshold — 2.0V max High input impedance Low input capacitance — 125pF max Fast switching speeds Low ON-resistance Free from secondary breakdown Low input and output leakage Complementary N and P-channel devices General Description The Supertex TN2540 is a low threshold enhancementmode transistor that utilizes an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► ► Logic level interfaces — ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic devices Analog switches General purpose line drivers Telecom switches Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V 10% t(ON) PULSE GENERATOR t(OFF) tr td(OFF) tF RL OUTPUT RGEN td(ON) VDD 10% 10% INPUT D.U.T. OUTPUT 0V 90% 90% TN2540 Ordering Information Package Options Device TO-92 TN2540 TN2540N3-G TO-243AA (SOT-89) TN2540N8-G Die* TN2540ND BVDSS/BVDGS (V) RDS(ON) (max) (Ω) VGS(th) (max) (V) ID(ON) (min) (A) 400 12 2.0 1.0 -G indicates package is RoHS compliant (‘Green’) * MIL visual screening available. Pin Configuration DRAIN Absolute Maximum Ratings Parameter Drain to source voltage Drain to gate voltage Gate to source voltage Operating and storage temperature Soldering temperature* * Distance of 1.6mm from case for 10 seconds. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Value BVDSS BVDGS ±20V -55°C to +150°C 300°C S G D GATE DRAIN (top view) SINK TO-92 (front view) TO-243AA (SOT-89) Product Marking TN 2540 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging TO-92 (N3) TN5DW W = Code for week sealed TO-243AA (SOT-89) (N8) Thermal Characteristics ID Package TO-92 TO-243AA (SOT-89) (continuous) (mA) ID (pulsed) (A) Power Dissipation @TA = 25OC (W) O θjc ( C/W) O θja ( C/W) IDR† (mA) 175 260 IDRM (A) 2.0 1.8 175 260 2.0 1.8 1.0 1.6‡ 125 15 170 78‡ Notes: † ID (continuous) is limited by max rated TJ . ‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm. 2 TN2540 Electrical Characteristics (@ 25°C unless otherwise specified) Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVGS(th) IGSS Drain-to-source breakdown voltage Gate threshold voltage VGS(th) change with temperature Gate body leakage current 400 0.6 - -2.5 0.5 1.0 8.0 8.0 200 95 20 10 300 2.0 -4.0 100 10 1.0 - V V mV/OC nA µA mA VGS = 0V, ID = 100µA VGS = VDS, ID = 1.0mA VGS = VDS, ID = 1.0mA VGS = ±20V, VDS = 0V VGS = 0V, VDS = Max rating VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V IDSS Zero gate voltage drain current 0.3 ID(ON) ON-state drain current 0.75 Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time 125 12 A RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr Ω 12 0.75 125 70 25 20 15 ns 25 20 1.8 V ns pF %/OC mmho VGS = 4.5V, ID = 150mA VGS = 10V, ID = 500mA VGS = 10V, ID = 500mA VDS = 25V, ID = 100mA VGS = 0V, VDS = 25V, f = 1.0MHz VDD = 25V, ID = 1.0A, RGEN = 25Ω VGS = 0V, ISD = 200mA VGS = 0V, ISD = 1.0A Notes: 1.All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. 3 TN2540 Typical Performance Curves ° ° ° ° ° 4 TN2540 Typical Performance Curves (cont.) BVDSS Variation with Temperature 1.1 50 On-Resistance vs. Drain Current 40 V GS = 4.5V BVDSS (normalized) RDS(ON) (ohms) VGS = 10V 30 1.0 20 10 0.9 -50 0 50 100 150 0 0 0.4 0.8 1.2 1.6 2.0 Tj (° C) Transfer Characteristics 1.5 ID (amperes) V(th) and RDS Variation with Temperature 2.5 VDS = 25V 1.2 1.4 R DS(ON) @ 10V, 0.5A 2.0 1.2 ID (amperes) TA = -55° C 0.9 1.5 1.0 1.0 0.8 0.5 0.6 0 0.6 25°C 0.3 125°C 0 2 4 6 8 10 -50 0 50 100 150 VGS (volts) Capacitance vs. Drain-to-Source Voltage 200 10 Tj (° C) Gate Drive Dynamic Characteristics f = 1MHz 8 150 VDS = 10V C (picofarads) VGS (volts) 6 100 CISS 4 VDS = 40V 260 pF 50 2 CRSS 0 0 10 20 30 COSS 0 40 0 95pF 0.4 0.8 1.2 1.6 2.0 VDS (volts) QG (nanocoulombs) 5 RDS(ON) (normalized) VGS(th) (normalized) V(th) @ 1mA TN2540 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L b e1 e C Front View Side View E1 E 1 2 3 Bottom View Symbol MIN Dimension (inches) NOM MAX Drawings not to scale. A .170 .210 b .014 .022 C .014 .022 D .175 .205 E .125 .165 E1 .800 .105 e .095 .105 e1 .045 .055 L .500 - 6 TN2540 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 4 C EH E1 1 L b e 2 3 b1 e1 A Top View Side View Symbol MIN Dimensions (mm) NOM MAX A 1.40 1.60 b 0.44 0.56 b1 0.36 0.48 C 0.35 0.44 D 4.40 4.60 D1 1.62 1.83 E 2.29 2.60 E1 2.13 2.29 e 1.50 BSC e1 3.00 BSC H 3.94 4.25 L 0.89 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN2540 A082307 7