TP2640LG-G

TP2635/TP2640 P- Channel Enhancement-Mode Vertical DMOS FETs Features ► ► ► ► ► ► ► ► Low threshold — -2.0V max. High input impedance Low input capacitance Fast switching speeds Low on resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices General Description These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► ► Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches Absolute Maximum Ratings Parameter Drain to source voltage Drain to gate voltage Gate to source voltage Operating and storage temperature Soldering temperature1 Value BVDSS BVDGS ±20V Pin Configurations NC NC S SGD 1 2 3 4 8 7 6 5 D D D D G -55°C to +150°C +300°C TO-92 (top view) SO-8 Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Note 1. Distance of 1.6mm from case for 10 seconds. Ordering Information Device Package Options SO-8 TP2640LG TP2640LG-G TO-92 TP2635N3 TP2635N3-G TP2640N3 TP2640N3-G BVDSS/BVDGS -350V RDS(ON) (max) 15Ω VGS(th) (max) -2.0V ID(ON) (min) -0.7A TP2635 TP2640 -400V 15Ω -2.0V -0.7A -G indicates package is RoHS compliant (‘Green’) 1 TP2635/TP2640 Thermal Characteristics Package ID (continuous)1 ID (pulsed) SO-8 TO-92 -210mA -180mA -1.25A -0.8A Power Dissipation @TC = 25OC 1.3W2 1.0W Θjc (OC/W) 24 125 Θjc (OC/W) 962 170 IDR1 210mA -180mA IDRM -1.25A -0.8A Notes: 1. ID (continuous) is limited by max rated Tj. 2. Mounted on FR4 board, 25mm x 25mm x 1.57mm Electrical Characteristics (T = 25°C unless otherwise specified) J Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(th) ΔVGS(th) IGSS Drain-to-source breakdown voltage Gate threshold voltage TP2640 TP2635 -400 -350 -0.8 - - -2.0 5 -100 -1.0 -10.0 -1.0 V V mV/ C nA µA µA mA A Ω %/OC m Ω O VGS = 0V, ID = -2.0mA VGS = VDS, ID = -1.0mA VGS = VDS, ID = -1.0mA VGS = ±20V, VDS = 0V VDS = -100V, VGS = 0V VDS = Max rating, VGS = 0V VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC VGS = -10V, VDS = -25V VGS = -2.5V, ID = -200mA VGS = -4.5V, ID = -150mA VGS = -10V, ID = -300mA VGS = -10V, ID = -300mA VDS = -25V, ID = -300mA VGS = 0V, VDS = -25V, f = 1MHz Change in VGS(th) with temperature Gate body leakage IDSS Zero gate voltage drain current - - ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time 0.7 200 - 12 11 11 300 15 15 15 0.75 300 50 12 10 15 60 40 -1.8 - pF ns VDD = 25V, ID = 2.0A, RGEN = 25Ω VGS = 0V, ISD = 200mA VGS = 0V, ISD = 1.0A V ns Notes: 1.All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. N- Channel Switching Waveforms and Test Circuit 0V 10% PULSE GENERATOR 90% t(ON) Rgen INPUT -10V t(OFF) tr td(OFF) tF INPUT td(ON) 0V D.U.T. OUTPUT RL 90% OUTPUT VDD 90% 10% 10% VDD 2 TP2635/TP2640 Typical Performance Curves Output Characteristics -2.0 -1.0 Saturation Characteristics -8V -8V -6V -6V -0.8 VGS = - 10V -1.6 VGS = - 10V ID (amperes) -4V ID (amperes) -1.2 -0.6 -0.8 -4V -0.4 -3V -0.2 -0.4 -3V 0 0 -10 -20 -30 -40 -50 0 0 -2 -4 -6 -8 -10 VDS (volts) Transconductance vs. Drain Current 1.0 2.0 VDS (volts) Power Dissipation vs. Temperature 0.8 1.6 GFS (siemens) VDS = -25V SO-8 PD (watts) 0.6 1.2 TO-92 0.4 TA = -55°C 0.8 0.2 125°C 0 0 -0.4 -0.8 -1.2 25°C 0.4 0 -1.6 -2.0 0 25 50 75 100 125 150 ID (amperes) Maximum Rated Safe Operating Area -10 SO-8 (pulsed) 1.0 TC (° C) Thermal Response Characteristics Thermal Resistance (normalized) -1.0 0.8 TO-92 (pulsed) SO-8 (DC) ID (amperes) 0.6 -0.1 TO-92 (DC) 0.4 -0.01 TC = 25°C 0.2 TO-92 TC = 25 °C PD = 1.0W 0.01 0.1 1.0 10 -0.001 -1 -10 -100 -1000 0 0.001 VDS (volts) tp (seconds) 3 TP2635/TP2640 Typical Performance Curves (cont.) BVDSS Variation with Temperature 30 1.1 24 On-Resistance vs. Drain Current VGS = -2.5V VGS = -4.5V BVDSS (normalized) RDS(ON) (ohms) 18 1.0 12 VGS = -10V 6 0.9 0 -50 0 50 100 150 0 -0.4 -0.8 -1.2 -1.6 -2.0 Tj (° C) Transfer Characteristics -2.0 ID (amperes) VTH and RDS Variation with Temperature 2.5 VDS = -25V -1.6 1.2 V(th) @ -1mA VGS(th) (normalized) ID (amperes) -1.2 TA = -55°C 1.0 1.5 0.8 1.0 0.6 25°C -0.8 RDS(ON)@ -10V, -0.3A 0.5 -0.4 0.4 0 0 -2 -4 -6 -8 -10 -50 0 50 100 150 0 VGS (volts) Capacitance vs. Drain-to-Source Voltage 400 -10 Tj (° C) Gate Drive Dynamic Characteristics f = 1MHz -8 300 678pF C (picofarads) VGS (volts) CISS 200 -6 VDS = -10V -4 VDS = -40V 100 -2 COSS 263pF 0 0 -10 -20 -30 CRSS -40 0 0 1 2 3 4 5 VDS (volts) QG (nanocoulombs) 4 RDS(ON) (normalized) +125°C 2.0 TP2635/TP2640 8-Lead SOIC Package Outline (LG) 4.90 ± 0.10 8 6.00 ± 0.20 3.90 ± 0.10 Note 2 1 Top View 0.17 - 0.25 1.75 MAX 1.25 MIN 5° - 15° (4 PLCS) 45° 0.25 - 0.50 Note 2 0° - 8° 0.10 - 0.25 1.27BSC 0.40 - 1.27 0.31 - 0.51 Side View Notes: 1. All dimensions in millimeters. Angles in degrees. 2. If the corner is not chamfered, then a Pin 1 identifier must be located within the area indicated. End View 3-Lead TO-92 Package Outline (N3) 0.135 MIN 0.125 - 0.165 0.080 - 0.105 1 2 3 Bottom View 0.175 - 0.205 0.170 - 0.210 123 Seating Plane 0.500 MIN 0.014 - 0.022 0.014 - 0.022 0.045 - 0.055 0.095 - 0.105 Front View Side View Notes: All dimensions are in millimeters; all angles in degrees. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP2635_TP2640 C032807 5