TP5322

TP5322 P-Channel Enhancement-Mode Vertical DMOS FETs Features ► ► ► ► ► ► ► ► High input impedance Low threshold Low input capacitance Fast switching speeds Low on resistance Low input and output leakage Free from secondary breakdown Complementary N- and P-channel devices General Description The Supertex TP5322 is a low threshold enhancementmode (normally-off) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► Logic level interfaces - ideal for TTL and CMOS Battery operated systems Photo voltaic devices Analog switches General purpose line drivers Telecom switches Ordering Information Package Options TO-236AB1 TP5322K1 TP5322K1-G TO-243AA2 TP5322N8 TP5322N8-G BVDSS /BVDGS -220V RDS(ON) (max) 12Ω VGS(TH) (max) -2.4V ID(ON) (min) -0.7A -G indicates package is RoHS compliant (‘Green’) Notes: 1Same as SOT-23, 2Same as SOT-89. Product marking for TO-236AB: P3C where = 2-week alpha date code Product marking for TO-243AA: TP3C where = 2-week alpha date code Absolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Gate-to-source voltage Operating and storage temperature Soldering temperature3 O Pin Configurations Value BVDSS BVDGS ±20V -55 C to +150OC 300OC Gate Source G D S Drain D Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 3 Distance of 1.6mm from case for 10 seconds. TO-236AB (Top View) TO-243AA (top view) TP5322 Thermal Characteristics Package TO-236AB TO-243AA ID (continuous)1 -0.12A -0.26A ID (pulsed) -0.70A -0.90A Power Dissipation @TC = 25OC 0.36W 1.6W 2 Θjc (OC/W) 200 15 Θjc (OC/W) 350 78 2 IDR1 -0.12A -0.26A IDRM -0.7A -0.9A Notes: 1. ID (continuous) is limited by max rated Tj. 2. Mounted on FR4 board, 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substrate. Electrical Characteristics Symbol Parameter Min Typ Max Units Conditions BVDSS VGS(TH) ΔVGS(TH) IGSS ID(SS) ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(TH) with temperature Gate body leakage current Zero gate voltage drain current ON-state drain current Static drain-to-source ON-state resistance Change in RDS(ON) with temperature Forward transconductance Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time O -220 -1.0 -0.7 - -0.95 10 8.0 -2.4 4.5 -100 -10 -1.0 15 12 1.7 110 45 20 V V mV/OC nA µA mA A Ω %/ C mmho pF O VGS = 0V, ID = -2.0mA VGS = VDS, ID = -1.0mA VGS = VDS, ID = -1.0mA VGS = ±20V, VDS = 0V VDS = Max rating, VGS = 0V VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC VGS = -10V, VDS = -25V VGS = -4.5V, ID = -100mA VGS = -10V, ID = -200mA VGS = -10V, ID = -200mA VDS = -25V, ID = -200mA VGS = 0V, VDS = -25V, f = 1MHz VDD = -25V, ID = -0.7A, RGEN = 25Ω, VGS = 0V, ISD = -0.5A VGS = 0V, ISD = -0.5A 100 - 250 300 10 15 20 15 -1.8 V ns ns Notes: 1.All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2.All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V 10% INPUT -10V PULSE GENERATOR 90% t(OFF) tr td(OFF) tF INPUT RGEN D.U.T. Output RL 10% t(ON) td(ON) 0V 90% OUTPUT VDD 90% 10% VDD 2 TP5322 3-Lead TO-236AB (SOT-23) Package Outline (K1) 0.0173 ± 0.0027 (0.4394 ± 0.0685) 0.0906 ± 0.0079 (2.299 ± 0.199) 1 3 0.0512 ± 0.004 2 (1.3004 ± 0.1016) Measurement Legend = 0.0207 ± 0.003 Dimensions in Inches (Dimensions in Millimeters) 0.0754 ± 0.0053 (1.915 ± 0.135) (0.5257 ± 0.0762) Top View 0.115 ± 0.005 (2.920 ± 0.121) 0.0400 ± 0.007 (1.016 ± 0.178) 0.0210 ± 0.003 (0.5334 ± 0.076) 0.0382 ± 0.003 (0.9690 ± 0.0762) 0.0043 ± 0.0009 (0.1092 ± 0.0229) 0.0035 ± 0.0025 (0.0889 ± 0.0635) 0.0197 (0.50) NOM Side View End View 3 TP5322 3-Lead TO-243AA (SOT-89) Surface Mount Package (N8) 4.50 ± 0.10 1.72 ± 0.10 0.40 ± 0.05 Exclusion Zone 1.50 ± 0.10 4.10 ± 0.15 2.45 ± 0.15 2.21 ± 0.08 No Vias/Traces in this area. Shape of pad may vary. 1.05 ± 0.15 0.42 ± 0.06 1.50 BSC 3.00 BSC 0.5 ± 0.06 Top View Side View Bottom View Notes: All dimensions are in millimeters; all angles in degrees. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP5322 A032807 4