VP1506

VP1504/VP1506/VP1509 P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / BVDGS -40V -60V -90V † MIL visual screening available. RDS(ON) (max) 8.0Ω 8.0Ω 8.0Ω ID(ON) (min) -0.5A -0.5A -0.5A Order Number / Package Die† VP1504NW VP1506NW VP1509NW Features ❏ Free from secondary breakdown ❏ Low power drive requirement ❏ Ease of paralleling ❏ Low CISS and fast switching speeds ❏ Excellent thermal stability ❏ Integral Source-Drain diode ❏ High input impedance and high gain ❏ Complementary N- and P-channel devices Advanced DMOS Technology This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ❏ Motor controls ❏ Converters ❏ Amplifiers ❏ Switches ❏ Power supply circuits ❏ Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Absolute Maximum Ratings Drain-to-Source Voltage Drain-to-Gate Voltage Gate-to-Source Voltage Operating and Storage Temperature Soldering Temperature* * Distance of 1.6 mm from case for 10 seconds. O BVDSS BVDGS ±20V -55 C to +150OC 300OC 1 VP1504/VP1506/VP1509 Electrical Characteristics (@ 25 C unless otherwise specified) Symbol BVDSS Parameter Drain-to-Source Breakdown Voltage VP1504 VP1506 VP1509 VGS(th) ΔVGS(th) IGSS IDSS Gate Threshold Voltage Change in VGS(th) with Temperature Gate Body Leakage Zero Gate Voltage Drain Current Min -40 -60 -90 -1.5 5.8 -1.0 -3.5 6.5 -100 -10 -1 ID(ON) RDS(ON) ΔRDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr ON-State Drain Current Static Drain-to-Source ON-State Resistance Change in RDS(ON) with Temperature Forward Transconductance Input Capacitance Common Source Output Capacitance Reverse Transfer Capacitance Turn-ON Delay Time Rise Time Turn-OFF Delay Time Fall Time Diode Forward Voltage Drop Reverse Recovery Time 150 -0.15 -0.50 -0.25 -1.2 11 6.0 0.55 190 45 22 3 4 3 8 4 -1.2 400 60 30 8 6 10 12 10 -2.0 V ns ns VDD = -25V ID = -0.5A RGEN = 25Ω ISD = -1.0A, VGS = 0V ISD = -1.0A, VGS = 0V pF 15 8.0 1.0 Ω %/ C m V mV/ C nA µA mA A VGS = VDS, ID = -1.0mA ID = -1.0mA, VGS = VDS VGS = ± 20V, VDS = 0V VGS = 0V, VDS = Max Rating VGS = 0V, VDS = 0.8 Max Rating TA = 125 C VGS = -5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -5V, ID = -0.1A VGS = -10V, ID = -0.5A VGS = -10V, ID = -0.5A VDS = -25V, ID = -0.5A VGS = 0V, VDS = -25V f = 1 MHz Typ Max Unit V Conditions ID = -1.0mA, VGS = 0V Notes: 1. All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V 10% INPUT -10V PULSE GENERATOR 90% t(ON) t(OFF) tr td(OFF) tF INPUT Rgen td(ON) 0V 90% OUTPUT VDD 90% 10% 10% Doc.# DSFP - VP1504/VP1506/VP1509 062706 2 Ω D.U.T. OUTPUT RL VDD