SM5964AL25

SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Product List SM5964AL25, 25MHz 64KB internal flash MCU Feature Working Voltage:3.0V through 3.6V 80C51 Central Processor Unit (CPU) 64K x 8 on chip flash memory with InSystem-Programming(ISP) capability and it can be programmed at VCC = 3.3V 1024 x 8 RAM, expandable externally to 64KB Two standard 16-bits timers/counters An additional 16-bits timer/counter coupled to a capture and compare register. Two 8-bits / 5-bits resolution Pulse-Width-Modulation (PWM) outputs Four 8-bits I/O ports.(For PDIP package) Four 8-bits I/O ports plus one 4-bits I/O port. (For PLCC or QFP package) TWSI-bus serial I/O port with master and slave functions Full-duplex UART 7 interrupt sources with 2 priority levels Temperature range (0℃ to +70℃) Software enable/disable ALE output pulse Wake-up from POWER-DOWN mode by external interrupt or H/W RESET. ISP service program space configurable in N*512 byte (N=0 to 8) size General Description The SM5964A is a single-chip 8-bits microcontroller manufactured in an advanced CMOS process with on chip flash memory. It supports InSystem Programming (ISP) function and is a derivative of the 8052 microcontroller family. The SM5964A has the same instructions set as the 80C51. The SM5964A contains a 64KB 3.3V on chip program flash, a volatile 1024 x 8 data RAM, four 8-bits I/O ports, one 4-bits I/O port, two 16-bits timer/event counters, and an additional 16-bits timer coupled to capture and compare latches, a two-priority-level, nested interrupt structure, two pulse-width- modulation (PWM) outputs, two serial interfaces (UART and TWSI bus). For system that requires extra capability the SM5964A can be expanded using standard LVTTL compatible memory and logic. In addition, The SM5964A has two software selectable modes of power saving – IDLE mode and POWER-DOWN mode. The IDLE mode freezes the CPU while allowing the RAM, timer, serial ports, and interrupt system to continue functioning. The POWER-DOWN mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The SM5964A is designed for 3.3V applications. The on chip flash memory can store data while the program is running. It also can upgrade the user program by down-load new code form PC or other devices. The chip is considered as a small integrated system. Ordering Information SM5964AihhkL yymmv i: process identifier {L=3.0V~3.6V} hh: working clock in MHz {25} k: package type postfix {as below table} yy: year mm: month v: version identifier { , A, B, ...} L: PB free identifier {no text is Non-PB free, “P” is PB free} Specifications subject to change without notice contact your sales representatives for the most recent information. Taiwan 6F, No.10-2 Li- Hsin 1st Road , Science-based Industrial Park, Hsinchu, Taiwan 30078 TEL: 886-3-567-1820 886-3-567-1880 FAX: 886-3-567-1891 886-3-567-1894 1 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Package Spec. K Package Pin / PAD Pin Configuration J Q P 44L PLCC 44L QFP 40L PDIP Figure 1 Figure 2 Figure 3 Figure 1 44L PLCC Package Figure 2 44L QFP Package Figure 3 40L PDIP Package Specifications subject to change without notice contact your sales representatives for the most recent information. 2 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Block Diagram PWM0 PWM1 T2 T2EX RxD (3) TxD (3) (1) (1) (1) (1) Xtal1 Xtal2 EA CPU ALE PSEN RD WR (3) (3) UART Int-RAM 256x8 IAP FLASH 64Kx8 Ext-RAM 768x8 PWM Timer2 C51 CORE iBUS Timer0 Timer1 INT PDWU Port0 Parallel I/O ports & Ext. Bus Port1 Port2 Port3 Port4 TWSI (1) (1) (3) (3) (3) (3) (3) (3) Notes: (1): Alternate function of P1 (3): Alternate function of P3 Specifications subject to change without notice contact your sales representatives for the most recent information. RES T0 T1 INT0 INT0 INT1 INT1 3 P0 P4 P1 P2 SCL SDA Ver 2.3 SM5964A 10/2006 P3 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Pin Description MNEMONIC VDD PDIP 40 pin 40 PQFP 44 Pin 38 PLCC 44 pin 44 Names and Functions Power supply: +3.3V power supply pin during normal operations and power saving modes. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them become floating and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: An 8-bits bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate function of SM5964A include： Port Pin Alternative function P1.0 T2： TIMER2 clock output P1.1 T2EX：TIMER2 reload/capture DIR. P1.2 PWM0：PWM channel 0 output P1.3 PWM1：PWM channel 1 output P1.6 SCL：TWSI bus clock P1.7 SDA：TWSI bus data Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor to VCC. Port 2: Port 2 is an 8-bits bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bits addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bits addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bits bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features. Port Pin Alternative function P3.0 RxD UART input P3.1 TxD UART output P3.2 #EX0 external interrupt 0 P3.3 #EX1 external interrupt 1 P3.4 T0: Timer 0 external input P3.5 T1: Timer 1 external input P3.6 #WR External data memory write strobe P3.7 #RD External data memory read strobe P0.0 – P0.7 39,38,37,36 35,34,33,32 37,36,35,34 33,32,31,30 43,42,41,40 39,38,37,36 P1.0 – P1.7 1,2,3,4, 5,6,7,8 40,41,42,43, 44,1,2,3 2,3,4,5, 6,7,8,9 RST 9 4 10 P2.0 – P2.7 21,22,23,24, 25,26,27,28 18,19,20,21 22,23,24,25 24,25,26,27, 28,29,30,31 P3.0 – P3.7 10,11,12,13 14,15,16,17 5,7,8,9, 10,11,12,13 11, 13,14,15, 16,17,18,19 Specifications subject to change without notice contact your sales representatives for the most recent information. 4 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A MNEMONIC ALE PDIP 40 pin 30 PQFP 44 Pin 27 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded PLCC 44 pin Names and Functions 33 Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Setting SFR SCONF.0 can disable ALE. With this bit set, ALE will be active only during a MOVX instruction. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, #PSEN is activated twice each machine cycle, except that two #PSEN activations are skipped during each access to external data memory. #PSEN is not activated during fetches from internal program memory. External Access Enable: #EA must be externally held low to enable the device to fetch code from external program memory locations. If #EA is held high, the device executes from internal program memory. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. #PSEN 29 26 32 #EA 31 29 35 X1 19 15 21 X2 18 14 20 Specifications subject to change without notice contact your sales representatives for the most recent information. 5 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded SFR Mapping The special function register of SM5964A fall into the following categories C51 CORE register: ACC, B, DPL, DPH, PSW, SP I/O ports: P0,P1, P2, P3, P4, P1CON Timer/Counter register: T2CON, T2MOD, TCON, TMOD, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H UART I/O register: SBUF, SCON TWSI bus register: TWSIS, TWSIA, TWSIC1, TWSIC2, TWSITXD, TWSIRXD Power and system control register: PCON, SCONF Interrupt system register: IP, IE, IP1, IE1, IFR IAP Flash programming register :ISPFAH, ISPFAL, ISPFD, ISPC PWM output register: PWMC0, PWMC1, PWMD0, PWMD1 Table 1 SFR Map $F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 ACC 0000 0000 P4 xxxx 1111 PSW 0000 0000 T2CON 0000 0000 TWSIS 0000 0000 IP 0000 0000 P3 1111 1111 IE 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 B 0000 0000 ISPFAH 0000 0000 ISPFAL 0000 0000 ISPFD 0000 0000 ISPC 0000 0000 $FF $F7 $EF $E7 $DF PWMC0 0000 0000 RCAP2H 0000 0000 TWSIC2 0000 0000 PWMC1 0000 0000 TL2 0000 0000 TWSITXD 1111 1111 $D7 TH2 0000 0000 TWSIRXD 0000 0000 SCONF 0000 0000 PWMD0 0000 0000 IE1 0000 0000 IFR 0000 0000 PWMD1 0000 0000 $CF $C7 $BF $B7 $AF $A7 SBUF xxxx xxxx P1CON 0000 0000 $9F $97 TMOD 0000 0000 SP 0000 0111 TL0 0000 0000 DPL 0000 0000 TL1 0000 0000 DPH 0000 0000 TH0 0000 0000 TH1 0000 0000 RCON 0000 0000 $8F PCON 0000 0000 $87 T2MOD xxxx xx00 TWSIA 1010 0000 IP1 0000 0000 RCAP2L 0000 0000 TWSIC1 0000 0001 Specifications subject to change without notice contact your sales representatives for the most recent information. 6 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Table 2 : All SFR list (8051, I/O, Timer, UART, TWSI, System, Interrupt) Symbol ACC B SP PSW DPH DPL P0 P1 P2 P3 P4 P1CON TCON TMOD TH0 TL0 TH1 TL1 T2CON T2MOD RCAP2H RCAP2L TH2 TL2 SCON SBUF TWSIS TWSIA TWSIC1 TWSIC2 TWSITXD TWSIRXD Description Accumulator B register Stack Pointer Process Status Data Pointer High Data Pointer Low Port 0 Port 1 Port 2 Port 3 Port 4 P1 Control Timer Control register Timer Mode Timer 0 High Timer 0 Low Timer 1 High Timer 1 Low Timer 2 Control Timer 2 Mode RCAP2 High RCAP2 Low Timer 2 High Time 2 Low UART Control UART Buffer TWSI bus status TWSI address TWSI control 1 TWSI Control 2 TWSI Transmit Data TWSI Received Data Power Control register System Control Interrupt Enable Interrupt Enable 1 Interrupt Flag 1 Interrupt Priority Interrupt Priority 1 Internal RAM Control ISP Address high ISP Address low ISP Data ISP Control PWM 0 Control PWM 1 Control PWM 0 Data PWM 1 Data Direct E0H F0H 81H D0H 83H 82H 80H 90H A0H B0H D8H 9BH 88H 89H 8CH 8AH 8DH 8BH C8H C9H CBH CAH CDH CCH 98H 99H C0H C1H C2H Bit 7 Bit 6 Bit 5 8051 Core Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET 00H 00H 07H 00H 00H 00H FFH FFH FFH FFH XFH 00H 00H 00H 00H 00H 00H 00H 00H X0H 00H 00H 00H 00H 00H XXH 00H A0H 01H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H CY AC F0 RS1 RS0 OV P P0.7 P1.7 P2.7 P3.7 SDAE TF1 GATE P0.6 P1.6 P2.6 P3.6 I/O PORT P0.5 P1.5 P2.5 P3.5 P0.4 P1.4 P2.4 P3.4 SCLE TIMER / Counter TF1 TF0 C/T M1 P0.3 P1.3 P2.3 P3.3 P4.3 PWM1E IE1 GATE P0.2 P1.2 P2.2 P3.2 P4.2 PWM0E IT1 C/T P0.1 P1.1 P2.1 P3.1 P4.1 IE0 M1 P0.0 P1.0 P2.0 P3.0 P4.0 IT0 M0 TR0 M0 TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 T2OE CPRL2 DCEN SM0 SM1 UART SM2 TWSI BUS REN TB8 RB8 TI RI RXIF TWSIE TXIF TFIF NAKIF Bus Busy RXAK TWSIFS2 MASTER TWSIFS1 TXAK TWSIFS0 C3H C4H C5H 87H BFH A8H A9H AAH B8H B9H 85H Match SRW RESTART MRW Power and System PCON SCONF IE IE1 IFR IP IP1 RCON ISPFAH ISPFAL ISPFD ISPC PWMC0 PWMC1 PWMD0 PWMD1 SMOD PDWUE EA Interrupt system ET2 ES0 ET1 GF1 GF0 ISPE EX1 PD OME ET0 ETWSI TWSIIF PT0 PTWSI RAMS1 ISP FLASH memory F4H F5H F6H F7H D3H D4H B3H B4H IDLE ALEI EX0 PT2 Data Memory PS0 PT1 PX1 PX0 RAMS0 START PWM output PBS PBS PWMD.7 PWMD.7 PWMD.6 PWMD.6 PWMD.5 PWMD.5 PWMD.4 PWMD.4 PWMD.3 PWMD.3 PWMD.2 PWMD.2 ISPF1 PFS1 PFS1 PWMD.1 PWMD.1 ISPF0 PFS0 PFS0 PWMD.0 PWMD.0 Operating Conditions Symbol TA Description Operating temperature Min. 0 Typ. 25 Max. 70 Unit. ℃ Remarks Ambient temperature under bias Specifications subject to change without notice contact your sales representatives for the most recent information. 7 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded VCC33 Fosc 25 Supply voltage Oscillator Frequency 3.0 3.3 3.6 25 V MHz For 3.3V application DC Characteristic VCC = 3.3V (±10%), VSS=0V TA= 0℃ to +70℃ SYMBOL VCC ICC IID IPD VIL1 VIL2 VIH1 VIH2 IIL1 IIL2 ITL ILI ISK1 ISK2 ISR1 ISR2 VOL1 VOL2 VOH1 VOH1 RRST CIO Supply Voltage Supply current operating Supply current IDLE mode Supply current Power-Down mode Input LOW voltage, Port 0,1,2,3,4,/EA Input LOW voltage, RES, XTAL1 Input HIGH voltage, Port 0,1,2,3,4,EA Input HIGH voltage, RES, XTAL1 Input current LOW level Port 1,2,3,4 ( except P1.6,P1.7 ) Input current LOW level Port 0,P1.6,P1.7 Transition current High to Low Port 1,2,3,4 Input leakage current Sink Current Port 1, 2, 3, 4 Sink Current Port 0,ALE, /PSEN Source Current Port 1, 2, 3, 4 Source Current Port 0,ALE, /PSEN Output LOW voltage, Port 0,ALE, /PSEN Output LOW voltage, Port 1, 2, 3, 4 Output High voltage Port0 ALE, /PSEN Output High voltage Port 1,2,3,4 Internal RESET pull-down resistor Pin capacitance VIN = 0.45V VIN = 0.45V VIN = 1.5 V 0.45V < VIN < VCC VCC = 3.3V, VIN = 0.4 V VCC = 3.3V, VIN = 0.4 V VCC = 3.3V, VIN = 2.4 V VCC = 3.3V, VIN = 2.4 V OUTPUT IOL = 3.2mA，VCC=3.3V IOL = 1.6mA，VCC=3.3V IOH = -300uA，VCC=3.3V IOH = -20μA，VCC=3.3V VCC=3.6V Test freq=1MHz, TA=25℃ See notes 1 fCLK = 12MHz VCC = 3.6V See note 2 fCLK = 12MHz VCC = 3.6V See note 3 2V < VPC < VCCmax INPUT -0.5 0 2.0 70% VCC PARAMETER TEST CONDITIONS LIMITS MIN MAX 3.0 3.6 10 5 20 0.8 0.8 Vcc+0.2 Vcc+0.2 -50 -650 -650 10 6 8 -80 -8 0.4 0.4 2.4 2.4 50 UNIT V mA mA μA V V V V μA μA μA μA mA mA uA mA V V V V kΩ pF 3 4 -40 -4 300 10 NOTES FOR DC ELECTRICAL CHARACTERISTICS 1. The operating supply current is measured with all output disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;/EA=RST=Port0=VDD; 2. The IDLE MODE supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;/EA= Port0=VDD; 3. The POWER-DOWN MODE supply current is measured with all output pins disconnected; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect; /EA= Port0=VDD; 4. Port 1, 2, 3, and 4 sources a transition current when they are being externally driven from HIGH to LOW. The transition current reaches its maximum value when VIN is approximately 2V. 5. Capacities loading on port 0 and 2 may cause spurious noise to be superimposed on VOL of ALE and port 1, 3, and 4. The noise is due to external bus capacitance discharging into port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacities loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt trigger STROBE input. 6. Under steady state (non-transient) conditions, IOL must be externally Limited as follows: Maximum IOL per pin (use sign pin only) : 10mA Maximum IOL per 8-bit port : port 0 : 26mA port 1,2,3 : 15mA Maximum total IOL for all output pins : 71mA If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Specifications subject to change without notice contact your sales representatives for the most recent information. 8 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded AC Characteristic VCC=3.3V±10%, VSS=0V, tclk min = 1/ fmax(maximum operating frequency) TA=0℃ to +70℃ CL=100pF for Port0, ALE and /PSEN; CL=80pF for all other outputs unless otherwise specified. Symbol tCLK tCLKH tCLKL tCLKR tCLKF tCYC NOTES : 1. Operating is 25MHz. FIGURE 4 4 4 4 4 4 PARAMETER External Clock drive into XTAL1 Xtal1 Period Xtal1 HIGH time Xtal1 LOW time XTAL1 rise time XTAL1 fall time Controller cycle time = tCLK / 12 40(1) 20 20 3.33 MIN MAX 10 10 ns ns ns ns ns ns UNIT Symbol 1/tCLK tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tAVLL tLLAX tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH tXLXL tQVXH tXHQX tXHDX tXHDV FIGURE 7 7 7 7 7 7 7 7 7 7 7 7 8,9 8,9 8 9 8 8 8 8 8 8,9 8,9 9 9 9 8 8,9 10 10 10 10 10 PARAMETER Program Memory System clock frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE LOW to valid instruction in ALE LOW to /PSEN LOW /PSEN pulse width /PSEN LOW to valid instruction in Input instruction hold after /PSEN Input instruction float after /PSEN Address to valid instruction in /PSEN low to address float Data Memory Address valid to ALE LOW Address hold after ALE LOW /RD pulse width /WR pulse width /RD LOW to valid data in Data hold after /RD Data float after /RD ALE LOW to valid data in Address to valid data in ALE LOW to /RD or /WR LOW Address valid to /WR or /RD LOW Data valid to /WR transition Data before /WR Data hold after /WR /RD LOW to address float /RD or /WR HIGH to ALE HIGH UART Serial port clock time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid MIN 3.0 2tCLK-40 tCLK-40 tCLK-30 tCLK-30 3tCLK-45 25 MAX UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4tCLK-100 3tCLK-105 0 tCLK -25 5tCLK-105 10 tCLK-40 tCLK-35 6tCLK-100 6tCLK-100 5tCLK-165 0 2tCLK-70 8tCLK-150 9tCLK-165 3tCLK+50 3tCLK-50 4tCLK-130 tCLK-50 7tCLK-150 tCLK-50 tCLK-40 12tCLK 10tCLK-133 2tCLK-117 0 0 tCLK+40 10tCLK-133 Specifications subject to change without notice contact your sales representatives for the most recent information. 9 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded tCLKH VIH1 0.8V tCLKR tCLKF tCLKL tCLK Figure 4 External Clock Drive waveform 2.0V 0.8V 2.0V Test Points 0.8V Notes: AC inputs during testing are driven at 2.4V for logic “HIGH” and 0.45V for logic “LOW”. Timing measurements are at 2.0V for logic “HIGH” and 0.8V for logic “LOW” Figure 5 AC Testing Input/Output Floating 2.0V 0.8V 2.0V 0.8V Notes: The float state is define as the point which PORT 0 pins sinks 3.2mA or source 400μA at the voltage test level. Figure 6 AC Testing, Floating Waveform t LHLL ALE t LLPL t AVLL /PSEN t PLAZ t LLAX t LLIV PORT0 A0-A7 t AVIV PORT2 A8-A15 A8-A15 A8-A15 INSTR IN t PXIZ t PXIX A0-A7 t PLIV t PLPH Figure 7 External Program Memory Read Cycle Specifications subject to change without notice contact your sales representatives for the most recent information. 10 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded ALE t WHLH /PSEN t LLDV t LLWL /RD t AVLL t LLAX PORT0 A0 - A7 (RI or DPL) t RLRH t RLDV t RLAZ DATA IN t RHDZ t RHDX A0 - A7 (PCL) INSTR IN t AVDV t AVWL PORT2 A8 - A15 of DPH or PORT2 A8 - A15 (PCH) Figure 8 external memory read cycle ALE tWHLH /PSEN t LLWL /WR tQVWH tAVLL PORT0 t LLAX tAVWL PORT2 A8 - A15 of DPH or PORT2 A8 - A15 (PCH) t QVWX DATA OUT tWHQX A0 - A7 (PCL) INSTR IN t WLWH A0 - A7 (RI or DPL) Figure 9 external memory write cycle nstruction ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH TXD 0 tXHDV RxD VALID tXHQX 1 tXHDX VALID VALID VALID VALID VALID VALID 2 3 4 5 6 7 Set_R VALID Figure 10 UART waveform in Shift Register MODE Specifications subject to change without notice contact your sales representatives for the most recent information. 11 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded repeat START condition tSU;STA START or repeat START condition STOP condition SDA tFD tRD tHD;DAT tFC 0.7VCC 0.3VCC tRC tSP tBUF tSU;STO START SCL tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tSU;DAT tSU;DAT2 Figure 11 Timing waveform of TWSI interface Standard-MODE MIN TWSI Bus fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tRD,tRC tFD tFC tSU;STO tSU;STA Cb tSP NOTES: 1. A fast-mode TWSI bus device can be used in a standard-mode TWSI bus system, but the requirement tSU;DAT ≥ 250ns must the be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode TWSI bus specification) before the SCL line is released. 2. Cb = Total capacitance of one bus line in pF. 11 11 11 11 11 11 11 11 11 11 11 11 11 SCL clock frequency Bus free time between a stop and stop condition Hold time (repeated) START condition. After this period, the first clock pulse is generated Low Period of the SCL clock High period of the SCL clock Set-up time of a repeated START condition Data hold time Data Setup-Time Rise time of both SDA and SCL Fall time of both SDA and SCL Set-up time for STOP and START condition Capacitive load for each bus line Pulse width of spikes which must be suppressed by input filter 0 4.7 4.0 4.7 4.7 4.0 0 250 4.0 100 1000 300 400 0 1.3 0.6 1.3 1.3 0.6 0 100 (1) (2) (2) Symbol FIGURE PARAMETER Fast-MODE MIN MAX UNIT MAX 400 0 0.9 300 300 400 50 kHz μS μS μS μS μS μS nS ns ns μS pF nS 20+0.1Cb 20+0.1Cb 0.6 0 Specifications subject to change without notice contact your sales representatives for the most recent information. 12 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Function Description The SM5964A is a stand-alone high-performance microcontroller designed for using in 3.3V ISP applications, such as LCD monitor, instrumentation, or high-end consumer applications. In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these applications. The SM5964A is a control-oriented CPU with on-chip program and data memory. It can be extended with external data memory up to 64K bytes. For system requiring extra capability, the SM5964A can be enhanced by using external memory and peripherals. The SM5964A has two software selectable modes of saving power consumption：IDLE and POWER- DOWN. The IDLE mode freezes the CPU while allowing the RAM, timer, serial ports and interrupt system to continue functioning. The POWER-DOWN mode save the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. The POWER-DOWN mode can be terminated by H/W reset, or by any one of the two external interrupt. CPU The CPU of SM5964A is compatible to standard 80C51. The structure of this CPU is shown as FIGURE 12. It contains Instruction Register (IR), Instruction Decoder, Program Counter (PC), Accumulator (ACC), B Register, and control logic. This CPU provides a 8-bits bi-direction bus to communicate with other blocks in the chip. The address and data are transferred through on the same 8-bits bus. PROG. ADDR. ACC IRQ RES CLK Timing & Reset CONTROL LOGIC TMP2 TMP1 PROGRAM ADDR.REGISTER BUFFER CTRL. BUS INSTRUCTION DECODER SP B Register ALU PROGRAM INCREMENT PROGRAM COUNTER PSW DPTR INSTRUCTION REGISTER DATA IN/OUT PCON POWER CTRL Signal Figure 12 The CPU structure CPU Timing The machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts for two oscillator periods. Thus a machine cycle takes 12 oscillator periods. Each state is divided into a PHASE1 half and a PHASE2 half. FIGURE 13 shows relationships between oscillator, phase, and S1-S6. Specifications subject to change without notice contact your sales representatives for the most recent information. 13 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded PHASE OSC (Xtal2) SEQUENCE P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 S1 S2 S3 S4 S5 S6 S1 S2 Figure 13 Sequences and Phases FIGURE 14 shows the fetch / execute sequences in states and phases for various kinds of instructions. Normally the program fetches are generated during each machine cycle, even if the instruction being executed doesn’t require it. If the instruction being executed doesn’t need more code bytes, the CPU simply ignores the extra fetch, and the PROGRAM COUNTER is incremented accordingly. Execution of a one-cycle instruction (FIGURE 14 A and B) begins during S1 of the machine cycle, when the OPCODE is latched into INSTRUCTION REGISTER. A second fetch occurs during S4 of the same machine cycle. Execution is completed at the end of S6 of this machine cycle. The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second cycle of a MOVX instruction. This is the only time program fetches are skipped. The fetch/execute sequence for MOVX instructions is shown in FIGURE 14 (D) The fetch / execute sequences are the same whether the PROGRAM MEMORY is internal or external to the chip. Execution times do not depend on whether the PROGRAM MEMORY is internal or external. FIGURE 15 shows the signals and timing involved in program fetches when the program memory is external. If PROGRAM MEMORY is external, the PROGRAM MEMORY READ STOBE (/PSEN) is normally activated twice per machine cycle, as shown in FIGURE 15(A). If an access external DATA MEMORY occurs, as shown in FIGURE 15(B), two (/PSEN) are SKIPPED, because the address and data bus are being used for DATA MEMORY access. Note that a DATA MEMORY bus cycle takes twice as much time as PROGRAM MEMORY bus cycle. FIGURE 15 shows the relative time of the address begin emitted at PORT0 and PORT2, and of ALE and /PSEN. ALE is used to latch the low address byte form PORT0 into the address latch. When CPU is executing from internal PROGRAM MEMORY, /PSEN is not activated, and program address are not emitted. However, ALE continues to be activated twice per machine cycle and so is available as clock output signal. Note, however, that ALE is skipped during the execution of the MOVX instruction. Specifications subject to change without notice contact your sales representatives for the most recent information. 14 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded A.) 1 byte, 1 Cycle Instruction S1 S2 S3 S4 S5 S6 S1 S2 Read OPCODE Read next OPCODE Discard Read next OPCODE again 1 machine cycle B.) 2 byte, 1 Cycle Instruction S1 S2 S3 S4 S5 S6 S1 S2 Read OPCODE Read 2’nd Byte Read next OPCODE 1 machine cycle C.) 1 byte, 2 Cycle Instruction S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 Read OPCODE 1’st cycle Read next OPCODE (Discard) 2’nd cycle ACCESS external memory DATA Read next OPCODE again D.) MOVX: 1 byte, 2 Cycle Instruction ADDR S1 S2 S3 S4 S5 S6 S1 No Fetch S2 S3 S4 No Fetch S5 S6 S1 S2 Read OPCODE Read next OPCODE (Discard) Read next OPCODE Again 1’st cycle 2’nd cycle Figure 14 Timing of various instructions Specifications subject to change without notice contact your sales representatives for the most recent information. 15 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded A.) Without MOVX One cycle S1 S2 S3 S4 ALE /PSEN /RD P2 PCH OUT S5 S6 S1 S2 One cycle S3 S4 S5 S6 S1 S2 PCH OUT PCH OUT PCH OUT P0 PCL OUT INST. IN PCL OUT INST. IN PCL OUT INST. IN PCL OUT INST. IN PCL OUT B.) With MOVX 1’st cycle S1 ALE /PSEN /RD P2 PCH OUT P2 or DPH out PCH OUT S2 S3 S4 S5 S6 S1 S2 2’nd cycle S3 S4 S5 S6 S1 S2 P0 PCL OUT INST. IN Addr. OUT Data. IN PCL OUT INST. IN PCL OUT Figure15: Bus cycle in external program memory mode Instruction Set The SM5964A uses the powerful instruction set of 80C51. It consists of 49 single-byte, 42 two-byte, and 15 three- byte instructions. Among them 63 instructions are executed in 1 machine-cycle, 46 instructions in 2 machine-cycles, and the multiply, 2 instructions in 4 machine-cycles. A summary of the instruction set is given in Table 4. Specifications subject to change without notice contact your sales representatives for the most recent information. 16 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Addressing Mode Notes on instruction set and address modes: Rn direct @Ri #data #data16 addr11 rel bit Register R7-R0 of the currently selected register bank. 8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)] 8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank 8-bits constant included in the instruction 16-bits constant included in the instruction 11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the same 2 K bytes page of program memory as the first byte of the following instruction. Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Direct addressed bit in internal data RAM or SFR Table 4: A Summary of the instruction set OPERATION A = A + Rn A = A + direct A = A + A = A + #data A = A + Rn + C A = A + direct + C A = A + @Ri + C A = A + #data + C A = A － Rn － C A = A － direct － C A = A － － C A = A－#data － C A=A+1 Rn = Rn + 1 direct = direct + 1 = + 1 A=A － 1 Rn = Rn － 1 direct = direct － 1 = － 1 DPTR = DPTR － 1 B:A = A × B A = INT (A/B) B = MOD (A/B) Decimal adjust ACC A .AND. Rn A .AND. direct A .AND. A .AND. #data direct .AND. A direct .AND. #data A .OR. Rn A .OR. direct A .OR. A .OR. #data direct .OR. A direct .OR. #data A .XOR. Rn A .XOR. direct A .XOR. A .XOR. #data direct .XOR. A direct .XOR. #data A=0 Mnemonic Arithmetic Instructions ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,direct ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A Rn direct @Ri A Rn direct @Ri DPTR AB AB BYTE 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 CYCLE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 DA A Logical Instructions ANL A,Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A Specifications subject to change without notice contact your sales representatives for the most recent information. 17 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded CPL A RL A RLC A RR A RRC A SWAP A Data Transfers Instructions MOV A,Rn MOV A,direct MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,direct MOV Rn,#data MOV direct,A MOV direct,Rn MOV direct,direct MOV direct,@Ri MOV direct,#data MOV @Ri,A MOV @Ri,direct MOV @Ri,#data MOV DPTR,#data16 MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH direct POP direct XCH A,Rn XCH A,direct XCH A,@Ri XCHD A,@Ri Boolean Instructions CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel Jump Instructions ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct,rel A = /A Rotate ACC Left 1 bit Rotate Left through Carry Rotate ACC Right 1 bit Rotate Right through Carry Swap Nibbles in A A = Rn A = direct A = A = #data Rn = A Rn = direct Rn = #data direct = A direct = Rn direct = direct direct = direct = #data = A = direct = #data DPTR = #data16 A = code memory[A+DPTR] A = code memory[A+PC] A = external memory[Ri] (8-bits address) A = external memory[DPTR] (16-bits address) external memory[Ri] = A (8-bits address) external memory[DPTR] = A (16-bits address) INC SP: MOV “@’SP’, < direct > MOV < direct >, “@SP”: DEC SP ACC and < Rn > exchange data ACC and < direct > exchange data ACC and < Ri > exchange data ACC and @Ri exchange low nibbles C=0 bit = 0 C=1 bit = 1 C = /C bit = /bit C = C .AND. bit C = C .AND. /bit C = C .OR. bit C = C .OR. /bit C = bit bit = C Jump if C= 1 Jump if C= 0 Jump if bit = 1 Jump if bit = 0 Jump if C = 1 Call Subroutine only at 2k bytes Address Call Subroutine in max 64K bytes Address Return from subroutine Return from interrupt Jump only at 2k bytes Address Jump to max 64K bytes Address Jump on at 256 bytes Jump to A+ DPTR Jump if A = 0 Jump if A ≠ 0 Jump if A ≠ < direct > 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 2 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Specifications subject to change without notice contact your sales representatives for the most recent information. 18 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded CJNZ CJNZ CJNZ DJNZ DJNZ NOP A, #data,rel Rn, #data,rel @Ri, #data,rel Rn,rel direct,rel Jump if A ≠ < #data > Jump if Rn ≠ < #data > Jump if @Ri ≠ < #data > Decrement and jump if Rn not zero Decrement and jump if direct not zero No Operation 3 3 3 2 3 1 2 2 2 2 2 1 Memory organization The central processing unit (CPU) manipulates operands in three memory spaces; there are 1024 bytes internal data memory (consisting of 256 bytes standard RAM and 768 bytes AUX-RAM) and 64K bytes internal/external program memory (see FIGURE 16) 64K 64K Overlapped space Internal FLASH memory /EA=1 External FLASH memory /EA=0 0080 DIRECT AND INDIRECT 0000 0000 0000 INDIRECT ONLY DIRECT (SFR) XRAM (OME=1) 02FF XRAM (OME=0) Program memory Internal DATA memory Figure 16 Memory organization of SM5964A External DATA memory Program memory The program memory of SM5964A consists of 64K bytes FLASH memory on chip. If during RESET, the /EA pin was held HIGH, the SM5964A does not execute out of the internal program memory. If the /EA pin was held LOW during RESET the SM5964A fetch all instructions from the external program memory. The FLASH memory of SM5964A can be programmed during the program is running by using ISP. Normally, a Writer is used for programming. The feature of FLASH memory is shown as following: READ: byte-wise WRITE: byte-wise within 30us (previously erased by a chip erase). ERASE: Full Erase (64K bytes) within 2 sec. Erased bytes contain FFH Endurance : 10K erase and write cycles each byte at TA=25℃ Retention : 10 years Program Code Security MOVC instruction executed from external program memory space will not be able to fetch internal codes from on chip program memory after the chip is protected on the Writer. Specifications subject to change without notice contact your sales representatives for the most recent information. 19 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Internal Data memory The Data memory of SM5964A consists of 1024 bytes internal data memory (256 bytes standard RAM and 768 bytes AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX Internal RAM Control Register (RCON, $85) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 RAMS1 Bit0 RAMS0 SM5964A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0). Pulse Width Modulation (PWM) The PWM output pins are P1.2 and P1.3. The PWM clock is {FOSC/ (2xDivider)}, the PWM output frequency is {(PWM clock)/32} at 5 bits resolution and {(PWM clock)/256} at 8 bits resolution. The PWM SFR has shown as below: PWMC [0:1] ($D3H and $D4H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 PBS Bit1 PFS1 Bit0 PFS0 PBS: when set, the PWM is 5 bits resolution. PFS [1:0]: The PWM clock divider select. PFS1 0 0 1 1 PFS0 0 1 0 1 PWM clock divider select 2 4 8 16 PWMD [0:1] ($B3H and $B4H) Bit7 PWMD.7 Bit6 PWMD.6 Bit5 PWMD.5 Bit4 PWMD.4 Bit3 PWMD.3 Bit2 PWMD.2 Bit1 PWMD.1 Bit0 PWMD.0 Two-Wire Series Interface (TWSI) The TWSI module uses the SCL (clock) and the SDA (data) line to communicate with external TWSI interface between other TWSI parts. The speed can up to 400K bps (max.) by software setting the TWSIFS [2:0]. The TWSI module used SFR shown as below TWSI Status Register: TWSIS ($C0H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RXIF TXIF TFIF NAKIF RXAK MASTER TXAK RXIF: The data Receive Interrupt Flag (RXIF) is set after the TWSIRxD (TWSI Receive Data Buffer) is loaded with a newly receive data. TXIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the TWSITxD (TWSI Transmit Data Buffer) is downloaded to the shift register or the TWSIA is downloaded to the shift register at Master Transmit mode. TFIF: The Transmit Fail Interrupt Flag is set when the data transmit fail. Specifications subject to change without notice contact your sales representatives for the most recent information. 20 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded NAKIF: The Non-acknowledge Interrupt Flag is only set in the master mode when there is no acknowledge bit detected after one byte data or calling address is transferred. RXAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has been received after the complete 8 bits data transmit on the bus. MASTER: This bit define this module is working at master mode. TXAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will set (NoAck) or clear (Ack) and transmit to master to indicate the receive status. TWSIA ($C1H) Bit7 Bit6 Bit5 Bit4 Bit3 TWSIA.7 TWSIA.6 TWSIA.5 TWSIA.4 TWSIA.3 TWSIA [7:1]: TWSI Address registers 7 bits. EXTADDR: Its only compare 4 bits MSB when set this bit. Bit2 TWSIA.2 Bit1 TWSIA.1 Bit0 EXTADDR TWSIC1 ($C2H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWSIE BusBusy TWSIFS2 TWSIFS1 TWSIFS0 TWSIE: enable TWSI module. BusBusy: When start condition is detected, this bit will set. When stop condition is detected, this bit will clear. TWSIFS [2:0]: The TWSI SCL speed divider select. TWSIFS [2:0] 000 001 010 011 100 101 110 111 Speed Xtal/32 Xtal/64(default) Xtal/128 Xtal/256 Xtal/512 Xtal/1024 Xtal/2048 Xtal/4096 TWSIC2 ($C3H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MATCH SRW RESTART MRW MATCH: When the first received data (following the START signal) in TWSIRxD register is matches with the address that address register (TWSIA) set, this bit will set. SRW: The slave mode read (received) or wrote (transmit) on the TWSI bus. When this bit is clear, the slave module received data on the TWSI bus (SDA). RESTART: This bit only set by master mode. The master will send a start signal then send TWSIA after the ACK signal when this bit setting. If TFIF was set (the NonACK signal was received), the master mode will release, and this bit will clear. MRW: This bit is determined the data transmit direction. And this bit will transmit to bus as bit0 at Address (Address is collection TWSIA [7:1] and MRW as 8 bits data). When clear this bit the master is in transmits mode and clear is in receive mode. TWSITXD ($C4) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWSITxD.7 TWSITxD.6 TWSITxD.5 TWSITxD.4 TWSITxD.3 TWSITxD.2 TWSITxD.1 TWSITxD.0 The data written into this register will be automatically downloaded to the shift register when the module detects a calling address is matched and the bit 0 of the received data is one (Slave transmit mode) or when the data in the shift register has been transmitted with received acknowledge bit (RXAK) =0 in transmit Specifications subject to change without notice contact your sales representatives for the most recent information. 21 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded mode. TWSIRXD ( $C5) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWSIRxD.7 TWSIRxD.6 TWSIRxD.5 TWSIRxD.4 TWSIRxD.3 TWSIRxD.2 TWSIRxD.1 TWSIRxD.0 The TWSI Receive Data Buffer (TWSIRxD) contains the last received data when the MATCH flag is one or the calling address from master when the MATCH flag is zero. The TWSIRxD register will be updated after a data byte is received and the previous received data had been read out, otherwise the TWSI module will pull down to SCL line to inhabit the next data transfer. It is a read-only register. The read operation of this register will clear the RXIF flag. After the RXIF flag is cleared, the register can load the received data again and set the RXIF flag to generate interrupt request for reading the newly received data. In-System Programming (ISP) The SM5964A can generator flash control signal by internal hardware circuit. That only need to put the ISP service code into ISP code area (4 Kbytes and divided by 8 zones) The area is set by lock-bit (N), the lock-bit number and ISP code area relation ship shown as below: Lock-bit number 1 2 3 4 5 6 7 8 ISP code area 512 bytes (from $FE00h to $FFFF) 1K bytes (from $FC00H to $FFFF) 1.5 K bytes (from $FA00H to $FFFF) 2 K bytes (from $F800H to $FFFF) 2.5 K bytes (from $F600H to $FFFF) 3 K bytes (from $F400H to $FFFF) 3.5 K bytes (from $F200H to $FFFF) 4 K bytes (from $F000H to $FFFF) There are three ways to into ISP code area: 1. Blank reset: Hardware reset with first flash address blank ($0000H = #FFH). 2. Execute the “LJMP” instruction. 3. By hardware setting: P2.6 P2.7 RST 10ms Or P4.3 RST 10ms 10ms 10ms The ISP register: Specifications subject to change without notice contact your sales representatives for the most recent information. 22 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded ISPFAH ($F4H) Bit7 Bit6 Bit5 Bit4 FA15 FA14 FA13 FA12 FA15 ~ FA8: flash address-high for ISP function Bit3 FA11 Bit2 FA10 Bit1 FA9 Bit0 FA8 ISPFAL ($F5H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 FA7 ~ FA0: flash address-low for ISP function The ISPFAH & ISPFAL provide the 16-bits flash memory address for ISP function. The flash memory address should not include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter will have no effect. ISPFD ($F6H) Bit7 Bit6 Bit5 Bit4 FD7 FD6 FD5 FD4 FD7 ~ FD0: flash data for ISP function The ISPFD provide the 8-bits data for ISP function. Bit3 FD3 Bit2 FD2 Bit1 FD1 Bit0 FD0 ISPC ($F7H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 START ISPF[1: 0]: ISP function select bit START: ISP function start bit = 1: start ISP function which indicated by bit 1, bit 0 (ISPF1, ISPF0) = 0: no operation Bit1 ISPF1 Bit0 ISPF0 The START bit is read-only by default, software must write three specific values 55H, AAH and 55H sequentially to the ISPFD register to enable the START bit write attribute. That is: Ex：Open ISP function: MOV ISPFD, #55H MOV ISPFD, #0AAH MOV ISPFD, #55H Any attempt to set START bit will not be allowed without the procedure above. After START bit set to 1 then the SM5964A hardware circuit will latch address and data bus and hold the program counter until the START bit reset to 0 when ISP function finished. User does not need to check START bit status by software method ISPF [1:0] 00 01 10 11 ISP function Byte Program Chip Protect Page erase (512 Bytes) Chip Erase ISPF[1:0]: ISP function select bits One page of flash memory is 512 bytes. To perform byte program / page erase ISP function, user need to specify flash address at first. When performing page erase function, SM5964A will erase entire page which flash address indicated by ISPFAH registers located within the page. To perform chip erase ISP function, SM5964A will erase all the flash program memory and data flash memory except the Specifications subject to change without notice contact your sales representatives for the most recent information. 23 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded ISP service program space if lock bit N been configured. Also, SM5964A will un-protect the flash memory automatically. To perform chip protect ISP function, all the flash memory will be read all zero. e.g. ISP service program to do the byte program - to program data of #22H to the address of the $1005H MOV ISPFD, #55H MOV ISPFD, #0AAH MOV ISPFD, #55H MOV SCONF, #04H MOV ISPFAH, #10H MOV ISPFAL, #05H MOV ISPFD, #22H MOV ISPFC, #80H ; open ISP function ; enable SM5964A ISP function ; set flash address-high, 10H ; set flash address-low, 05H ; set flash data to be programmed, data = 22H ; start to program data of 22H to the flash address of the $1005H ; after byte program finished, START bit of ISPC will reset to 0 automatically ; program counter then point to the next instruction The Power Down Wake Up (PDWU) function The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and PSEN pins are pulled low. The port pins output the values held by their respective SFRs. PCON ($87H) Bit7 Bit6 Bit5 Bit4 Bit3 SMOD GF1 SMOD: This bit set to ‘1’ to make the UART baud-rate double. GF1: General-purpose flag bit. GF0: General-purpose flag bit. PD: When set to ‘1’ , the MCU will into Power Down mode IDLE: When set to ‘1’ , the MCU will into IDLE mode Bit2 GF0 Bit1 PD Bit0 IDLE SCONF ($BFH) Bit4 PDWUE PDWUE: When set to ‘1’, enable the PDWU function. ISPE: When set to ‘1’, enable the ISP function. Bit7 Bit6 Bit5 Bit3 Bit2 ISPE Bit1 OME Bit0 ALEI IE ($A8H) Bit7 Bit6 Bit5 Bit4 EA ET2 ES0 EA: When set to ‘1’, enable interrupt global. ET2: When set to ‘1’, enable Timer2 interrupt. ES0: When set to ‘1’, enable UART interrupt. ET1: When set to ‘1’, enable Timer1 interrupt. EX1: When set to ‘1’, enable external interrupt 1. ET0: When set to ‘1’, enable Timer0 interrupt. EX0: When set to ‘1’, enable external interrupt 0. Bit3 ET1 Bit2 EX1 Bit1 ET0 Bit0 EX0 IE1 ($A9H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ETWSI Bit0 Specifications subject to change without notice contact your sales representatives for the most recent information. 24 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded ETWSI: When set to ‘1’, enable the TWSI interrupt. IFR ($AAH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 TWSIIF Bit0 TWSIIF: When set to ‘1’, enable the TWSI interrupt flag. TCON ($88H) Bit7 Bit6 Bit5 TF1 TR1 TF0 TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Timer 0 overflow flag. TR0: Timer 0 run control bit. IE1: External Interrupt 1 edge flag. IT1: Interrupt 1 type control bit. IE0: External Interrupt 0 edge flag. IT0: Interrupt 0 type control bit. Bit4 TR0 Bit3 IE1 Bit2 IT1 Bit1 IE0 Bit0 IT0 TMOD ($89H) Bit7 Bit6 Bit5 Bit4 GATE C/T M1 M0 Note: High 4 bits are Timer1, Low 4 bits are Timer0. Bit3 GATE Bit2 C/T Bit1 M1 Bit0 M0 GATE: Gating control when set. Timer/Counter “x” is enabled only while “INTx” pin is high and “TRx” control pin is set. when cleared Timer “x” is enabled whenever “TRx” control bit is set. C/T: Timer or Counter Selector cleared for Timer operation (input from in=ternal system clock.) Set for Counter operation (input from “Tx” input pin). M1 0 0 1 M0 0 1 0 Mode OPERATING 0 13-bit Timer Mode. 8-bit Timer/Counter THz with TLx as 5-bit prescaler. 1 16-bit Timer Mode. 16-bit Timer/Counters THx and TLx are cascaded; there is no prescaler. 2 8-bit Auto Reload. 8-bit auto-reload Timer/Counter THx holds a value which is to be reloaded into TLx each time it overflows. 3 Split Timer Mode (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/Counter 1 stopped. 1 1 IP ($B8H) Bit7 Bit6 Bit5 PT2 Bit4 PS0 Bit3 PT1 Bit2 PX1 Bit1 PT0 Bit0 PX0 PT2: Timer2 interrupt priority. PS0: UART interrupts priority. PT1: Timer1 interrupt priority. PX1: external interrupt 1 priority. PT0: Timer0 interrupt priority. Specifications subject to change without notice contact your sales representatives for the most recent information. 25 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded PX0: external interrupt 0 priority. IP1($B9H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 PTWSI Bit0 PTWSI: When set to ‘1’, enable the TWSI interrupt priority. The Priority structure and vector locations of interrupts: Source External interrupt 0 Timer 0 overflow External interrupt 1 Timer 1 overflow UART interrupt Timer 2 overflow TWSI Flag IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 RXIF+ TXIF+ TFIF+ NAKIF Priority level 1(highest) 2 3 4 5 6 7 Vector Address 03H 0BH 13H 1BH 23H 2BH 3BH T2MOD ($C9H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 T2OE Bit0 DCEN T2OE: Timer2 clock Output Enable bit. If set to 1, the Timer2 clock will output to P1.0. DCEN: Down Count Enable. When set this bit then allows Timer2 to be configured as an up/down counter. Application Reference X'tal C1 C2 R X'tal C1 C2 R Note: 3MHz 30 pF 30 pF open 16MHz 30 pF 30 pF open Valid for SM5964A 6MHz 9MHz 30 pF 30 pF 30 pF 30 pF open open 25MHz 15 pF 15 pF open XI 12MHz 22 pF 22 pF open C1 X'tal SM5964A R X2 C2 Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. Specifications subject to change without notice contact your sales representatives for the most recent information. 26 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded PDIP 40L (600mil) Package Information： Symbol A1 A2 b b1 b2 b3 c c1 D E E1 e eB L S Q1 θ Dimension in mm Min 0.254 3.683 0.356 0.356 1.016 1.016 0.203 0.203 52.07 14.99 13.69 － 15.75 2.921 1.727 1.651 0° Dimension in MIL Min 10 145 14 14 40 40 8 8 2050 590 539 － 620 115 68 65 0° Nom － 3.810 0.500 0.457 1.270 1.321 0.254 0.254 52.2 15.24 13.87 2.540 16.26 3.302 1.981 1.778 － Max － 3.937 0.660 0.508 1.524 1.626 0.432 0.356 52.32 15.49 13.94 － 16.76 3.683 2.235 1.905 10° Nom － 150 20 18 50 52 10 10 2055 600 546 100 640 130 78 70 － Max － 155 26 22 60 64 17 14 2060 610 549 － 660 145 88 75 10° Note: 1. Refer to JEDEC STD.MS-011(AC). 2. Dimension D and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D and E1 are maximum plastic body size dimension include mold mismatch. 3. Dimension b3 does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.2mm. Specifications subject to change without notice contact your sales representatives for the most recent information. 27 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded PLCC 44L Package Information： UNIT SYMBOL A A1 A2 B B1 c D D1 D2 E E1 E2 e y θ INCH(REF) 0.180(MAX) 0.024 ±0.005 0.105 ±0.005 0.018 + 0.004 - 0.002 0.028 + 0.004 - 0.002 0.010(TYP) 0.690 ±0.010 0.653 ±0.003 0.610 ±0.020 0.690 ±0.010 0.653 ±0.003 0.610 ±0.010 0.050(TYP) 0.003(MAX) 0~5° MM(BASE) 4.572(MAX) 0.52 ±0.14 2.667 ±0.127 0.457 + 0.102 - 0.051 0.711 + 0.102 - 0.051 0.254(TYP) 17.526 ±0.254 16.586 ±0.076 15.494 ±0.508 17.526 ±0.254 16.586 ±0.076 15.494 ±0.254 1.270(TYP) 0.076(MAX) 0~5° Specifications subject to change without notice contact your sales representatives for the most recent information. 28 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded QFP 44L(10x10x2.0mm) Package Information： Symbol A A1 A2 b b1 c Note: 1. Refer to JEDC STD.MS-022(AB). 2. Dimension E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side.E1 are maximum plastic body size dimension include mold mismatch . 3. Dimension b does not include dambar protrusion .Allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm. Dimension in mm Min － 0.05 1.90 0.29 0.29 0.11 0.11 13.00 9.90 － 0.73 1.50 － 0° Dimension in MIL Min － 2.1 74.8 11.4 11.4 4.3 4.3 512 390 － 28.7 59.1 － 0° Nom － 0.15 2.00 0.32 0.30 0.17 0.15 13.20 10.00 0.800 0.88 1.60 － － Max 2.45 0.25 2.10 0.45 0.41 0.23 0.19 13.40 10.10 － 1.03 1.70 0.076 7° Nom － 6.0 78.7 12.6 11.8 6.7 5.9 520 394 31.5 34.6 63.0 － － Max 964 9.6 82.7 17.7 16.1 9.1 7.5 528 398 － 40.6 66.9 3 7° c1 E E1 【e】 L L1 y θ Specifications subject to change without notice contact your sales representatives for the most recent information. 29 Ver 2.3 SM5964A 10/2006 SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded e MCU writer list Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang Rd., Nei Hu, Taipei, Taiwan, ROC. Web site: http://www.hilosystems.com.tw Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei Hsien, Taiwan, ROC Web site: http://www.leap.com.tw Xeltek Electronic Co., Ltd 338 Hongwu Road, Nanjing, China 210002 Web site: http://www.xeltek-cn.com Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number Lab Tool - 48XP (1 * 1) Lab Tool - 848 (1*8) Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw All - 11 (1*1) Gang - 08 (1*8) Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw Leap-48 (1*1) SU - 2000 (1*8) Tel:+86-25-84408399, 84543153-206 E-mail: xelclw@jlonline.com, xelgbw@jlonline.com Superpro/2000 (1*1) Superpro/280U (1*1) Superpro/L+(1*1) Specifications subject to change without notice contact your sales representatives for the most recent information. 30 Ver 2.3 SM5964A 10/2006