SM8958AC25

SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Product List SM8958AL25, 25MHz 32KB internal flash MCU SM8958AL33, 33MHz 32KB internal flash MCU SM8958AC25, 25MHz 32KB internal flash MCU SM8958AC40, 40MHz 32KB internal flash MCU Features Working Voltage: 3.0V ~ 3.6V For L Version. 4.5V ~ 5.5V For C Version. General 8052 family compatible 12 clocks per machine cycle 32K byte on chip program flash 1024 byte on-chip data RAM Three 16 bit Timers/Counters One Watch Dog Timer Four 8-bit I/O ports for PDIP package Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package Full duplex serial channel Bit operation instruction Industrial Level 8-bit Unsigned Division 8-bit Unsigned Multiply BCD arithmetic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and Power down mode Code protection function Low EMI (inhibit ALE) 5 channel SPWM function with P1.3 ~ P1.7 Description The SM8958A is an 8-bit single chip micro controller with 32KB on-chip flash and 1K byte RAM embedded. It is a derivative of the 8052 micro controller family. It has 5-channel SPWM build-in. With its hardware features and powerful instruction set, it’s straight forward to make it a versatile and cost effective controller for those applications which demand up to 32 I/O pins for PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 32K byte flash memory for program data. To program the on-chip flash memory, a commercial writer is available to do it in parallel programming method. Ordering Information yymmv SM8958AihhkL yy: year, ww: month v: version identifier{ , A, B,…} i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table} L:PB Free identifier {No text is Non-PB Free，”P”is PB Free} Postfix P J Q Package 40L PDIP 44L PLCC 44L QFP Pin / Pad Configuration Page 2 Page 2 Page 2 Dimension Page 20 Page 21 Page 22 Taiwan 6F, No.10-2 Li- Hsin 1st Road , Science-based Industrial Park, Hsinchu, Taiwan 30078 TEL: 886-3-567-1820 886-3-567-1880 FAX: 886-3-567-1891 886-3-567-1894 Specifications subject to change without notice contact your sales representatives for the most recent information. 1 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. Pin Configuration SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. 2 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Block Diagram Specifications subject to change without notice contact your sales representatives for the most recent information. 3 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Pin Description 40L PDIP Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44L QFP Pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 17 28 39 6 44L PLCC Pin# 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 23 34 1 12 Symbol P1.0/T2 P1.1/T2EX P1.2 P1.3/SPWM0 P1.4/SPWM1 P1.5/SPWM2 P1.6/SPWM3 P1.7/SPWM4 RES P3.0/RXD P3.1/TXD P3.2/#INT0 P3.3/#INT1 P3.4/T0 P3.5/T1 P3.6/#WR P3.7/#RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 #PSEN ALE #EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.0 P4.1 P4.2 P4.3 Active I/O i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o Names bit 0 of port 1 & timer 2 clock out bit 1 of port 1 & timer 2 control bit 2 of port 1 bit 3 of port 1 & SPWM channel 0 bit 4 of port 1 & SPWM channel 1 bit 5 of port 1 & SPWM channel 2 bit 6 of port 1 & SPWM channel 3 bit 7 of port 1 & SPWM channel 4 Reset bit 0 of port 3 & Receiver data bit 1 of port 3 & Transmit data bit 2 of port 3 & low true interrupt 0 bit 3 of port 3 & low true interrupt 1 bit 4 of port 3 & Timer 0 bit 5 of port 3 & Timer 1 bit 6 of port 3 & ext. memory write bit 7 of port 3 & ext. memory Read Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of ext. memory address bit 1 of port 2 & bit 9 of ext. memory address bit 2 of port 2 & bit 10 of ext. memory address bit 3 of port 2 & bit 11 of ext. memory address bit 4 of port 2 & bit 12 of ext. memory address bit 5 of port 2 & bit 13 of ext. memory address bit 6 of port 2 & bit 14 of ext. memory address bit 7 of port 2 & bit 15 of ext. memory address program storage enable address latch enable external access bit 7 of port 0 & data/address bit 7 of ext. memory bit 6 of port 0 & data/address bit 6 of ext. memory bit 5 of port 0 & data/address bit 5 of ext. memory bit 4 of port 0 & data/address bit 4 of ext. memory bit 3 of port 0 & data/address bit 3 of ext. memory bit 2 of port 0 & data/address bit 2 of ext. memory bit 1 of port 0 & data/address bit 1 of ext. memory bit 0 of port 0 & data/address bit 0 of ext. memory Drive Voltage, +5 Vcc bit 0 of Port 4 bit 1 of Port 4 bit 2 of Port 4 bit 3 of port 4 H L/L/- L Specifications subject to change without notice contact your sales representatives for the most recent information. 4 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Special Function Register (SFR) The address $80 to $FF can be accessed by direct addressing mode only. Address $80 to $FF is SFR area. The following table lists the SFRs which are identical to general 8052, as well as SM8958A Extension SFRs. Special Function Register (SFR) Memory Map $F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 $FF $F7 $EF $E7 $DF $D7 $CF $C7 $BF $B7 $AF $A7 $9F $97 $8F $87 B ACC P4 PSW T2CON IP P3 IE P2 SCON P1 TCON P0 T2MOD RCAP2L RCAP2H TL2 TH2 SCONF SBUF TMOD SP TL0 DPL SPWMC P1CON TL1 DPH SPWMD4 SPWMD0 TH0 SPWMD1 TH1 RCON SPWMD2 SPWMD3 WDTC WDTKEY PCON Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8958A Addr 85H 97H 9BH 9FH A3H A4H A5H A6H A7H ACH BFH C8H C9H D8H SFR RCON WDTKEY P1CON WDTC SPWMC SPWMD0 SPWMD1 SPWMD2 SPWMD3 SPWMD4 SCONF T2CON T2MOD P4 Reset 00H 00H 00000*** 0*0**000 ******00 00H 00H 00H 00H 00H 0*****00 00H ******00 ****1111 P4.3 P4.2 SPWMD04 SPWMD14 SPWMD24 SPWMD34 SPWMD44 WDR TF2 EXF2 RCLK TCLK EXEN2 TR2 SPWMD03 SPWMD13 SPWMD23 SPWMD33 SPWMD43 SPWMD02 SPWMD12 SPWMD22 SPWMD32 SPWMD42 SPWMD01 SPWMD11 SPWMD21 SPWMD31 SPWMD41 SPWMD00 SPWMD10 SPWMD20 SPWMD30 SPWMD40 BRM02 BRM12 BRM22 BRM32 BRM42 WDTKEY7 SPWME4 WDTE WDTKEY6 SPWME3 WDTKEY5 SPWME2 CLEAR WDTKEY4 SPWME1 WDTKEY3 SPWME0 PS2 PS1 SPFS1 BRM01 BRM11 BRM21 BRM31 BRM41 OME C/T2 T2OE P4.1 PS0 SPFS0 BRM00 BRM10 BRM20 BRM30 BRM40 ALEI CP/RL2 DCEN P4.0 WDTKEY2 7 6 5 4 3 2 1 RAMS1 WDTKEY1 0 RAMS0 WDTKEY0 Specifications subject to change without notice contact your sales representatives for the most recent information. 5 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Extension Function Description 1. Memory Structure The SM8958A is the general 8052 hardware core as a single chip micro controller. Its memory structure follows general 8052 structure. 1.1 Program Memory The SM8958A has 32K byte on-chip flash memory which used as general program memory. The address range for the 32K byte is $0000 to $7FFF. Note: The single flash block address structure for doing as well as program ROM flash. 1.2 Data Memory The SM8958A has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX). Specifications subject to change without notice contact your sales representatives for the most recent information. 6 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. 1.2.1 Data Memory - Lower 128 byte ($00 to $7F) Data Memory $00 to $FF is the same as 8052. The address $00 to $7F can be accessed by direct and indirect addressing modes. Address $00 to $1F is register area. Address $20 to $2F is memory bit area. Address $30 to $7F is for general memory area. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded 1.2.2 Data Memory - Higher 128 byte ($80 to $FF) The address $80 to $FF can be accessed by indirect addressing mode . Address $80 to $FF is data area. 1.2.3 Data Memory - Expanded 768bytes ($0000 to $02FF) From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by external direct addressing mode (by instruction MOVX): Specifications subject to change without notice contact your sales representatives for the most recent information. 7 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Internal RAM Control Register (RCON, $85) bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * Unused * Unused * RAMS1 R/W 0 bit-0 RAMS0 R/W 0 SM8958A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0). RAMS1 0 0 1 RAMS0 0 1 0 MOVX @Ri i=0,1 mapping to expended RAM address $0000 ~ $00FF $0100 ~ $01FF $0200 ~ $02FF The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure. System Control Register (SCONF, $BF) bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Unused * OME R/W 0 bit-0 ALEI R/W 0 WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow. WDR will be set to 1, The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened. OME : 768 bytes on-chip RAM enable bit. The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 0 (disable). ALEI : ALE output inhibit bit, to reduce EMI. Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin. Specifications subject to change without notice contact your sales representatives for the most recent information. 8 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded 1.3 I/O Pin Configuration The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can be used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a ‘1’ which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal port operation. Writing ‘1’ to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance input. The port 4 used as GPIO will has the same function as port 1, 2 and 3. 2. Port 4 for PLCC or QFP package : The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3. Port4 (P4, $D8) bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * P4.3 R/W 1 P4.2 R/W 1 P4.1 R/W 1 bit-0 P4.0 R/W 1 The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively. 3.Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway. Specifications subject to change without notice contact your sales representatives for the most recent information. 9 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is independent to the system frequency. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8958A been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. 3.1 Watch Dog Timer Registers: Watch Dog Timer Registers - WDT Control Register (WDTC, $9F) bit-7 WDTE Read / Write: Reset value: R/W 0 R * CLEAR R/W 0 Unused * Unused * PS2 R/W 0 PS1 R/W 0 bit-0 PS0 R/W 0 WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits PS [2:0] 000 001 010 011 100 101 110 111 Overflow Period (ms) 2.048 4.096 8.192 16.384 32.768 65.536 131.072 262.144 Watch Dog Key Register - (WDTKEY, $97H) bit-7 WDT KEY7 R/W 0 WDT KEY6 R/W 0 WDT KEY5 R/W 0 WDT KEY4 R/W 0 WDT KEY3 R/W 0 WDT KEY2 R/W 0 WDT KEY1 R/W 0 bit-0 WDT KEY0 R/W 0 Read / Write: Reset value: Specifications subject to change without notice contact your sales representatives for the most recent information. 10 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to enable the WDTC write attribute, That is MOV WDTKEY, # 1EH MOV WDTKEY, # 0E1H When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # 0E1H MOV WDTKEY, # 1EH Watch Dog Timer Register - System Control Register (SCONF, $BF) bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Unused * OME R/W 0 bit-0 ALEI R/W 0 The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened. 4. Reduce EMI Function The SM8958A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. 5. Specific Pulse Width Modulation (SPWM) The Specific Pulse Width Modulation (SPWM) module contain 1 kind of PWM sub module: SPWM (Specific PWM). SPWM has five 8-bit channels. 5.1 SPWM Function Description: The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock, Fosc/2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(SPFS[1:0]+1)]/32. Specifications subject to change without notice contact your sales representatives for the most recent information. 11 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded 5.2 SPWM Registers - P1CON, SPWMC, SPWMD[4:0] SPWM Registers - Port1 Configuration Register (P1CON, $9B) bit-7 SPWME4 Read / Write: Reset value: R/W 0 SPWME3 R/W 0 SPWME2 R/W 0 SPWME1 R/W 0 SPWME0 R/W 0 Unused * Unused * bit-0 Unused * SPWME[4:0] : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset. SPWM Registers -SPWM Control Register (SPWMC, $A3) bit-7 Unused Read / Write: Unused Unused Unused Unused Unused SPFS1 R/W 0 bit-0 SPFS0 R/W 0 Reset value: * * * * * * SPFS[1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock. SPFS1 0 0 1 1 SPFS0 0 1 0 1 Divider 2 4 8 16 SPWM clock, Fosc=20MHz 10MHz 5MHz 2.5MHz 1.25MHz SPWM clock, Fosc=24MHz 12MHz 6MHz 3MHz 1.5MHz SPWM Registers -SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4) bit-7 SPWMD [4:0]4 R/W 0 SPWMD [4:0]3 R/W 0 SPWMD [4:0]2 R/W 0 SPWMD [4:0]1 R/W 0 SPWMD [4:0]0 R/W 0 BRM [2:0]2 R/W 0 BRM [2:0]1 R/W 0 bit-0 BRM [2:0]0 R/W 0 Read / Write: Reset value: SPWMD[4:0] : content of SPWM Data Register. It determines duty cycle of SPWM output waveform. BRM[2:0] : will insert certain narrow pulses among an 8-SPWM-cycle frame Specifications subject to change without notice contact your sales representatives for the most recent information. 12 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded N = BRM[2:0] 000 001 010 011 100 101 110 111 Example of SPWM timing diagram: MOV SPWMC , #03H MOV SPWMD0 , #83H MOV P1CON , #08H Number of SPWM cycles inserted in an 8-cycle frame 0 1 2 3 4 5 6 7 ; Set output frequency (Divider = 16) ; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3 ; Enable P1.3 as SPWM output pin (narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3) SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1) The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32 If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz Specifications subject to change without notice contact your sales representatives for the most recent information. 13 Ver 2.1 SM8958A 08/2006 SyncMOS Technologies International, Inc. SM8958A 8-Bits Micro-controller With 32KB flash & 1KB RAM embedded Operating Conditions Symbol TA VCC5 VCC3 Fosc 25 Fosc 40 Description Operating temperature Supply voltage Supply voltage Oscillator Frequency Oscillator Frequency Min. -40 4.5 3 3.0 3.0 Typ. 25 5.0 3.3 25 40 Max. 85 5.5 3.6 25 40 Unit. ℃ Remarks Ambient temperature under bias For C Version For L Version For 5V, 3.3V application For 5V application V V MHz MHz DC Characteristics (TA = -40 degree C to 85 degree C, Vcc = 3.0V to 5.5V) Symbol VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current Valid port 0,1,2,3,4,#EA RES, XTAL1 port 0,1,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 1,2,3,4 port 0 port 1,2,3,4,ALE,#PSEN port 1,2,3,4 port 1,2,3,4 port 0, #EA RES Vdd Min. -0.5 0 2.0 70%Vcc Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45 Unit V V V V V V V V V V Test Conditions 2.4 90%Vcc 2.4 90%Vcc -75 -650 ±10 50 300 10 20 6.5 50 IOL=8mA (5V) / IOL=6mA (3.3V) IOL=6.5mA (5V) / IOL=5mA (3.3V) IOH=-800uA (only for VCC =5V) IOH=-80uA IOH=-60uA (only for VCC =5 V) IOH=-10uA Vin=0.45V Vin=2.0V 0.45V