CC1111F32RSPR

CC1110Fx / CC1111Fx Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller Applications • Low-power SoC wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands • Wireless alarm and security systems • Industrial monitoring and control • Wireless sensor networks • • • • AMR – Automatic Meter Reading Home and building automation Low power telemetry CC1111Fx: USB dongles Product Description The CC1110Fx/CC1111Fx is a true low-power sub1 GHz system-on-chip (SoC) designed for lowpower wireless applications. The CC1110Fx/CC1111Fx combines the excellent performance of the state-of-the-art RF transceiver CC1101 with an industry-standard enhanced 8051 MCU, up to 32 kB of in-system programmable flash memory and up to 4 kB of RAM, and many other powerful features. The small 6x6 mm package makes it very suited for applications with size limitations. The CC1110Fx/CC1111Fx is highly suited for systems where very low power consumption is required. This is ensured by several advanced low-power operating modes. The CC1111Fx adds a full-speed USB 2.0 interface to the feature set of the CC1110Fx. Interfacing to a PC using the USB interface is quick and easy, and the high data rate (12 Mbps) of the USB interface avoids the bottlenecks of RS-232 or low-speed USB interfaces. DIGITAL ANALOG MIXED VDD (2.0 - 3.6 V) DCOUPL RESET_N XOSC_Q2 XOSC_Q1 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 DP DM RF_P RF_N Key Features • Radio o o o o o o o o o o High-performance RF transceiver based on the market-leading CC1101 Excellent receiver selectivity and blocking performance High sensitivity (-110 dBm at 1.2 kBaud) Programmable data rate up to 500 kBaud Programmable output power up to +10 dBm for all supported frequencies Frequency range: 300-348 MHz, 391-464 MHz and 782-928 MHz Digital RSSI / LQI support Low current consumption (RX: 16.2 mA @ 1.2 kBaud, TX: 16 mA @ -6 dBm output power) 0.3 µA in PM3 (operating mode with the lowest power consumption, only external interrupt wakeup) 0.5 µA in PM2 (operating mode with the second lowest power consumption, timer or external interrupt wakeup) • MCU, Memory, and Peripherals o o o o o o o o o o o o o o o High performance and low power 8051 microcontroller core. Powerful DMA functionality 8/16/32 KB in-system programmable flash, and 1/2/4 KB RAM Full-Speed USB Controller with 1 KB FIFO (CC1111Fx ) 128-bit AES security coprocessor 7-12 bit ADC with up to eight inputs 2 I S interface Two USARTs 16-bit timer with DSM mode Three 8-bit timers Hardware debug support 21 (CC1110Fx ) or 19 (CC1111Fx ) GPIO pins SW compatible with CC2510Fx/CC2511Fx Wide supply voltage range (2.0V – 3.6V) RoHS compliant 6x6 mm QLP36 package • Low Power • General SWRS033E Page 1 of 239 CC1110Fx / CC1111Fx Table of Contents 1 2 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 5 5.1 5.2 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 8 9 9.1 9.2 10 10.1 10.2 10.3 10.4 10.5 10.6 11 11.1 11.2 11.3 11.4 11.5 12 12.1 12.2 12.3 12.4 ABBREVIATION ...................................................................................................................................... 4 REGISTER CONVENTIONS .................................................................................................................. 5 KEY FEATURES (IN MORE DETAILS) .............................................................................................. 6 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER....................................... 6 8/16/32 KB NON-VOLATILE PROGRAM MEMORY AND 1/2/4 KB DATA MEMORY ........................................ 6 FULL-SPEED USB CONTROLLER (CC1111FX )................................................................................................. 6 I2S INTERFACE .............................................................................................................................................. 6 HARDWARE AES ENCRYPTION/DECRYPTION ............................................................................................... 6 PERIPHERAL FEATURES ................................................................................................................................ 6 LOW POWER ................................................................................................................................................. 6 SUB-1 GHZ RADIO WITH BASEBAND MODEM .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 8 OPERATING CONDITIONS .................................................................................................................. 8 CC1110FX OPERATING CONDITIONS ............................................................................................................... 8 CC1111FX OPERATING CONDITIONS ............................................................................................................... 8 GENERAL CHARACTERISTICS.......................................................................................................... 9 ELECTRICAL SPECIFICATIONS ...................................................................................................... 10 CURRENT CONSUMPTION ........................................................................................................................... 10 RF RECEIVE SECTION ................................................................................................................................. 14 RF TRANSMIT SECTION .............................................................................................................................. 18 CRYSTAL OSCILLATORS ............................................................................................................................. 20 32.768 KHZ CRYSTAL OSCILLATOR ........................................................................................................... 21 LOW POWER RC OSCILLATOR .................................................................................................................... 21 HIGH SPEED RC OSCILLATOR .................................................................................................................... 22 FREQUENCY SYNTHESIZER CHARACTERISTICS ........................................................................................... 22 ANALOG TEMPERATURE SENSOR ............................................................................................................... 23 7-12 BIT ADC............................................................................................................................................. 23 CONTROL AC CHARACTERISTICS ............................................................................................................... 25 SPI AC CHARACTERISTICS ......................................................................................................................... 26 DEBUG INTERFACE AC CHARACTERISTICS ................................................................................................ 27 PORT OUTPUTS AC CHARACTERISTICS ...................................................................................................... 27 TIMER INPUTS AC CHARACTERISTICS ........................................................................................................ 28 DC CHARACTERISTICS ............................................................................................................................... 28 PIN AND I/O PORT CONFIGURATION ............................................................................................ 29 CIRCUIT DESCRIPTION ..................................................................................................................... 33 CPU AND PERIPHERALS ............................................................................................................................. 34 RADIO ........................................................................................................................................................ 36 APPLICATION CIRCUIT ..................................................................................................................... 36 BIAS RESISTOR ........................................................................................................................................... 36 BALUN AND RF MATCHING ........................................................................................................................ 36 CRYSTAL .................................................................................................................................................... 36 USB (CC1111FX) .......................................................................................................................................... 37 POWER SUPPLY DECOUPLING ..................................................................................................................... 37 PCB LAYOUT RECOMMENDATIONS ............................................................................................................ 40 8051 CPU .................................................................................................................................................. 41 8051 INTRODUCTION .................................................................................................................................. 41 MEMORY .................................................................................................................................................... 42 CPU REGISTERS ......................................................................................................................................... 54 INSTRUCTION SET SUMMARY ..................................................................................................................... 56 INTERRUPTS................................................................................................................................................ 61 DEBUG INTERFACE............................................................................................................................. 71 DEBUG MODE ............................................................................................................................................. 71 DEBUG COMMUNICATION........................................................................................................................... 71 DEBUG LOCK BIT ....................................................................................................................................... 72 DEBUG COMMANDS.................................................................................................................................... 73 SWRS033E Page 2 of 239 CC1110Fx / CC1111Fx 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 13.15 13.16 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.12 14.13 14.14 14.15 14.16 14.17 14.18 14.19 15 15.1 16 17 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 22 23 PERIPHERALS....................................................................................................................................... 77 POWER MANAGEMENT AND CLOCKS.......................................................................................................... 77 RESET ......................................................................................................................................................... 84 FLASH CONTROLLER .................................................................................................................................. 85 I/O PORTS ................................................................................................................................................... 91 DMA CONTROLLER ................................................................................................................................. 102 16-BIT TIMER, TIMER 1............................................................................................................................. 114 MAC TIMER (TIMER 2) ............................................................................................................................ 126 SLEEP TIMER ............................................................................................................................................ 128 8-BIT TIMERS, TIMER 3 AND TIMER 4 ....................................................................................................... 131 ADC......................................................................................................................................................... 141 RANDOM NUMBER GENERATOR ............................................................................................................... 147 AES COPROCESSOR .................................................................................................................................. 149 WATCHDOG TIMER ................................................................................................................................... 151 USART .................................................................................................................................................... 153 I2S ............................................................................................................................................................ 162 USB CONTROLLER ................................................................................................................................... 169 RADIO.................................................................................................................................................... 185 COMMAND STROBES ................................................................................................................................ 185 RADIO REGISTERS .................................................................................................................................... 187 INTERRUPTS.............................................................................................................................................. 187 TX/RX DATA TRANSFER ......................................................................................................................... 189 DATA RATE PROGRAMMING ..................................................................................................................... 190 RECEIVER CHANNEL FILTER BANDWIDTH................................................................................................ 190 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION ............................................................ 191 PACKET HANDLING HARDWARE SUPPORT ............................................................................................... 192 MODULATION FORMATS........................................................................................................................... 195 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ......................................................... 196 FORWARD ERROR CORRECTION WITH INTERLEAVING .............................................................................. 199 RADIO CONTROL ...................................................................................................................................... 200 FREQUENCY PROGRAMMING .................................................................................................................... 203 VCO......................................................................................................................................................... 203 OUTPUT POWER PROGRAMMING .............................................................................................................. 204 SHAPING AND PA RAMPING ..................................................................................................................... 204 SELECTIVITY ............................................................................................................................................ 206 SYSTEM CONSIDERATIONS AND GUIDELINES ............................................................................................ 206 RADIO REGISTERS .................................................................................................................................... 209 VOLTAGE REGULATORS ................................................................................................................ 226 VOLTAGE REGULATOR POWER-ON ........................................................................................................... 226 RADIO TEST OUTPUT SIGNALS..................................................................................................... 226 REGISTER OVERVIEW ..................................................................................................................... 227 PACKAGE DESCRIPTION (QLP 36)................................................................................................ 231 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 36) .......................................................................... 232 SOLDERING INFORMATION........................................................................................................................ 232 TRAY SPECIFICATION ............................................................................................................................... 232 CARRIER TAPE AND REEL SPECIFICATION ................................................................................................ 233 ORDERING INFORMATION............................................................................................................. 234 REFERENCES ...................................................................................................................................... 235 GENERAL INFORMATION............................................................................................................... 236 DOCUMENT HISTORY ............................................................................................................................... 236 PRODUCT STATUS DEFINITIONS ............................................................................................................... 237 ADDRESS INFORMATION ................................................................................................................ 238 TI WORLDWIDE TECHNICAL SUPPORT..................................................................................... 238 SWRS033E Page 3 of 239 CC1110Fx / CC1111Fx 1 ∆Σ ADC AES AGC ARIB ASK BCD BER BOD CBC CBC-MAC CCA CCM CFB CFR CMOS CPU CRC CTR DAC DMA DSM ECB EM ENOB EP{0-5} ESD ESR ETSI FCC FIFO GPIO HSSD HW I/O I/Q IS IF IOC ISM ISR IV JEDEC KB kbps 2 Abbreviation Delta-Sigma Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control Association of Radio Industries and Businesses Amplitude Shift Keying Binary Coded Decimal Bit Error Rate Brown Out Detector Cipher Block Chaining Cipher Block Chaining Message Authentication Code Clear Channel Assessment Counter mode + CBC-MAC Cipher Feedback Code of Federal Regulations Complementary Metal Oxide Semiconductor Central Processing Unit Cyclic Redundancy Check Counter mode (encryption) Digital to Analog Converter Direct Memory Access Delta-Sigma Modulator Electronic Code Book Evaluation Module Effective Number of Bits USB Endpoints 0 – 5 Electro Static Discharge Equivalent Series Resistance European Telecommunications Standard Institute Federal Communications Commision First In First Out General Purpose Input / Output High Speed Serial Debug HardWare Input / Output In-phase / Quadrature-phase Inter-IC Sound Intermediate Frequency I/O Controller Industrial, Scientific and Medical Interrupt Service Routine Initialization Vector Joint Electron Device Engineering Council Kilo Bytes (1024 bytes) kilo bits per second LFSR LNA LO LQI LSB MAC MCU MISO MOSI MSB NA OFB OOK PA PCB PER PLL PM{0-3} PMC POR PQI PWM QLP RAM RCOSC RF RoHS RSSI RX SCK SFD SFR SINAD SPI SRAM SW T/R TX UART USART USB VCO VGA WDT XOSC Linear Feedback Shift Register Low-Noise Amplifier Local Oscillator Link Quality Indication Least Significant Bit / Byte Medium Access Control Microcontroller Unit Master In Slave Out Master Out Slave In Most Significant Bit / Byte Not Applicable Output Feedback (encryption) On-Off Keying Power Amplifier Printed Circuit Board Packet Error Rate Phase Locked Loop Power Mode 0-3 Power Management Controller Power On Reset Preamble Quality Indicator Pulse Width Modulator Quad Leadless Package Random Access Memory RC Oscillator Radio Frequency Restriction on Hazardous Substances Receive Signal Strength Indicator Receive Serial Clock Start of Frame Delimiter Special Function Register Signal-to-noise and distortion ratio Serial Peripheral Interface Static Random Access Memory SoftWare Transmit / Receive Transmit Universal Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Serial Bus Voltage Controlled Oscillator Variable Gain Amplifier Watchdog Timer Crystal Oscillator SWRS033E Page 4 of 239 CC1110Fx / CC1111Fx 2 Register Conventions Each SFR is described in a separate table. The table heading is given in the following format: REGISTER NAME (SFR Address) - Register Description. Each RF register is described in a separate table. The table heading is given in the following format: XDATA Address: REGISTER NAME - Register Description All register descriptions include a symbol denoted R/W describing the accessibility of each bit in the register. The register values are always given in binary notation unless prefixed by ‘0x’, which indicates hexadecimal notation. Symbol R/W R R0 R1 W W0 W1 H0 H1 Access Mode Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 Hardware clear Hardware set Table 1: Register Bit Conventions SWRS033E Page 5 of 239 CC1110Fx / CC1111Fx 3 3.1 Key Features (in more details) High-Performance and Low-Power 8051-Compatible Microcontroller • Optimized 8051 core which typically gives 8x the performance of a standard 8051 • Two data pointers • In-circuit interactive debugging is supported by the IAR Embedded Workbench through a simple two-wire serial interface • SW compatible with CC2510Fx/CC2511Fx 3.6 Peripheral Features • Powerful DMA Controller • Power On Reset/Brown-Out Detection • ADC with eight individual input channels, single-ended or differential (CC1111Fx has six channels) and configurable resolution • Programmable watchdog timer • Five timers: one general 16-bit timer with DSM mode, two general 8-bit timers, one MAC timer, and one sleep timer • Two programmable USARTs for master/slave SPI or UART operation • 21 configurable general-purpose digital I/O-pins (CC1111Fx has 19) • Random number generator 3.7 Low Power • Four flexible power modes for reduced power consumption • System can wake up on external interrupt or when the Sleep Timer expires • 0.5 µA current consumption in PM2, where external interrupts or the Sleep Timer can wake up the system • 0.3 µA current consumption in PM3, where external interrupts can wake up the system • Low-power fully static CMOS design • System clock source is either a high speed crystal oscillator (26 – 27 MHz for CC1110Fx and 48 MHz for CC1111Fx) or a high speed RC oscillator (13 – 13.5 MHz for CC1110Fx and 12 MHz for CC1111Fx). The high speed crystal oscillator must be used when the radio is active. • Clock source for ultra-low power operation can be either a low-power RC oscillator or an optional 32.768 kHz crystal oscillator • Very fast transition to active mode from power modes enables ultra low average power consumption in low duty-cycle systems 3.8 Sub-1 GHz Radio with Baseband Modem • Based on the industry leading CC1101 radio core • Few external components: No external filters or RF switch needed, on-chip frequency synthesizer 3.2 8/16/32 KB Non-volatile Program Memory and 1/2/4 kB Data Memory • 8, 16, or 32 KB of non-volatile flash memory, in-system programmable through a simple two-wire interface or by the 8051 core • Minimum flash memory endurance: 1000 write/erase cycles • Programmable read and write lock of portions of flash memory for software security • 1, 2, or 4 kB of internal SRAM 3.3 Full-Speed USB Controller (CC1111Fx ) • 5 bi-directional endpoints in addition to control endpoint 0 • Full-Speed, 12 Mbps transfer rate • Support for Bulk, Interrupt, and Isochronous endpoints • 1024 bytes of dedicated endpoint FIFO memory • 8 – 512 byte data packet size supported • Configurable FIFO size for IN and OUT direction of endpoint 3.4 I2S Interface • Industry standard I2S interface for transfer of digital audio data • Full duplex • Mono and stereo support • Configurable sample rate and sample size • Support for µ-law compression and expansion • Typically used to connect to external DAC or ADC 3.5 Hardware AES Encryption/Decryption • 128-bit AES supported in hardware coprocessor SWRS033E Page 6 of 239 CC1110Fx / CC1111Fx • Flexible support for packet oriented systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling • Supports use of DMA for both RX and TX resulting in minimal CPU intervention even on high data rates • Programmable channel filter bandwidth • 2-FSK, GFSK, MSK, ASK, and OOK modulation formats supported • Optional automatic whitening and dewhitening of data • Programmable Carrier Sense (CS) indicator • Programmable Preamble Quality Indicator (PQI) for detecting preambles and improved protection against sync word detection in random noise • Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) • Support for per-package Link Quality Indication (LQI) SWRS033E Page 7 of 239 CC1110Fx / CC1111Fx 4 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Supply voltage (VDD) Voltage on any digital pin Voltage on the pins RF_P, RF_N and DCOUPL Voltage ramp-up rate Input RF level Storage temperature range Solder reflow temperature ESD CC1110Fx ESD CC1110Fx ESD CC1111x ESD CC1111x -50 Min -0.3 -0.3 -0.3 Max 3.9 VDD + 0.3, max 3.9 2.0 120 +10 150 260 1000 750 750 750 Units V V V kV/µs dBm °C °C V V V V Device not programmed According to IPC/JEDEC J-STD-020D According to JEDEC STD 22, method A114, Human Body Model (HBM) According to JEDEC STD 22, C101C, Charged Device Model (CDM) According to JEDEC STD 22, method A114, Human Body Model (HBM) According to JEDEC STD 22, C101C, Charged Device Model (CDM) Condition All supply pins must have the same voltage Table 2: Absolute Maximum Ratings Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. 5 5.1 Operating Conditions CC1110Fx Operating Conditions The operating conditions for CC1110Fx are listed in Table 3 below. Parameter Operating ambient temperature, TA Operating supply voltage (VDD) Min -40 2.0 Max 85 3.6 Unit °C V All supply pins must have the same voltage Condition Table 3: Operating Conditions for CC1110Fx 5.2 CC1111Fx Operating Conditions The operating conditions for CC1111Fx are listed in Table 4 below. Parameter Operating ambient temperature, TA Operating supply voltage (VDD) Min 0 3.0 Max 85 3.6 Unit °C V All supply pins must have the same voltage Condition Table 4: Operating Conditions for CC1111Fx SWRS033E Page 8 of 239 CC1110Fx / CC1111Fx 6 General Characteristics Min Typ Max Unit Condition/Note TA = 25 °C, VDD = 3.0 V if nothing else stated Parameter Radio part Frequency range 300 391 782 Data rate 1.2 1.2 26 348 464 928 500 250 500 MHz MHz MHz kBaud kBaud kBaud 2-FSK (500 kBaud only characterized @ 915 MHz on CC1110Fx) GFSK, OOK, and ASK Shaped) MSK (also known as differential offset QPSK) – 500 kBaud only characterized @ 915 MHz Optional Manchester encoding (the data rate in kbps will be half the baud rate) Wake-Up Timing PM1 Active Mode 4 µs Digital regulator on. HS RCOSC and high speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running. SLEEP.OSC_PD=1 and CLKCON.OSC=1 PM2 Active Mode 100 µs Digital regulator off. HS RCOSC and high speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running SLEEP.OSC_PD=1 and CLKCON.OSC=1 PM3 Active Mode 100 µs Digital regulator off. No crystal oscillators or RC oscillators are running. SLEEP.OSC_PD=1 and CLKCON.OSC=1 Table 5: General Characteristics SWRS033E Page 9 of 239 CC1110Fx / CC1111Fx 7 7.1 Electrical Specifications Current Consumption TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference design ([1]). Parameter Active mode, full speed (high speed 1 crystal oscillator) . Low CPU activity. 5.0 4.8 mA mA Min Typ Max Unit Condition Digital regulator on. High speed crystal oscillator and low power RCOSC running. No peripherals running. Low CPU activity: No flash access (i.e. only cache hit), no RAM access System clock running at 26 MHz. System clock running at 24 MHz. CC1111Fx runs on 48 MHz crystal giving 24 MHz system clock Active mode, full speed (HS 1 RCOSC) . Low CPU activity. 2.5 mA System clock running at 13 MHz. Digital regulator on. HS RCOSC and low power RCOSC running. No peripherals running. Low CPU activity: No flash access (i.e. only cache hit), no RAM access Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1) 19 19.5 16.2 19 19.4 19 16.2 19 20 21 17.2 20 20 1 Active mode with radio in RX, 315 MHz mA mA mA mA mA mA mA mA mA mA mA mA mA 1.2 kBaud, input at sensitivity limit, system clock at 26 MHz. 1.2 kBaud, input at sensitivity limit, system clock at 24 MHz 1.2 kBaud, input at sensitivity limit, system clock at 203 kHz. 1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz 1.2 kBaud, input well above sensitivity limit, system clock at 24 MHz 38.4 kBaud, input at sensitivity limit, system clock at 26 MHz. 38.4 kBaud, input at sensitivity limit, system clock at 203 kHz. 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz. 250 kBaud, input at sensitivity limit, system clock at 26 MHz 250 kBaud, input at sensitivity limit, system clock at 24 MHz. 250 kBaud, input at sensitivity limit, system clock at 1.625 MHz. 250 kBaud, input well above sensitivity limit, system clock at 26 MHz. 250 kBaud, input well above sensitivity limit, system clock at 24 MHz. Note: In order to reduce the current consumption in active mode, the clock speed can be reduced by setting CLKCON.CLKSPD ≠ 000 (see section 13.1 for details). Figure 1 shows typical current consumption in active mode for different clock speeds SWRS033E Page 10 of 239 CC1110Fx / CC1111Fx Parameter Active mode with radio in RX, 433 MHz 19.8 19.7 17.1 19.8 19.7 19.8 17.1 19.8 20.5 21.5 18.1 20.5 20.2 mA mA mA mA mA mA mA mA mA mA mA mA mA Min Typ Max Unit Condition Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1) 1.2 kBaud, input at sensitivity limit, system clock at 26 MHz. 1.2 kBaud, input at sensitivity limit, system clock at 24 MHz. 1.2 kBaud, input at sensitivity limit, system clock at 203 kHz. 1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz. 1.2 kBaud, input well above sensitivity limit, system clock at 24 MHz. 38.4 kBaud, input at sensitivity limit, system clock at 26 MHz. 38.4 kBaud, input at sensitivity limit, system clock at 203 kHz 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz. 250 kBaud, input at sensitivity limit, system clock at 26 MHz. 250 kBaud, input at sensitivity limit, system clock at 24 MHz. 250 kBaud, input at sensitivity limit, system clock at 1.625 MHz. 250 kBaud, input well above sensitivity limit, system clock at 26 MHz. 250 kBaud, input well above sensitivity limit, system clock at 24 MHz See Figure 2 for typical variation over operating conditions Active mode with radio in RX, 868, 915 MHz 19.7 17.0 18.7 19.7 17.0 18.7 20.4 18.0 19.1 Active mode with radio in TX, 315 MHz 31.5 19 18 mA mA mA mA mA mA mA mA mA mA mA mA Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1). 24MHz system clock not measured 1.2 kBaud, input at sensitivity limit, system clock at 26 MHz. 1.2 kBaud, input at sensitivity limit, system clock at 203 kHz. 1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz. 38.4 kBaud, input at sensitivity limit, system clock at 26 MHz. 38.4 kBaud, input at sensitivity limit, system clock at 203 kHz. 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz. 250 kBaud, input at sensitivity limit, system clock at 26 MHz. 250 kBaud, input at sensitivity limit, system clock at 1.625 MHz. 250 kBaud, input well above sensitivity limit, system clock at 26 MHz. System clock running at 26 MHz or 24MHz. Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode +10 dBm output power (PA_TABLE0=0xC2) 0 dBm output power (PA_TABLE0=0x51) -6 dBm output power (PA_TABLE0=0x2A) SWRS033E Page 11 of 239 CC1110Fx / CC1111Fx Parameter Active mode with radio in TX, 433 MHz 33.5 20 19 Active mode with radio in TX, 868, 915 MHz 36.2 21 20 Power mode 0 Power mode 1 4.3 220 mA mA mA mA µA mA mA mA Min Typ Max Unit Condition System clock running at 26 MHz or 24MHz. Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode +10 dBm output power (PA_TABLE0=0xC0) 0 dBm output power (PA_TABLE0=0x60) -6 dBm output power (PA_TABLE0=0x2A) System clock running at 26 MHz or 24MHz. Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode +10 dBm output power (PA_TABLE0=0xC2). See Table 7 for typical variation over operating conditions 0 dBm output power (PA_TABLE0=0x50) -6 dBm output power (PA_TABLE0=0x2B) Same as active mode, but the CPU is not running (see 13.1.2.2 for details). System clock at 26 MHz or 24MHz Digital regulator on. HS RCOSC and high speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running (see 13.1.2.3 for details) Digital regulator off. HS RCOSC and high speed crystal oscillator off. Low power RCOSC running (see 13.1.2.4 for details) Digital regulator off. No crystal oscillators or RC oscillators are running (see 13.1.2.5 for details) Add to the figures above if the peripheral unit is activated Power mode 2 Power mode 3 Peripheral Current Consumption Timer 1 Timer 2 Timer 3 Timer 4 ADC 0.5 0.3 1.0 µA µA 2.7 1.3 1.6 2 1.2 µA/MHz µA/MHz µA/MHz µA/MHz mA When running When running When running When running When converting Table 6: Current Consumption SWRS033E Page 12 of 239 CC1110Fx / CC1111Fx Current consumption Active Mode. No Peripherals Running. fxosc = 26MHz 6,0 5,0 4,0 Current [mA] 3,0 2,0 1,0 0,0 0246 HS XOSC HS RCOSC 8 10 12 14 16 18 20 22 24 26 28 Clock Speed [MHz] Measurements done for all valid CLKCON.CLKSPD settings (000 – 111 for HS XOSC, 001 – 111 for HS RCOSC) Figure 1: Current Consumption (Active Mode) vs. Clock Speed RX current consumption, typical variation over temperature and input power level 25 Current [mA] 23 21 19 Avg -40degC Avg 25decC Avg 85degC -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Pin [dBm] Figure 2: Typical Variation in RX Current Consumption over Temperature and Input Power Level, @ 433 MHz and 250 kBaud data rate. Supply Voltage, VDD = 2 V Temperature [°C] Current [mA] -40 37 +25 36 +85 35.4 Supply Voltage, VDD = 3 V -40 37.2 +25 36.2 +85 35.6 Supply Voltage, VDD = 3.6 V -40 37.5 +25 36.4 +85 35.8 Table 7: Typical Variation in TX Current Consumption over Temperature and Supply Voltage, @ 868 MHz and +10 dBm output power. SWRS033E Page 13 of 239 CC1110Fx / CC1111Fx 7.2 RF Receive Section TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference design ([1]) if nothing else is stated. Parameter Digital channel filter bandwidth Min 58 Typ Max 812 Unit kHz Condition/Note User programmable (see section 14.6). The bandwidth limits are proportional to crystal frequency (given values assume a 26MHz system clock). 315 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity -110 -112 dBm dBm System clock running at 26 MHz System clock running at 24MHz The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -107 dBm. 315 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity -102 -103 dBm dBm System clock running at 26 MHz System clock running at 24MHz The RX current consumption can be reduced by approximately 2.1 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -99 dBm. 315 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity -94 -94 dBm dBm System clock running at 26 MHz System clock running at 24MHz 433 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) -110 Receiver sensitivity -110 dBm dBm System clock running at 26 MHz System clock running at 24MHz The RX current consumption can be reduced by approximately 2.6 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -107 dBm. 433 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) -102 Receiver sensitivity -101 dBm dBm System clock running at 26 MHz System clock running at 24MHz The RX current consumption can be reduced by approximately 2.7 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -99 dBm. Min Typ Max Unit Condition/Note Parameter 433 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) -95 Receiver sensitivity -93 System clock running at 26 MHz System clock running at 24MHz See Table 9 for typical variation over operating conditions SWRS033E Page 14 of 239 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition/Note 868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity -110 -110 dBm dBm System clock running at 26 MHz Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -107 dBm. Saturation Adjacent channel rejection Alternate channel rejection -14 38 dBm dB MCSM0.CLOSE_IN_RX=00 Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 100 kHz channel spacing See Figure 57 for plot of selectivity versus frequency offset 35 dB Image channel rejection, 868MHz 33 dB IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit. 868 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) -102 -101 dBm dBm Receiver sensitivity System clock running at 26 MHz Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock The RX current consumption can be reduced by approximately 2.2 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -100 dBm. Saturation Adjacent channel rejection Alternate channel rejection -14 19 dBm dB MCSM0.CLOSE_IN_RX=00 Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing See Figure 58 for plot of selectivity versus frequency offset 32 dB Image channel rejection, 868MHz 28 dB IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit. SWRS033E Page 15 of 239 CC1110Fx / CC1111Fx Parameter Min Typ Max Unit Condition/Note 868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) Receiver sensitivity -94 -91 Saturation Adjacent channel rejection Alternate channel rejection Image channel rejection, 868MHz -16 27 dBm dBm dBm dB System clock running at 26 MHz Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock MCSM0.CLOSE_IN_RX=00 Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing See Figure 59 for plot of selectivity versus frequency offset 17 dB IF frequency 304 kHz Desired channel 3 dB above the sensitivity limit. 36 dB 915 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth) Receiver sensitivity -108 -110 dBm dBm System clock running at 26 MHz Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -107 dBm. 915 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 100 kHz digital channel filter bandwidth) Receiver sensitivity -100 -100 dBm dBm System clock running at 26 MHz Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock The RX current consumption can be reduced by approximately 2.1 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then -99 dBm. 915 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –93 -91 dBm dBm System clock running at 26 MHz Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock 915 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –86 dBm System clock running at 26 MHz. Not tested on [4] CC1111 USB-Dongle Reference Design, 24MHz clock SWRS033E Page 16 of 239 CC1110Fx / CC1111Fx Parameter Blocking Blocking at ±2 MHz offset, 1.2 kBaud, 868 MHz Blocking at ±2 MHz offset, 250 kBaud, 868 MHz Blocking at ±10 MHz offset, 1.2 kBaud, 868 MHz Blocking at ±10 MHz offset, 250 kBaud, 868 MHz Parameter General Spurious emissions Conducted measurement in a 50 Ω single ended load. Complies with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66. Numbers are from CC1101 (same radio on CC1110 and CC1111) Typical radiated spurious emission is -49 dB measured at the VCO frequency. -68 -66 -57 -47 dBm dBm Maximum figure is the ETSI EN 300 220 limit Maximum figure is the ETSI EN 300 220 limit Min -45 dBm Desired channel 3dB above the sensitivity limit. Min Typ Max Unit Condition/Note -50 dBm Desired channel 3dB above the sensitivity limit -33 dBm Desired channel 3dB above the sensitivity limit. -40 dBm Desired channel 3dB above the sensitivity limit. Typ Max Unit Condition/Note 25 MHz – 1 GHz Above 1 GHz Table 8: RF Receive Section Supply Voltage, VDD = 2 V Temperature [°C] Sensitivity [dBm] -40 -96.4 25 -94.9 85 -92.6 Supply Voltage, VDD = 3 V -40 -96.1 25 -95.0 85 -92.2 Supply Voltage, VDD = 3.6 V -40 -96.1 25 -94.5 85 -92.2 Table 9: Typical Variation in Sensitivity over Temperature and Supply Voltage @ 433 MHz and 250 kBaud Data Rate SWRS033E Page 17 of 239 CC1110Fx / CC1111Fx 7.3 RF Transmit Section TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference designs ([1]) if nothing else is stated. Parameter Differential load impedance 315 MHz 433 MHz 868/915 MHz Output power, highest setting 122 + j31 116 + j41 86.5 + j43 +10 dBm Output power is programmable, and full range is available in all frequency bands Output power may be restricted by regulatory limits. See Application Note AN050 [13] – note that this AN is for CC1101 but the same limitations apply for CC1110Fx and CC1111Fx as well. For CC1111Fx see in addition Design Note DN016 [14] for information on antenna solution and additional regulatory restrictions See figure Figure 3 for typical variation over operating conditions Delivered to 50 Ω single-ended load via CC1110EM reference design [3] RF matching network. Output power, lowest setting -30 dBm Output power is programmable and is available across the entire frequency band Delivered to 50 Ω single-ended load via CC1110EM reference design [3] RF matching network. Harmonics, radiated 2 Harm, 433 MHz rd 3 Harm, 433 MHz 2 Harm, 868 MHz rd 3 Harm, 868 MHz Harmonics, radiated 2 Harm, 868 MHz rd 3 Harm, 868 MHz Harmonics, conducted 315 MHz 433 MHz 868 MHz 915 MHz < -35 < -52 < -44 < -35 < -35 < -34 dBm nd nd nd Min Typ Max Unit Condition/Note Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1110EM reference designs ([1], [2] and [3]) available from the TI website. Ω -51 -42 -37 -43 dBm Measured on CC1110EM reference designs ([2] and [3]) with CW, 10dBm output power The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in attenuating the harmonics dBm -55 -55 Measured on [4] CC1111 USB-Dongle Reference Design, with CW, 10dBm output power. The chip antenna used during the radiated measurements play a part in attenuating the harmonics Measured on CC1110EM reference designs ([1], [2] and [3]) with CW, 10dBm output power, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz, or 915.00 MHz Frequencies below 960 MHz Frequencies above 960 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies above 1 GHz Frequencies above 1 GHz SWRS033E Page 18 of 239 CC1110Fx / CC1111Fx Parameter Spurious emissions radiated, Harmonics not included Min Typ Max Unit Condition/Note Measured on CC1110EM reference designs ([1], [2] and [3]) with 10 dBm CW, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 or 915.00 MH. For CC1111Fx see DN016 [14] Please refer to register TEST1 on page 222 for required settings in RX and TX < -58 < -53 < -50 < -54 < -56 < -56 < -54 < -56 < -51 < -60 dBm dBm Frequencies below 960 MHz Frequencies above 960 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz. Frequencies below 960 MHz Frequencies above 960 MHz 315 MHz 433 MHz 868 MHz dBm dBm 915 MHz Table 10: RF Transmit Section Output power (10dBm), variation over frequency and temperature 12 Output power [dBm] 11 10 9 8 7 6 750 800 850 Frequency [MHz] 900 950 Avg -40degC Avg 25degC Avg 85degC Figure 3: Typical Variation in Output Power over Frequency and Temperature (+10 dBm output power) SWRS033E Page 19 of 239 CC1110Fx / CC1111Fx 7.4 7.4.1 Crystal Oscillators CC1110Fx Crystal Oscillator (26 – 27 MHz) TA = 25 °C, VDD = 3.0 V if nothing else is stated. Parameter Crystal frequency Crystal frequency accuracy requirement Min 26 Typ 26 ±40 Max 27 Unit MHz ppm Condition/Note Referred to as fXOSC. This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. 1 10 5 13 7 20 100 250 pF pF Ω µs Simulated over operating conditions Simulated over operating conditions Simulated over operating conditions fXOSC = 26 MHz Note: A Ripple counter of 12 bit is included to ensure duty-cycle requirements. Start-up time includes ripple counter delay until SLEEP.XOSC_STB is asserted Power Down Guard Time 3 ms The crystal oscillator must be in power down for a guard time before it is used again. This requirement is valid for all modes of operation. The need for power down guard time can vary with crystal type and load. Minimum figure is valid for reference crystal NDK, AT-41CD2 and load capacitance according to Table 29. If power down guard time is violated increased CRC error can be present in the first few radio packets after power down. C0 Load capacitance ESR Start-up time Table 11: CC1110Fx Crystal Oscillator Parameters 7.4.2 CC1111Fx Crystal Oscillator (48 MHz) TA = 25 °C, VDD = 3.0 V if nothing else is stated. Parameter Crystal frequency Min Typ 48 Max Unit MHz Condition/Note Referred to as fXOSC. 48MHz crystal gives a system clock of 24MHz. Please note that there are restricted usage in the frequency bands 863-870 MHz (due to spurious emission). See DN016 Compact antenna solutions for 868/915MHz [14] Crystal frequency accuracy requirement ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. Simulated over operating conditions. Variation given by reference crystal NX2520SA from NDK (fundamental). Simulated over operating conditions Simulated over operating conditions Note: A Ripple counter of 14 bit is included to ensure duty-cycle requirements. Start-up time includes ripple counter delay until SLEEP.XOSC_STB is asserted C0 Fundamental Load capacitance ESR Start-up time Fundamental crystal 650 µs 0.85 15 1 16 1.15 17 60 pF pF Ω Table 12: CC1111Fx Crystal Oscillator Parameters SWRS033E Page 20 of 239 CC1110Fx / CC1111Fx 7.5 32.768 kHz Crystal Oscillator TA = 25 °C, VDD = 3.0V if nothing else is stated. Parameter Crystal frequency Crystal shunt capacitance Load capacitance ESR Start-up time Min Typ 32.768 0.9 12 40 400 2.0 16 130 Max Unit kHz pF pF kΩ ms Simulated over operating conditions Simulated over operating conditions Simulated over operating conditions Value is simulated Condition/Note Table 13: 32.768 kHz Crystal Oscillator Parameters 7.6 Low Power RC Oscillator TA = 25 °C, VDD = 3.0 V if nothing else is stated. Parameter Calibrated frequency 2 Min 32.0 Typ 34.7 Max 36.0 ±1 Unit kHz % %/°C %/V ms Condition/Note Calibrated low power RC oscillator frequency is fXOSC / 750 Frequency accuracy after calibration Temperature coefficient Supply voltage coefficient Initial calibration time +0.5 +3 2 Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration When the low power RC oscillator is enabled, calibration is continuously done in the background as long as the high speed crystal oscillator is running. Table 14: Low Power RC Oscillator Parameters Min figures are given using fXOSC = 24 MHz. Typical figures are given using fXOSC = 26 MHz, and Max figures are given using fXOSC = 27 MHz 2 SWRS033E Page 21 of 239 CC1110Fx / CC1111Fx 7.7 High Speed RC Oscillator TA = 25 °C, VDD = 3.0 V if nothing else is stated. Parameter Calibrated frequency 2 Min 12 Typ 13 ±15 Max 13.5 Unit MHz % Condition/Note Calibrated HS RCOSC frequency is fXOSC / 2 Uncalibrated frequency accuracy Calibrated frequency accuracy Start-up time Temperature coefficient Supply voltage coefficient Initial calibration time ±1 10 -325 28 65 % µs ppm/°C ppm/V µs Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration The HS RCOSC will be calibrated once when the high speed crystal oscillator is selected as system clock source (CLKCON.OSC is set to 0), and also when the system wakes up from PM{1-3}. See 13.1.5.1 for details). Table 15: High Speed RC Oscillator Parameters 7.8 Frequency Synthesizer Characteristics TA = 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1110EM reference designs ([1]). Parameter Programmed frequency resolution Synthesizer frequency tolerance RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise RF carrier phase noise PLL turn-on / hop time 3 Min 367 Typ 397 Max 412 Unit Hz Condition/Note 24 - 27 MHz system clock. Frequency resolution = fXOSC / 2 16 ±40 ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. @ 50 kHz offset from carrier @ 100 kHz offset from carrier @ 200 kHz offset from carrier @ 500 kHz offset from carrier @ 1 MHz offset from carrier @ 2 MHz offset from carrier @ 5 MHz offset from carrier @ 10 MHz offset from carrier Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration. Crystal oscillator running. Settling time for the 1·IF frequency step from RX to TX Settling time for the 1·IF frequency step from TX to RX Calibration can be initiated manually or automatically before entering or after leaving RX/TX. -92 -93 -93 -98 -107 -113 -119 -129 85.1 88.4 95.8 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz µs PLL RX/TX settling time PLL TX/RX settling time PLL calibration time 3 3 3 9.3 20.7 694 9.6 21.5 721 10.4 23.3 780.8 µs µs µs Table 16: Frequency Synthesizer Parameters 3 Min figures are given using fXOSC = 27 MHz. Typ figures are given using fXOSC = 26 MHz, and Max figures are given using fXOSC = 24 MHz. SWRS033E Page 22 of 239 CC1110Fx / CC1111Fx 7.9 Analog Temperature Sensor TA= 25 °C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1110EM reference designs ([1]). Parameter Output voltage at -40 °C Output voltage at 0 °C Output voltage at +40 °C Output voltage at +80 °C Temperature coefficient Error in calculated temperature, calibrated -2 * Min Typ 0.660 0.755 0.859 0.958 2.54 0 Max Unit V V V V mV/°C Condition/Note Fitted from -20 °C to +80 °C From –20°C to +80°C when using 2.43 mV / °C, after 1-point calibration at room temperature * 2 * °C The indicated minimum and maximum error with 1-point calibration is based on measured values for typical process parameters Current consumption increase when enabled 0.3 mA Table 17: Analog Temperature Sensor Parameters 7.10 7-12 bit ADC TA = 25 °C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed in accordance with IEEE Std 1241-2000 [8]. The ADC data are from CC2430 characterization. As the CC1110Fx/C1111Fx uses the same ADC, the numbers listed in Table 18 should be good indicators of the performance to be expected from CC1110Fx and CC1111Fx. Note that these numbers will apply for 24 MHz operated systems (like CC1110Fx using a 24 MHz crystal or CC1111Fx using a 48 MHz crystal). Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz). Parameter Input voltage External reference voltage External reference voltage differential Input resistance, signal Full-Scale Signal ENOB 4 4 Min 0 0 0 Typ Max VDD VDD VDD Unit V V V kΩ V bits Condition/Note VDD is voltage on AVDD pin (2.0 – 3.6 V) VDD is voltage on AVDD pin (2.0 – 3.6 V) VDD is voltage on AVDD pin (2.0 – 3.6 V) Simulated using 4 MHz clock speed (see section 13.10.2.7) Peak-to-peak, defines 0 dBFS 7-bits setting 9-bits setting 10-bits setting 12-bits setting 197 2.97 5.7 7.5 9.3 10.8 Single ended input ENOB 4 6.5 8.3 10.0 11.5 bits 7-bits setting 9-bits setting 10-bits setting 12-bits setting Differential input Useful Power Bandwidth THD 4 0-20 kHz 7-bits setting, both single and differential -Single ended input -Differential input 4 -75.2 -86.6 dB dB 12-bits setting, -6 dBFS 12-bits setting, -6 dBFS Measured with 300 Hz Sine input and VDD as reference. SWRS033E Page 23 of 239 CC1110Fx / CC1111Fx Parameter Signal To Non-Harmonic Ratio -Single ended input -Differential input Spurious Free Dynamic Range -Single ended input -Differential input CMRR, differential input Crosstalk, single ended input Offset Gain error DNL 4 4 4 Min Typ Max Unit Condition/Note 70.2 79.3 dB dB 12-bits setting 12-bits setting 78.8 88.9 n Byte/Word 2 Byte/Word 1 Length = n LEN = n Byte/Word n+3 Byte/Word n+2 Byte/Word n+1 Byte/Word n Byte/Word n-1 Byte/Word n-2 . . . . Byte/Word 3 LEN > n Byte/Word 2 Byte/Word 1 Length = n LEN = n Byte/Word n+3 Byte/Word n+2 Byte/Word n+1 Byte/Word n Byte/Word n-1 Byte/Word n-2 . . . . Byte/Word 3 Byte/Word 2 Byte/Word 1 Length = n LEN > n LEN = n Byte/Word n+3 Byte/Word n+2 Byte/Word n+1 Byte/Word n Byte/Word n-1 Byte/Word n-2 . . . . Byte/Word 3 Byte/Word 2 Byte/Word 1 Length = n LEN = n VLEN = 001 If LEN ≤ n, LEN bytes/words are being transferred. The dotted line shows the case where LEN = n VLEN = 010 VLEN = 011 VLEN = 100 Figure 26: Variable Length (VLEN) Transfer Options 13.5.2.4 Byte or Word Transfers (WORDSIZE) Determines whether each DMA transfer should be 8-bit (byte) or 16-bit (word). 13.5.2.5 DMA Transfer Mode (TMODE) The transfer mode determines how the DMA channel behaves when transferring data. There are four different transfer modes. Single. On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After completing the number of transfers specified by the transfer count, the CPU is notified (DMAIRQ.DMAIFn=1) and the DMA channel is disarmed. Block. On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified (DMAIRQ.DMAIFn=1) and the DMA channel is disarmed. Repeated single. On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After completing the number of transfers specified by the transfer count, the CPU is notified (DMAIRQ.DMAIFn=1) and the DMA channel is rearmed. Repeated block. On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified (DMAIRQ.DMAIFn=1) and the DMA channel is rearmed. 13.5.2.6 Trigger Event (TRIG) All DMA transfers are initiated by so-called DMA trigger events, which either starts a DMA block transfer or a single DMA transfer (or repeated versions of these). Each DMA channel can be set up to sense on a single trigger. The TRIG field in the configuration determines which trigger the DMA channel is to use. In addition to the configured trigger, a DMA channel can always be triggered by setting its designated DMAREQ.DMAREQn flag. The DMA trigger sources are described in Table 51 on page 108. 13.5.2.7 Source and Destination Increment (SRCINC and DESTINC) When the DMA channel is armed or rearmed, the source and destination addresses are transferred to internal address pointers. These pointers, and hence the source and destination addresses, can be controlled to increment, decrement, or not change between transfers in order to give good flexibility. The possibilities for address increment/decrement are: • Increment by zero. The address pointer shall remain fixed after each transfer. SWRS033E Page 105 of 239 CC1110Fx / CC1111Fx • Increment by one. The address pointer shall increment one count after each transfer. • Increment by two. The address pointer shall increment two counts after each transfer. • Decrement by one. The address pointer shall decrement one count after each transfer. 13.5.2.8 Interrupt Mask (IRQMASK) data structure in memory. Each DMA channel in use requires its own DMA configuration data structure. The DMA configuration data structure consists of eight bytes and is described in Table 52. A DMA configuration data structure may reside at any location in unified memory space decided upon by the user software, and the address location is passed to the DMA controller through a set of SFRs DMAxCFGH:DMAxCFGL (x is 0 or 1). Once a channel has been armed, the DMA controller will read the configuration data structure for that channel, given by the address in DMAxCFGH:DMAxCFGL. It is important to note that the method for specifying the start address for the DMA configuration data structure differs between DMA channel 0 and DMA channels 1-4 as follows: DMA0CFGH:DMA0CFGL gives the start address for DMA channel 0 configuration data structure. DMA1CFGH:DMA1CFGL gives the start address for DMA channel 1 configuration data structure followed by channel 2 - 4 configuration data structures. This means that the DMA controller expects the DMA configuration data structures for DMA channels 1 - 4 to lie in a contiguous area in memory, starting at the address held in DMA1CFGH:DMA1CFGL and consisting of 32 bytes. 13.5.4 Stopping DMA Transfers Ongoing DMA transfer or armed DMA channels will be aborted using the DMAARM register to disarm the DMA channel. One or more DMA channels are aborted by writing a 1 to DMAARM.ABORT register bit, and at the same time select which DMA channels to abort by setting the corresponding, DMAARM.DMAARMn bits to 1. When setting DMAARM.ABORT to 1, the DMAARM.DMAARMn bits for non-aborted channels must be written as 0. An example of DMA channel arm and disarm is shown in Figure 27. The DMA transfer will upon completion set IRCON.DMAIF=1 if this bit is set to 1. An interrupt request is being generated if IEN1.DMAIE=1. 13.5.2.9 Mode 8 Setting (M8) In variable length transfers (VLEN≠000 and VLEN≠111) this field determines whether to use seven or eight bits of the first byte in source data as the transfer length. This configuration is only applicable when doing byte transfers. 13.5.2.10 DMA Priority (PRIORITY) A DMA priority is associated with each DMA channel. The DMA priority is used to determine the winner in the case of multiple simultaneous internal memory requests, and whether the DMA memory access should have priority or not over a simultaneous CPU memory access. In case of an internal tie, a round-robin scheme is used to ensure access for all. There are three levels of DMA priority: High: Highest internal priority. DMA access will always prevail over CPU access. Normal: Second highest internal priority. Guarantees that DMA access prevails over CPU on at least every second try. Low: Lowest internal priority. DMA access will always defer to a CPU access. 13.5.3 DMA Configuration Setup The DMA channel parameters such as address mode, transfer mode and priority described in the previous section have to be configured before a DMA channel can be armed and activated. The parameters are not configured directly through SFRs, but instead they are written in a special DMA configuration MOV DMAARM, #0x03 MOV DMAARM, #0x81 ; Arm DMA channel 0 and 1 ; Disarm DMA channel 0, channel 1 is still armed Figure 27: DMA Arm/Disarm Example SWRS033E Page 106 of 239 CC1110Fx / CC1111Fx 13.5.5 DMA Interrupts Each DMA channel can be configured to generate an interrupt to the CPU upon completion of a DMA transfer. This is accomplished by setting the IRQMASK bit in the channel configuration to 1. When this bit is set to 1, IRCON.DMAIF=1 will be set to 1 when a transfer is completed. An interrupt request is being generated if IEN1.DMAIE=1.The corresponding interrupt flag in the SFR will be set when the interrupt is generated. Regardless of the IRQMASK bit in the channel configuration, DMAIRQ.DMAIFn will be set upon DMA channel complete. Thus software should always check (and clear) this register when rearming a channel with a changed IRQMASK setting. Failure to do so could DMA Trigger Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 T2_OVFL T3_CH0 T3_CH1 T4_CH0 T4_CH1 ST IOC_0 IOC_1 URX0 UTX0 URX1 UTX1 FLASH RADIO ADC_CHALL ADC_CH0 Timer 2 Timer 3 Timer 3 Timer 4 Timer 4 Sleep Timer IO Controller IO Controller USART0 USART0 USART1 USART1 Flash Controller Radio ADC ADC DMA Trigger Name NONE PREV T1_CH0 T1_CH1 T1_CH2 Functional Unit DMA DMA Timer 1 Timer 1 Timer 1 Description No trigger, setting DMAREQ.DMAREQx bit starts transfer DMA channel is triggered by completion of previous channel Timer 1, capture/compare, channel 0 Timer 1, capture/compare, channel 1 Timer 1, capture/compare, channel 2 Not in use. Timer 2, timer count reaches 0x00 Timer 3, compare, channel 0 Timer 3, compare, channel 1 Timer 4, compare, channel 0 Timer 4, compare, channel 1 Sleep Timer compare P0_1 input transition P1_3 input transition 15 16 generate an interrupt based on the stored interrupt flag. 13.5.6 DMA Memory Access The DMA data transfer is affected by endian convention. This as the memory system use Big-Endian in XDATA memory, while LittleEndian is used in SFR memory. This must be accounted for in compilers. 13.5.7 DMA USB Endianess (CC1111Fx) When a USB FIFO is accessed using word transfer, the endianess of the word read/written can be controlled by setting the ENDIAN.USBWLE and ENDIAN.USBRLE configuration bits in the ENDIAN register. See section 13.16 for details. USART0 RX complete USART0 TX complete USART1 RX complete USART1 TX complete Flash data write complete RF packet byte received/transmit ADC end of a conversion in a sequence, sample ready ADC end of conversion (AIN0, single-ended or AIN0 – AIN1, differential). Sample ready 15 16 Trigger on rising edge. P0SEL.SELP0_1 and P0DIR.P0_1 must be 0 Trigger on falling edge. P1SEL.SELP1_3 and P1DIR.P1_3 must be 0 SWRS033E Page 107 of 239 CC1110Fx / CC1111Fx DMA Trigger Number 22 23 24 25 26 DMA Trigger Name ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 27 I2SRX ADC_CH7 28 I2STX 29 30 ENC_DW ENC_UP IS AES AES 2 Functional Unit ADC ADC ADC ADC ADC ADC IS ADC 2 Description ADC end of conversion (AIN1, single-ended or AIN0 – AIN1, differential). Sample ready ADC end of conversion (AIN2, single-ended or AIN2 – AIN3, differential). Sample ready ADC end of conversion (AIN3, single-ended or AIN2 – AIN3, differential). Sample ready ADC end of conversion (AIN4, single-ended or AIN4 – AIN5, differential). Sample ready ADC end of conversion (AIN5, single-ended or AIN4 – AIN5, differential). Sample ready ADC end of conversion (AIN6, single-ended or AIN6 – AIN7, differential). Sample ready I S RX complete ADC end of conversion (AIN7, single-ended or AIN6 – AIN7, differential). Sample ready I S TX complete AES encryption processor requests download input data AES encryption processor requests upload output data 2 2 Table 51: DMA Trigger Sources Byte Offset 0 1 2 Bit 7:0 7:0 7:0 Field Name SRCADDR[15:8] SRCADDR[7:0] DESTADDR[15:8] Description The DMA channel source address, high byte The DMA channel source address, low byte The DMA channel destination address, high byte. Note that flash memory is not directly writeable. 3 7:0 DESTADDR[7:0] The DMA channel destination address, low byte. Note that flash memory is not directly writeable. SWRS033E Page 108 of 239 CC1110Fx / CC1111Fx Byte Offset 4 Bit 7:5 Field Name VLEN[2:0] Description Variable length transfer mode. In word mode, bits 12:0 of the first word is considered as the transfer length. 000 001 Use LEN for transfer count Transfer number of bytes/words commanded by first byte/word + 1 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word up to a maximum specified by LEN). Transfer number of bytes/words commanded by first byte/word (transfers length byte/word, and then as many bytes/words as dictated by length byte/word – 1 up to a maximum specified by LEN).) Transfer number of bytes/words commanded by first byte/word + 2 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 1 up to a maximum specified by LEN) Transfer number of bytes/words commanded by first byte/word + 3 (transfers length byte/word, and then as many bytes/words as dictated by length byte/word + 2 up to a maximum specified by LEN) Reserved Reserved Alternative for using LEN as transferr count 010 011 100 101 110 111 4 4:0 LEN[12:8] The DMA channel transfer count. This value is used as transfer count when VLEN=000 or VLEN=111 (fixed length transfers) and as maximum allowable length when VLEN≠000 and VLEN≠111 (variable length transfers). The DMA channel counts in words when in WORDSIZE mode, and otherwise in bytes. 5 7:0 LEN[7:0] The DMA channel transfer count. This value is used as transfer count when VLEN=000 or VLEN=111 (fixed length transfers) and as maximum allowable length when VLEN≠000 and VLEN≠111 (variable length transfers). The DMA channel counts in words when in WORDSIZE mode, and otherwise in bytes. 6 6 7 6:5 WORDSIZE TMODE[1:0] Selects whether each DMA transfer shall be 8-bit (0) or 16-bit (1). The DMA channel transfer mode: 00 01 10 11 Single Block Repeated single Repeated block 6 4:0 TRIG[4:0] Select DMA trigger 00000 00001 00010 11111 No trigger (writing to DMAREQ is only trigger) The previous DMA channel finished Selects one of the triggers shown in Table 51. The trigger is selected in the order shown in the table. 7 7:6 SRCINC[1:0] Source address increment mode (after each transfer) 00 01 10 11 0 bytes/words 1 bytes/words 2 bytes/words -1 bytes/words SWRS033E Page 109 of 239 CC1110Fx / CC1111Fx Byte Offset 7 Bit 5:4 Field Name DESTINC[1:0] Description Destination address increment mode (after each transfer) 00 01 10 11 7 3 IRQMASK 0 bytes/words 1 bytes/words 2 bytes/words -1 bytes/words Interrupt Mask for this channel. 0 1 Disable interrupt generation Enable interrupt generation upon DMA channel done th 7 2 M8 Mode of 8 bit in transfer count for variable length transfers (VLEN≠000 and VLEN≠111). Only applicable when WORDSIZE=0. 0 1 Use all 8 bits for transfer count Use 7 LSB for transfer count 7 1:0 PRIORITY[1:0] The DMA channel priority: 00 01 10 11 Low, DMA access will always defer to a CPU access Normal, guarantees that DMA access prevails over CPU on at least every second try. High, DMA access will always prevail over CPU access. Reserved Table 52: DMA Configuration Data Structure SWRS033E Page 110 of 239 CC1110Fx / CC1111Fx 13.5.8 DMA Registers This section describes the SFRs associated with the DMA Controller. DMAARM (0xD6) – DMA Channel Arm Bit 7 Name ABORT Reset 0 R/W R0/W Description DMA abort. Ongoing DMA transfer or armed DMA channels will be aborted when writing a 1 to this bit, and at the same time select which DMA channels to abort by setting the corresponding, DMAARM.DMAARMn bits to 1 0 1 6:5 4 DMAARM4 0 0 R0 R/W Normal operation Abort channels all selected channels Not used DMA arm channel 4 This bit must be set to 1 in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared when the transfer count is reached 3 DMAARM3 0 R/W DMA arm channel 3 This bit must be set to 1 in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared when the transfer count is reached 2 DMAARM2 0 R/W DMA arm channel 2 This bit must be set to 1 in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared when the transfer count is reached 1 DMAARM1 0 R/W DMA arm channel 1 This bit must be set to 1 in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared when the transfer count is reached 0 DMAARM0 0 R/W DMA arm channel 0 This bit must be set to 1 in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared when the transfer count is reached SWRS033E Page 111 of 239 CC1110Fx / CC1111Fx DMAREQ (0xD7) – DMA Channel Start Request and Status Bit 7:5 4 DMAREQ4 Name Reset 000 0 R/W R0 R/W1 H0 Description Not used DMA transfer request, channel 4 (manual trigger) Setting this bit to 1 will have the same effect as a single trigger event. This bit is cleared when the DMA channel is granted access. 3 DMAREQ3 0 R/W1 H0 DMA transfer request, channel 3 (manual trigger) Setting this bit to 1 will have the same effect as a single trigger event. This bit is cleared when the DMA channel is granted access. 2 DMAREQ2 0 R/W1 H0 DMA transfer request, channel 2 (manual trigger) Setting this bit to 1 will have the same effect as a single trigger event. This bit is cleared when the DMA channel is granted access. 1 DMAREQ1 0 R/W1 H0 DMA transfer request, channel 1 (manual trigger) Setting this bit to 1 will have the same effect as a single trigger event. This bit is cleared when the DMA channel is granted access. 0 DMAREQ0 0 R/W1 H0 DMA transfer request, channel 0 (manual trigger) Setting this bit to 1 will have the same effect as a single trigger event. This bit is cleared when the DMA channel is granted access. DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte Bit 7:0 Name DMA0CFG[15:8] Reset 0x00 R/W R/W Description The DMA channel 0 configuration address, high byte DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte Bit 7:0 Name DMA0CFG[7:0] Reset 0x00 R/W R/W Description The DMA channel 0 configuration address, low byte DMA1CFGH (0xD3) – DMA Channel 1-4 Configuration Address High Byte Bit 7:0 Name DMA1CFG[15:8] Reset 0x00 R/W R/W Description The DMA channel 1 - 4 configuration address, high byte DMA1CFGL (0xD2) – DMA Channel 1-4 Configuration Address Low Byte Bit 7:0 Name DMA1CFG[7:0] Reset 0x00 R/W R/W Description The DMA channel 1 - 4 configuration address, low byte SWRS033E Page 112 of 239 CC1110Fx / CC1111Fx DMAIRQ (0xD1) – DMA Interrupt Flag Bit 7:5 4 DMAIF4 Name Reset 0 0 R/W R0 R/W0 Description Not used DMA channel 4 interrupt flag. 0 1 3 DMAIF3 0 R/W0 DMA channel transfer not complete DMA channel transfer complete/interrupt pending DMA channel 3 interrupt flag. 0 1 DMA channel transfer not complete DMA channel transfer complete/interrupt pending 2 DMAIF2 0 R/W0 DMA channel 2 interrupt flag. 0 1 DMA channel transfer not complete DMA channel transfer complete/interrupt pending 1 DMAIF1 0 R/W0 DMA channel 1 interrupt flag. 0 1 DMA channel transfer not complete DMA channel transfer complete/interrupt pending 0 DMAIF0 0 R/W0 DMA channel 0 interrupt flag. 0 1 DMA channel transfer not complete DMA channel transfer complete/interrupt pending ENDIAN (0x95) – USB Endianess Control (CC1111Fx) Bit 7:2 1 USBWLE Name Reset 0 0 R/W R/W R/W Description Not used USB Write Endianess setting for DMA channel word transfers to USB. 0 1 0 USBRLE 0 R/W Big Endian Little Endian USB Read Endianess setting for DMA channel word transfers from USB. 0 1 Big Endian Little Endian SWRS033E Page 113 of 239 CC1110Fx / CC1111Fx 13.6 16-bit Timer, Timer 1 Timer 1 is an independent 16-bit timer which supports typical timer/counter functions such as input capture, output compare, and PWM functions. The timer has three independent capture/compare channels and uses one I/O pin per channel. The features of Timer 1 are as follows: • • • • • • • • • Three capture/compare channels Rising, falling, or any edge input capture Set, clear, or toggle output compare Free-running, modulo or up/down counter operation Clock prescaler for divide by 1, 8, 32, or 128 Interrupt request generation on capture/compare and when reaching the terminal count value Capture triggered by radio DMA trigger function Delta-Sigma Modulator (DSM) mode clock frequency used by Timer 1 is fXOSC/2 for CC1110Fx and 12 MHz for CC1111Fx, given that the HS RCOSC has been calibrated. The counter operates as either a free-running counter, a modulo counter, or as an up/down counter for use in centre-aligned PWM. It can also be used in DSM mode. It is possible to read the 16-bit counter value through the two 8-bit SFRs; T1CNTH and T1CNTL, containing the high-order byte and low-order byte respectively. When the T1CNTL register is read, the high-order byte of the counter at that instant is buffered in T1CNTH so that the high-order byte can be read from T1CNTH . Thus T1CNTL shall always be read first before reading T1CNTH. All write accesses to the T1CNTL register will reset the 16-bit counter. The counter may produce an interrupt request when the terminal count value (overflow) is reached (see section 13.6.2.1 - 13.6.2.3). It is possible to start and halt the counter with T1CTL control register settings. The counter is started when a value other than 00 is written to T1CTL.MODE. If 00 is written to T1CTL.MODE the counter halts at its present value. 13.6.2 Timer 1 Operation In general, the control register T1CTL is used to control the timer operation. The various modes of operation are described in the following three sections. 13.6.2.1 Free-running Mode In free-running mode the counter starts from 0x0000 and increments at each active clock edge. When the counter reaches the terminal count value 0xFFFF (overflow), the counter is loaded with 0x0000 and continues incrementing its value as shown in Figure 28. When 0xFFFF is reached, the T1CTL.OVFIF flag is set. The IRCON.T1IF flag is only asserted if the corresponding interrupt mask bit TIMIF.OVFIM is set. An interrupt request is generated when both TIMIF.OVFIM and IEN1.T1EN are set to 1. The free-running mode can be used to generate independent time intervals and output signal frequencies. Note: In the following sections, an n in the register name represent the channel number 0, 1, or 2 if nothing else is stated 13.6.1 16-bit Timer Counter The timer consists of a 16-bit counter that increments or decrements at each active clock edge. The frequency of the active clock edges is given by CLKCON.TICKSPD and T1CTL.DIV. CLKCON.TICKSPD is used to set the timer tick speed. The timer tick speed will vary from 203.125 kHz to 26 MHz for CC1110Fx and 187.5 kHz to 24 MHz for CC1111Fx (given the use of a 26 MHz or 48 MHz crystal respectively). Note that the clock speed of the system clock is not affected by the TICKSPD setting. The timer tick speed is further divided in Timer 1 by the prescaler value set by T1CTL.DIV. This prescaler value can be 1, 8, 32, or 128. Thus the lowest clock frequency used by Timer 1 is 1.587 kHz and the highest is 26 MHz when a 26 MHz crystal oscillator is used as system clock source (CC1110Fx). The lowest clock frequency used by Timer 1 is 1.465 kHz and the highest is 24 MHz for CC1111Fx. When the high speed RC oscillator is used as system clock source, the highest SWRS033E Page 114 of 239 CC1110Fx / CC1111Fx 0xFFFF 0x0000 OVFIF = 1 OVFIF = 1 Figure 28: Free-running Mode 13.6.2.2 Modulo Mode In modulo mode the counter starts from 0x0000 and increments at each active clock edge. When the counter value matches the terminal count value T1CC0 (overflow), held in the registers T1CC0H:T1CC0L, the counter is loaded with 0x0000 and continues incrementing its value as shown in Figure 29. T1CC0 When T1CC0 is reached, the T1CTL.OVFIF flag is set. The IRCON.T1IF flag is only asserted if the corresponding interrupt mask bit TIMIF.OVFIM is set. An interrupt request is generated when both TIMIF.OVFIM and IEN1.T1EN are set to 1. The modulo mode can be used for applications where a period other than 0xFFFF is required. 0x0000 OVFIF = 1 OVFIF = 1 Figure 29: Modulo Mode 13.6.2.3 Up/Down Mode In up/down mode the counter starts from 0x0000 and increments at each active clock edge. When the counter value matches the terminal count value T1CC0, held in the registers T1CC0H:T1CC0L, the counter counts down until 0x0000 is reached and it starts counting up again as shown in Figure 30. When 0x0000 is reached, the T1CTL.OVFIF T1CC0 flag is set. The IRCON.T1IF flag is only asserted if the corresponding interrupt mask bit TIMIF.OVFIM is set. An interrupt request is generated when both TIMIF.OVFIM and IEN1.T1EN are set to 1. The up/down mode can be used when symmetrical output pulses are required with a period other than 0xFFFF, and therefore allows implementation of centrealigned PWM output applications. 0x0000 OVFIF = 1 OVFIF = 1 Figure 30: Up/Down Mode 13.6.3 Channel Mode Control The channel mode is set with each channel’s control and status register T1CCTLn. The settings include input capture and output compare modes. Note: Before an I/O pin can be used by the timer, the required I/O pin must be configured as a Timer 1 peripheral pin as described in section 13.4.6 on page 92 . 13.6.4 Input Capture Mode When a channel is configured as an input capture channel, the I/O pin associated with that channel, is configured as an input. After the timer has been started, a rising edge, falling edge or any edge on the input pin will trigger a capture of the 16-bit counter contents into the associated capture register. Thus the timer is able to capture the time when an external event takes place. Page 115 of 239 SWRS033E CC1110Fx / CC1111Fx The channel input pin is synchronized to the internal system clock. Thus pulses on the input pin must have a minimum duration greater than the system clock period. The contents of the 16-bit capture register can be read from registers T1CCnH:T1CCnL. When the capture takes place, the interrupt flag for the appropriate channel (T1CTL.CH0IF, T1CTL.CH1IF, or T1CTL.CH2IF for channel 0, 1, and 2 respectively) is asserted. The IRCON.T1IF flag is only asserted if the corresponding interrupt mask bit T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM is set to 1. An interrupt request is generated if the corresponding interrupt mask bit is set together with IEN1.T1EN. 13.6.4.1 RF Event Capture Each timer channel may be configured so that the RF events associated with the RF interrupt (interrupt #16) will trigger a capture instead of the normal input pin capture. This is done by setting T1CCTLn.CPSEL=1. When this configuration is choosen, the RF event(s) enabled by RFIM (see section 14.3.1 on page 187) will trigger a capture. This way the timer can be used to capture a value when e.g. a start of frame delimiter (SFD) is detected. Note: When using an RF event to trigger a capture, both CLKCON.CLKSPD and CLKCON.TICKSPD must be set to 000. 13.6.5 Output Compare Mode In output compare mode the I/O pin associated with a channel is set as an output. After the timer has been started, the contents of the counter are compared with the contents of the channel compare register T1CCnH:T1CCnL. If the compare register equals the counter contents, the output pin is set, reset, or toggled according to the compare output mode setting of T1CCTLn.CMP. Note that all edges on output pins are glitch-free when operating in a given output compare mode. Writing to the compare register T1CCnL is buffered so that a value written to T1CCnL does not take effect until the corresponding high order register, T1CCnH is written. For output compare modes 0 - 2, a new value written to the compare register T1CCnH:T1CCnL takes effect after the registers have been written. For other output compare modes the new value written to the compare register takes effect when the timer reaches 0x0000. Note that channel 0 has fewer output compare modes than channel 1 and 2 because T1CC0H:T1CC0L has a special function in modes 6 and 7, meaning these modes would not be useful for channel 0. When a compare occurs, the interrupt flag for the appropriate channel (T1CTL.CH0IF, T1CTL.CH1IF, or T1CTL.CH2IF for channel 0, 1, and 2 respectively) is asserted. The IRCON.T1IF flag is only asserted if the corresponding interrupt mask bit T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM is set to 1. An interrupt request is generated if the corresponding interrupt mask bit is set together with IEN1.T1EN. When operating in up-down mode, the interrupt flag for channel 0 is set when the counter reaches 0x0000 instead of when a compare occurs. Examples of output compare modes in various timer modes are given in Figure 31, Figure 32, and Figure 33. Edge-aligned: PWM output signals can be generated using the timer modulo mode and channels 1 and 2 in output compare mode 5 or 6 (defined by T1CCTLn.CMP bits, where n is 1 or 2) as shown in Figure 32. The period of the PWM signal is determined by the setting in T1CC0 and the duty cycle is determined by T1CCn. PWM output signals can also be generated using the timer free-running mode and channels 1 and 2 in output compare mode 5 or 6 as shown in Figure 31. In this case the period of the PWM signal is determined by CLKCON.TICKSPD and the prescaler divider value in T1CTL.DIV and the duty cycle is determined by T1CCn (n = 1 or 2). The polarity of the PWM signal is determined by whether output compare mode 5 or 6 is used. For both modulo mode and free-running mode it is also possible to use compare mode 3 or 4 to generate a PWM output signal (see Figure 31 and Figure 32). The polarity of the PWM signal is determined by whether output compare mode 3 or 4 is used. Centre-aligned: PWM outputs can be generated when the timer up/down mode is selected. The channel output compare mode 3 or 4 (defined by T1CCTLn.CMP bits, where n is 1 or 2) is selected depending on required polarity of the PWM signal (see Figure 33). The period of the PWM signal is determined by SWRS033E Page 116 of 239 CC1110Fx / CC1111Fx T1CC0 and the duty cycle for the channel output is determined by T1CCn (n = 1 or 2). 0xFFFF T1CC0 T1CCn 0x0000 0: Set output on compare 1: Clear output on compare 2: Toggle output on compare 3: Set output on compare-up, clear on 0 4: Clear output on compare-up, set on 0 5: Set when T1CCn, clear when T1CC0 6: Clear when T1CCn, set when T1CC0 T1CCn T1CC0 T1CCn T1CC0 Figure 31: Output Compare Modes, Timer Free-running Mode SWRS033E Page 117 of 239 CC1110Fx / CC1111Fx T1CC0 T1CCn 0x0000 0: Set output on compare 1: Clear output on compare 2: Toggle output on compare 3: Set output on compare-up, clear on 0 4: Clear output on compare-up, set on 0 5: Set when T1CCn, clear when T1CC0 6: Clear when T1CCn, set when T1CC0 T1CCn T1CC0 T1CCn T1CC0 Figure 32: Output Compare Modes, Timer Modulo Mode SWRS033E Page 118 of 239 CC1110Fx / CC1111Fx T1CC0 T1CCn 0x0000 0: Set output on compare 1: Clear output on compare 2: Toggle output on compare 3: Set output on compare-up, clear on compare down 4: Clear output on compare-up, set on compare-down 5: Set when T1CCn, clear when T1CC0 6: Clear when T1CCn, set when T1CC0 T1CCn T1CC0 T1CCn T1CCn T1CC0 T1CCn Figure 33: Output Modes, Timer Up/Down Mode 13.6.6 Timer 1 Interrupts There is one interrupt vector assigned to the timer. This is T1 (Interrupt #9, see Table 39). The following timer events may generate an interrupt request: • Counter reaches terminal count value (overflow) or turns around on zero • Input capture event • Output compare event The register bits T1CTL.OVFIF, T1CTL.CH0IF, T1CTL.CH1IF, and T1CTL.CH2IF contains the interrupt flags for the terminal count value event (overflow), and the three channel compare/capture events, respectively. These flags will be asserted regardless off the channel n interrupt mask bit (T1CCTLn.IM). The CPU interrupt flag, IRCON.T1IF will only be asserted if one or more of the channel n interrupt mask bits are set to 1. An interrupt request is only generated when the corresponding interrupt mask bit is set together with IEN1.T1EN. The interrupt mask bits are T1CCTL0.IM, T1CCTL1.IM, T1CCTL2.IM, and TIMIF.OVFIM. Note that enabling an interrupt mask bit will generate a SWRS033E Page 119 of 239 CC1110Fx / CC1111Fx new interrupt request if the corresponding interrupt flag is set. When the timer is used in Free-running Mode or Modulo Mode the interrupt flags are set as follows: • T1CTL.CH0IF, T1CTL.CH1IF, and T1CTL.CH2IF are set on compare/capture event • T1CTL.OVFIF is set when counter reaches terminal count value (overflow) When the timer is used in Up/Down Mode the interrupt flags are set as follows: In compare mode: • T1CTL.CH0IF and T1CTL.OVFIF are set when counter turns around on zero • T1CTL.CH1IF and T1CTL.CH2IF are set on compare event In capture mode: • T1CTL.OVFIF is set when counter turns around on zero • T1CTL.CH0IF, T1CTL.CH1IF, and T1CTL.CH2IF are set on capture event I addition, the CPU interrupt flag, IRCON.T1IF will be asserted if the channel n interrupt mask bit (T1CCTLn.IM) is set to 1. 13.6.7 Timer 1 DMA Triggers There are three DMA triggers associated with Timer 1, one for each channel. These are DMA triggers T1_CH0, T1_CH1 and T1_CH2, which are generated on timer capture/compare events as follows: • • • T1_CH0 - Channel 0 capture/compare T1_CH1 - Channel 1 capture/compare T1_CH2 - Channel 2 capture/compare interpolator is of first order with a scaling compensation. The scaling compensation is due to variable gain defined by the difference in sampling speed and DSM speed. This interpolation mechanism can be disabled by setting T1CCTL1.CAP=10 or T1CCTL1.CAP=11, thus using a zeroth order interpolator. In addition to the interpolator, a shaper can be used to account for differences in rise/fall times in the output signal. Also the shaper is enabled/disabled using the two CAP bits in the T1CCTL1 register. This shaper ensures a rising and a falling edge per bit and will thus limit the output swing to 1/8 to 7/8 of I/O VDD when the DSM operates at 1/8 of the timer tick speed or 1/4 to 3/4 of I/O VDD when the DSM operates at 1/4 of the timer tick speed. The DSM is used as in PWM mode where the terminal count value T1CC0 defines the period/sampling rate. The DSM can not use the Timer 1 prescaler to further slow down the period. Timer 1 must be configured to operate in modulo mode (T1CTL.MODE=10) and channel 0 must be configured to compare mode (T1CCTL0.MODE=1). The terminal count value T1CC0, held in the registers T1CC0H:T1CC0L, defines the sample rate. Table 53 shows some T1CC0 settings for different sample rates (CLKCON.TICKSPD=000). Sample Rate 8 kHz @ 24 MHz 8 kHz @ 26 MHz 16 kHz @ 24 MHz 16 kHz @ 26 MHz 48 kHz @ 24 MHz 48 kHz @ 26 MHz 64 kHz @ 24 MHz 64 kHz @ 26 MHz T1CC0H 0x0B 0x0C 0x05 0x06 0x01 0x02 0x01 0x01 T1CC0L 0xB7 0xB1 0xDB 0x59 0xF3 0x1D 0x76 0x96 13.6.8 DSM Mode Timer 1 also contains a 1-bit Delta-Sigma Modulator (DSM) of second order that can be used to produce a mono audio output PWM signal. The DSM removes the need for high order external filtering required when using regular PWM mode. The DSM operates at a fixed speed of either 1/4 or 1/8 of the timer tick speed set by CLKCON.TICKSPD. The DSM speed is set by T1CCTL1.MODE. The input samples are updated at a configurable sampling rate set by the terminal count value T1CC0. An interpolator is used to match the sampling rate with the DSM update rate. This Table 53: Channel 0 Period Setting for some Sampling Rates (CLKCON.TICKSPD=000) Since the DSM starts immediately after DSM mode has been enabled by setting T1CCTL1.CMP=111, all configuration should have been performed prior to enabling DSM mode. Also, the Timer 1 counter should be cleared and started just before starting the DSM operation (all write accesses to the T1CNTL register will reset the 16-bit counter while writing a value other than 00 to T1CTL.MODE will start the counter). A simple Page 120 of 239 SWRS033E CC1110Fx / CC1111Fx procedure for setting up DSM mode should then be as follows: 1. Suspend timer 1 (T1CTL.MODE=00) 2. Clear timer counter by writing any value to T1CNTL, (CNT=0x0000) 3. Set the sample rate by writing to T1CC0. 4. Set Timer 1 channel 0 compare mode (T1CCTL0.MODE=1) 5. Load first sample if available (or zero if no sample available) into T1CC1H:T1CC1L. 6. Set timer operation to modulo mode (T1CTL.MODE=10) 7. Configure the DSM by setting the MODE and CAP fields of the T1CCTL1 register. 8. Enable DSM (T1CCTL1.CMP=111) mode written to T1CC1L before the most significant bits are written to T1CC1H. The samples written must be signed 2’s complement values. The 2 least significant bits will always be treated as 0, thus the effective sample size is 14 bits. 13.6.9 Timer 1 Registers This section describes the following Timer 1 registers: • • • • T1CNTH – Timer 1 Counter High T1CNTL – Timer 1 Counter Low T1CTL – Timer 1 Control and Status T1CCTLn – Timer 1 Channel Capture/Compare Control • T1CCnH – Timer 1 Channel Capture/Compare Value High • T1CCnL Timer 1 Channel Capture/Compare Value Low n n n On each Timer 1 IRQ or Timer 1 DMA trigger, write a new sample to the T1CC1H:T1CC1L registers. The least significant bits must be T1CNTH (0xE3) – Timer 1 Counter High Bit 7:0 Name CNT[15:8] Reset 0x00 R/W R Description The TIMIF register is described in section 13.9.7. Timer count high order byte. Contains the high byte of the 16-bit timer counter buffered at the time T1CNTL is read. T1CNTL (0xE2) – Timer 1 Counter Low Bit 7:0 Name CNT[7:0] Reset 0x00 R/W R/W Description Timer count low order byte. Contains the low byte of the 16-bit timer counter. Writing anything to this register results in the counter being cleared to 0x0000. SWRS033E Page 121 of 239 CC1110Fx / CC1111Fx T1CTL (0xE4) – Timer 1 Control and Status Bit 7 Name CH2IF Reset 0 R/W R/W0 Description Timer 1 channel 2 interrupt flag 0 1 6 CH1IF 0 R/W0 No interrupt pending Interrupt pending Timer 1 channel 1 interrupt flag 0 1 No interrupt pending Interrupt pending 5 CH0IF 0 R/W0 Timer 1 channel 0 interrupt flag 0 1 No interrupt pending Interrupt pending 4 OVFIF 0 R/W0 Timer 1 counter overflow interrupt flag. Set when the counter reaches the terminal count value in free-running or modulo mode or when counter turns around on zero in up/down mode 0 1 No interrupt pending Interrupt pending 3:2 DIV[1:0] 00 R/W Prescaler divider value. Generates the active clock edge used to update the counter as follows: 00 01 10 11 Tick frequency/1 Tick frequency/8 Tick frequency/32 Tick frequency/128 Note: The prescaler counter is not reset when writing these bits, hence one prescaler period may be needed before updated data is used. 1:0 MODE[1:0] 00 R/W Timer 1 mode select. The timer operating mode is selected as follows: 00 01 10 11 Operation is suspended Free-running, repeatedly count from 0x0000 to 0xFFFF Modulo, repeatedly count from 0x0000 to T1CC0 Up/down, repeatedly count from 0x0000 to T1CC0 and from T1CC0 down to 0x0000 SWRS033E Page 122 of 239 CC1110Fx / CC1111Fx T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control Bit 7 Name CPSEL Reset 0 R/W R/W Description Timer 1 channel 0 capture select 0 1 6 IM 1 R/W Use normal capture input Use RF event(s) enabled in the RFIM register to trigger a capture Channel 0 interrupt mask 0 1 Interrupt disabled Interrupt enabled 5:3 CMP[2:0] 000 R/W Channel 0 compare mode select. Selects action on output when timer value equals compare value in T1CC0 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Reserved Reserved Reserved 2 MODE 0 R/W Mode. Select Timer 1 channel 0 capture or compare mode 0 1 Capture mode Compare mode 1:0 CAP[1:0] 00 R/W Channel 0 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on both edges T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value High Bit 7:0 Name T1CC0[15:8] Reset 0x00 R/W R/W Description Timer 1 channel 0 capture/compare value, high order byte. Set the DSM sample rate in DSM mode T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value Low Bit 7:0 Name T1CC0[7:0] Reset 0x00 R/W R/W Description Timer 1 channel 0 capture/compare value, low order byte Set the DSM sample rate in DSM mode SWRS033E Page 123 of 239 CC1110Fx / CC1111Fx T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control Bit 7 Name CPSEL Reset 0 R/W R/W Description Timer 1 channel 1 capture select 0 1 6 IM 1 R/W Use normal capture input Use RF event(s) enabled in the RFIM register to trigger a capture Channel 1 interrupt mask 0 1 Interrupt disabled Interrupt enabled 5:3 CMP[2:0] 000 R/W Channel 1 compare mode select. Selects action on output when timer value equals compare value in T1CC1 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Set when equal to T1CC1, clear when equal to T1CC0 Clear when equal to T1CC1, set when equal to T1CC0 DSM mode enable CMP = 111 Set the DSM speed 1/8 of timer tick speed 1/2 of timer tick speed DSM interpolator and output shaping configuration (DSM mode) DSM interpolator and output shaping enabled DSM interpolator enabled and output shaping disabled DSM interpolator disabled and output shaping enabled DSM interpolator and output shaping disabled 2 MODE 0 R/W CMP ≠ 111 Select Timer 1 channel 1 capture or compare mode 0 1 Capture mode Compare mode Channel 1 capture mode select (timer mode) 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on both edges 1:0 CAP[1:0] 00 R/W T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High Bit 7:0 Name T1CC1[15:8] Reset 0x00 R/W R/W Description Timer 1 channel 1 capture/compare value, high order byte DSM data high order byte (DSM mode) T1CC1L (0xDC) – Timer 1 Channel 1 Capture/Compare Value Low Bit 7:0 Name T1CC1[7:0] Reset 0x00 R/W R/W Description Timer 1 channel 1 capture/compare value, low order byte DSM data low order byte. The two least significant bits are not used. (DSM mode) SWRS033E Page 124 of 239 CC1110Fx / CC1111Fx T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control Bit 7 Name CPSEL Reset 0 R/W R/W Description Timer 1 channel 2 capture select 0 1 6 IM 1 R/W Use normal capture input Use RF event(s) enabled in the RFIM register to trigger a capture Channel 2 interrupt mask 0 1 Interrupt disabled Interrupt enabled 5:3 CMP[2:0] 000 R/W Channel 2 compare mode select. Selects action on output when timer value equals compare value in T1CC2 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Set when equal to T1CC2, clear when equal to T1CC0 Clear when equal to T1CC2, set when equal to T1CC0 Not used 2 MODE 0 R/W Mode. Select Timer 1 channel 2 capture or compare mode 0 1 Capture mode Compare mode 1:0 CAP[1:0] 00 R/W Channel 2 capture mode select 00 01 10 11 No capture Capture on rising edge Capture on falling edge Capture on both edges T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High Bit 7:0 Name T1CC2[15:8] Reset 0x00 R/W R/W Description Timer 1 channel 2 capture/compare value, high order byte T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low Bit 7:0 Name T1CC2[7:0] Reset 0x00 R/W R/W Description Timer 1 channel 2 capture/compare value, low order byte SWRS033E Page 125 of 239 CC1110Fx / CC1111Fx 13.7 MAC Timer (Timer 2) The MAC timer is designed for slot timing operations used by the MAC layer in an RF protocol. The timer includes a highly tunable prescaler allowing the user to select a timer interval that equals, or is an integer fraction of, a transmission slot. • 8-bit timer • 18-bit tunable prescaler 13.7.1 Timer Operation This section describes the operation of the timer. The timer count can be read from the T2CT SFR. At each active clock edge, the timer count is decremented by one. When the timer count reaches 0x00, the register bit T2CTL.TEX is set to 1. When T2CTL.TIG=0, the timer will not wrap around when the timer count reaches 0x00. When T2CTL.TIG=1, timer count will wrap around and start counting down from 0xFF. If T2CTL.INT=1, IRCON.T2IF will also be asserted when T2CTL.TEX is set to 1. An interrupt request will be generated if both T2CTL.INT and IEN1.T2IE are set to 1. When a new value is written to the timer count register, T2CT, this value is stored in the counter immediately. If an active clock edge and a write to T2CT occur at the same time, the written value will be decremented before it is stored. The 18 bit prescaler is controlled by: • Timer tick speed (CLKCON.TICKSPD) • T2CTL.TIP • Prescaler value (T2PR) All events in timer 2 are aligned to timer tick speed given by CLKCON.TICKSPD. T2CTL.TIP defines how fast the prescaler counter counts up towards its maximum value where it is reset and starts over again. The prescaler value, T2PR, defines the 8 MSB of the 18 bit counter and thus set the maximum value. The timer 2 interval / time slot, T, can be given as: T = T2PR · Val(T2CTL.TIP)/ timer tick speed, where the function Val(x) is set by T2CTL.TIP and defined as Val(00) = 64 Val(01) = 128 Val(10) = 256 Val(11) = 1024 Example: T2PR = 0x09 T2CTL.TIP = 10 CLKCON.TICKSPD = 101 (812.5 kHz @ when fxosc = 26 MHz) T = 9 · 256 / 812.5 kHz = 2.84 ·10-3 s 13.7.2 Timer 2 DMA Trigger There is one DMA trigger associated with Timer 2. This is the DMA trigger T2_OVFL, which is generated when T2CTL.TEX is set to 1. 13.7.3 Timer 2 Registers The SFRs associated with Timer 2 are listed in this section. These registers are the following: • T2CTL – Timer 2 Control • T2PR – Timer 2 Prescaler • T2CT – Timer 2 Count Note: These registers will be in their reset state when returning to active mode from PM2 and PM3. SWRS033E Page 126 of 239 CC1110Fx / CC1111Fx T2CTL (0x9E) – Timer 2 Control Bit 7 6 5 4 INT TEX Name Reset 0 0 0 0 R/W R/W0 R/W0 R/W R/W Description Reserved This bit is set to 1 when the timer count reaches 0x00. Writing a 1 to this bit has no effect Reserved. Always set to 0. Timer 2 Interrupt enable 0 1 3 2 TIG 0 0 R/W R/W Interrupt enabled Interrupt disabled Reserved. Always set to 0 Tick generator mode 0 1 Tick generator is running when T2CT not equal to 0x00. The tick generator will always start running form its null state. Tick generator is in free-running mode. If it is not already running it will start from its null state when this bit is set to 1 1:0 TIP[1:0] 00 R/W This value is used to calculate the timer 2 interval / time slot, T T = T2PR · Val(T2CTL.TIP)/ timer tick speed, 00 01 10 11 64 128 256 1024 T2CT (0x9C) – Timer 2 Count Bit 7:0 Name CNT[7:0] Reset 0x00 R/W R/W Description Timer count. Contents of 8-bit counter. T2PR (0x9D) – Timer 2 Prescaler Bit 7:0 Name PR[7:0] Reset 0x00 R/W R/W Description Timer prescaler multiplier. 0x00 is interpreted as 256 SWRS033E Page 127 of 239 CC1110Fx / CC1111Fx 13.8 Sleep Timer CC1110Fx/CC1111Fx exits from PM{0-2} and The Sleep Timer is used to control when the power RC oscillator to clock the Sleep Timer, tEvent0 is given by: hence the Sleep Timer can be used to implement a wake up functionality which enables CC1110Fx/CC1111Fx to periodically wake up to active mode and listen for incoming RF packets. 13.8.1 Sleep Timer Operation This section describes the operation of the timer. Note: In this section of the document, fRef is used to denote the reference frequency for the synthesizer. For CC1110Fx fref=fXOS and for t Event 0 = 750 ⋅ EVENT 0 ⋅ 25⋅WOR _ RES f ref If the 32.768 kHz crystal oscillator is used to clock the Sleep Timer, tEvent0 is calculated as follows: t Event 0 = 1 ⋅ EVENT 0 ⋅ 25⋅WOR _ RES 32768 CC1111Fx, f ref = f XOSC 2 When referring to the low power RCOSC, calibrated values are assumed The Sleep Timer consists of a 31-bit counter. The appropriate bits of this counter are selected according to a resolution setting determined by the WORCTRL.WOR_RES register bits. The Sleep Timer is either clocked by the 32.768 kHz crystal oscillator or by the low power RC oscillator (fref / 750). The timer can only be used in PM0, PM1, and PM2. The Sleep Timer has a programmable timing event called Event 0. While in PM0, PM1, or PM2, reaching Event 0 will make the CC1110Fx/CC1111Fx enter active mode. The time between two consecutive Event 0’s (tEvent0) is programmed with a mantissa value given by WOREVT1.EVENT0 and WOREVT0.EVENT0, and an exponent value set by WORCTRL.WOR_RES. When using the low The time from the CC1110Fx/CC1111Fx enters PM2 until the next Event 0 is programmed to appear (tSLEEPmin) should be larger than 11.08 ms when fref is 26 MHz and 12 ms when fref is 24 MHz (Sleep Timer clocked by the low power RC oscillator). t SLEEPmin = 750 ⋅ 384 f ref When the Sleep Timer is clocked by the 32.768 kHz crystal oscillator, tSLEEPmin = 11.72 ms (384/32768). 13.8.2 Sleep Timer and Power Modes Entering PM0-2 has to be aligned to a positive edge on the 32 kHz clock source. There has to be at least two positive edges on the 32 kHz clock source between WORCTRL.WOR_RESET being asserted and updating EVENT0 and entering PM0-2. If EVENT0 is to be updated to a value lower than current time value, WORCTRL.WOR_RESET has to be asserted first. The following two code examples should be used in order to set correct sleep time: // Updating Event0 to a value higher than current timer value char temp = WORTIME0; while(temp == WORTIME0); // Wait until a positive 32 kHz edge WOREVT1 = desired event0; // Set Event0, high byte WOREVT0 = desired event0; // Set Event0, low byte PCON |= 0x01; // Enter PM // Updating Event0 to a value lower than current time value WORCTRL |= 0x04; // Reset Sleep Timer char temp = WORTIME0; while(temp == WORTIME0); // Wait until a positive 32 kHz edge temp = WORTIME0; while(temp == WORTIME0); // Wait until a positive 32 kHz edge WOREVT1 = desired event0; // Set Event0, high byte WOREVT0 = desired event0; // Set Event0, low byte PCON |= 0x01; // Enter PM SWRS033E Page 128 of 239 CC1110Fx / CC1111Fx 13.8.3 Low Power RC Oscillator and Timing This section applies to using the low power RC oscillator as clock source for the Sleep Timer. The frequency of the low-power RC oscillator, which can be used as clock source for the Sleep Timer, varies with temperature and supply voltage. In order to keep the frequency as accurate as possible, the RC oscillator should be calibrated whenever possible, which is when the high speed crystal oscillator is running and the chip is in active mode or PM0. When the chip goes to PM1 or PM2, the RC oscillator will use the last valid calibration result. The frequency of the low power RC oscillator is therefore locked to fref / 750. 13.8.4 Sleep Timer Interrupt The Sleep Timer generates the Sleep Timer interrupt, ST, when Event 0 occurs. This interrupt source can be masked using the WORIRQ.EVENT0_MASK interrupt mask bit. The interrupt flag bit WORIRQ.EVENT0_FLAG will be set when Event 0 occurs. 13.8.5 Sleep Timer DMA Trigger There is one DMA trigger associated with the Sleep Timer. This is the DMA trigger ST, which is generated when Event 0 occurs. 13.8.6 Sleep Timer Registers This section describes the SFRs associated with the Sleep Timer. WORTIME0 (0xA5) – Sleep Timer Low Byte Bit 7:0 Name WORTIME[7:0] Reset 0x00 R/W R Description 8 LSB of the16 bits selected from the 31-bit Sleep Timer according to the setting of WORCTRL.WOR_RES[1:0] WORTIME1 (0xA6) – Sleep Timer High Byte Bit 7:0 Name WORTIME[15:8] Reset 0x00 R/W R Description 8 MSB of the16 bits selected from the 31-bit Sleep Timer according to the setting of WORCTRL.WOR_RES[1:0] WOREVT1 (0xA4) – Sleep Timer Event0 Timeout High Bit 7:0 Name EVENT0[15:8] Reset 0x87 R/W R/W Description High byte of Event 0 timeout register Sleep Timer clocked by low power RCOSC Sleep Timer clocked by 32.768 kHz crystal oscillator t Event 0 = 750 ⋅ EVENT 0 ⋅ 25⋅WOR _ RES f ref t Event0 = 1 ⋅ EVENT 0 ⋅ 25⋅WOR _ RES 32768 WOREVT0 (0xA3) – Sleep Timer Event0 Timeout Low Bit 7:0 Name EVENT0[7:0] Reset 0x6B R/W R/W Description Low byte of Event 0 timeout register SWRS033E Page 129 of 239 CC1110Fx / CC1111Fx WORCTRL (0xA2) – Sleep Timer Control Bit 7 6:4 3 2 1:0 WOR_RESET WOR_RES[1:0] Name Reset 111 0 00 R/W R0 R/W R0 R0/W1 R/W Description Not used Reserved. Always write 000 Not used Reset timer. The timer will be reset to 4. Sleep Timer resolution Controls the resolution and maximum timeout for the Sleep Timer. Adjusting the resolution does not affect the clock cycle counter: Setting 00 01 10 11 Resolution (1 LSB) 1 period 2 periods 2 periods 2 periods 15 10 5 Bits selected from the 31-bit Sleep Timer 15:0 20:5 25:10 30:15 WORIRQ (0xA1) – Sleep Timer Interrupt Control Bit 7:6 5 4 EVENT0_MASK Name Reset 00 0 0 R/W R0 R/W R/W Reserved. Always write 0 Event 0 interrupt mask 0 1 3:2 1 0 EVENT0_FLAG 00 0 0 R0 R/W0 R/W0 Reserved Event 0 interrupt flag 0 1 No interrupt is pending Interrupt is pending Interrupt is disabled Interrupt is enabled Description SWRS033E Page 130 of 239 CC1110Fx / CC1111Fx 13.9 8-bit Timers, Timer 3 and Timer 4 Timer 3 and Timer 4 are two 8-bit timers which supports typical timer/counter functions such as output compare and PWM functions. The timers have two independent compare channels each and use one I/O pin per channel. The features of Timer 3/4 are as follows: • Two compare channels • Set, clear, or toggle output compare • Free-running, modulo, down, or up/down counter operation • Clock prescaler for divide by 1, 2, 4, 8, 16, 32, 64, 128 • Interrupt request generation on compare and when reaching the terminal count value • DMA trigger function Note: In the following sections, an n in the register name represent the channel number 0 or 1 if nothing else is stated. An x in the register name refers to the timer number, 3 or 4 13.9.1 8-bit Timer Counter Both timers consist of an 8-bit counter that increments or decrements at each active clock edge. The frequency of the active clock edges is given by CLKCON.TICKSPD and TxCTL.DIV. CLKCON.TICKSPD is used to set the timer tick speed. The timer tick speed will vary from 203.125 kHz to 26 MHz for CC1110Fx and 187.5 kHz to 24 MHz for CC1111Fx (given the use of a 26 MHz or 48 MHz crystal respectively). Note that the clock speed of the system clock is not affected by the TICKSPD setting. The timer tick speed is further divided in Timer 3/4 by the prescaler value set by TxCTL.DIV. This prescaler value can be 1, 2, 4, 8, 16, 32, 64, or 128. Thus the lowest clock frequency used by Timer 3/4 is 1.587 kHz and the highest is 26 MHz when a 26 MHz crystal oscillator is used as system clock source (CC1110Fx). The lowest clock frequency used by Timer 3/4 is 1.465 kHz and the 0xFF highest is 24 MHz for CC1111Fx. When the high speed RC oscillator is used as system clock source, the highest clock frequency used by Timer 3/4 is fXOSC/2 for CC1110Fx and 12 MHz for CC1111Fx, given that the HS RCOSC has been calibrated. The counter operates as either a free-running counter, a modulo counter, a down counter, or as an up/down counter for use in centrealigned PWM. It is possible to read the 8-bit counter value through the SFR TxCNT. Writing a 1 to TxCTL.CLR will reset the 8-bit counter. The counter may produce an interrupt request when the terminal count value (overflow) is reached (see section 13.9.2.1 - 13.9.2.4). It is possible to start and halt the counter with the TxCTL.START bit. The counter is started when a 1 is written to TxCTL.START. If a 0 is written to TxCTL.START, the counter halts at its present value. 13.9.2 Timer 3/4 Operation In general, the control register TxCTL is used to control the timer operation. The timer modes are described in the following four sections. 13.9.2.1 Free-running Mode In free-running mode the counter starts from 0x00 and increments at each active clock edge. When the counter reaches the terminal count value 0xFF (overflow), the counter is loaded with 0x00 and continues incrementing its value as shown in Figure 34. When 0xFF is reached, the TIMIF.TxOVFIF flag is set. The IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. The free-running mode can be used to generate independent time intervals and output signal frequencies. 0x00 OVFIF = 1 OVFIF = 1 Figure 34: Free-running Mode SWRS033E Page 131 of 239 CC1110Fx / CC1111Fx 13.9.2.2 Modulo Mode In modulo mode the counter starts from 0x00 and increments at each active clock edge. When the counter value matches the terminal count value TxCC0, the counter is loaded with 0x00 and continues incrementing its value as shown in Figure 35. When TxCC0 is reached, the TIMIF.TxOVFIF flag is set. The TxCC0 IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. Modulo mode can be used for applications where a period other than 0xFF is required. 0x00 OVFIF = 1 OVFIF = 1 Figure 35: Modulo Mode 13.9.2.3 Down Mode In down mode, after the timer has been started, the counter is loaded with the contents in TxCC0. The counter then counts down to 0x00 (terminal count value) and remains at 0x00 as shown in Figure 36. The flag TIMIF.TxOVFIF is set when 0x00 is reached. TxCC0 IRCON.TxIF is only asserted if the corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. The timer down mode can generally be used in applications where an event timeout interval is required. 0x00 OVFIF = 1 Figure 36: Down Mode 13.9.2.4 Up/Down Mode In up/down mode the counter starts from 0x00 and increments at each active clock edge. When the counter value matches the terminal count value TxCC0, the counter counts down until 0x00 is reached and it starts counting up again as shown in Figure 37. When 0x00 is reached, the TIMIF.TxOVFIF flag is set. The IRCON.TxIF flag is only asserted if the TxCC0 corresponding interrupt mask bit TxCTL.OVFIM is set. An interrupt request is generated when both TxCTL.OVFIM and IEN1.TxEN are set to 1. The up/down mode can be used when symmetrical output pulses are required with a period other than 0xFF, and therefore allows implementation of centrealigned PWM output applications. 0x00 OVFIF = 1 OVFIF = 1 Figure 37: Up/Down Mode SWRS033E Page 132 of 239 CC1110Fx / CC1111Fx 13.9.3 Channel Mode Control The channel mode is set with each channel’s control and status register TxCCTLn. Note: before an I/O pin can be used by the timer, the required I/O pin must be configured as a Timer 3/4 peripheral pin as described in section 13.4.6 on page 64. 13.9.4 Output Compare Mode In output compare mode the I/O pin associated with a channel is set as an output. After the timer has been started, the contents of the counter are compared with the contents of the channel compare register TxCCn. If the compare register equals the counter contents, the output pin is set, reset, or toggled according to the compare output mode setting of TxCCTLn.CMP. Note that all edges on output pins are glitch-free when operating in a given compare output mode. Writing to the compare register TxCC0 does not take effect on the output compare value until the counter value is 0x00. Writing to the compare register TxCC1 takes effect immediately. When a compare occurs, the interrupt flag for the appropriate channel (TIMIF.TxCHnIF) is asserted. The IRCON.TxIF flag is only asserted if the corresponding interrupt mask bit TxCCTLn.IM is set to 1. An interrupt request is generated if the corresponding interrupt mask bit is set together with IEN1.TxEN. When operating in up-down mode, the interrupt flag for channel 0 is set when the counter reaches 0x00 instead of when a compare occurs. For simple PWM use, output compare modes 3 and 4 are preferred. 13.9.5 Timer 3 and 4 Interrupts There is one interrupt vector assigned to each of the timers. These are T3 and T4 (interrupt #11 and #12, see Table 39). The following timer events may generate an interrupt request: • Counter reaches terminal count value (overflow) or turns around on zero / reach zero • Output compare event The register bits TIMIF.T3OVFIF, TIMIF.T4OVFIF, TIMIF.T3CH0IF, TIMIF.T3CH1IF, TIMIF.T4CH0IF, and TIMIF.T4CH1IF contains the interrupt flags for the two terminal count value event (overflow), and the four channel compare events, respectively. These flags will be asserted regardless off the channel n interrupt mask bit (TxCCTLn.IM). The CPU interrupt flag, IRCON.TxIF will only be asserted if one or more of the channel n interrupt mask bits are set to 1. An interrupt request is only generated when the corresponding interrupt mask bit is set together with IEN1.TxEN. The interrupt mask bits are T3CCTL0.IM, T3CCTL1.IM, T4CCTL0.IM, T4CCTL1.IM, T3CTL.OVFIM, and T4CTL.OVFIM. Note that enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. When the timer is used in Free-running Mode or Modulo Mode the interrupt flags are set as follows: • TIMIF.TxCH0IF and TIMIF.TxCH1IF are set on compare event • TIMIF.TxOVFIF is set when counter reaches terminal count value (overflow) When the timer is used in Down Mode the interrupt flags are set as follows: • TIMIF.TxCH0IF and TIMIF.TxCH1IF are set on compare event • TIMIF.TxOVFIF is set when counter reaches zero When the timer is used in Up/Down Mode the interrupt flags are set as follows: • TIMIF.TxCH0IF and TIMIF.TxOVFIF are set when the counter turns around on zero • TIMIF.TxCH1IF is set on compare event In addition, the CPU interrupt flag, IRCON.TxIF will be asserted if the channel n interrupt mask bit (TxCCTLn.IM) is set to 1. 13.9.6 Timer 3 and Timer 4 DMA Triggers There are two DMA triggers associated with Timer 3 and two DMA triggers associated with Timer 4. These are DMA triggers T3_CH0, T3_CH1, T4_CH0, and T4_CH1, which are generated on timer compare events as follows: • • • • T3_CH0: Timer 3 channel 0 compare T3_CH1: Timer 3 channel 1 compare T4_CH0: Timer 4 channel 0 compare T4_CH1: Timer 4 channel 1 compare SWRS033E Page 133 of 239 CC1110Fx / CC1111Fx 13.9.7 Timer 3 and 4 Registers This section describes the following Timer 3 and Timer 4 registers: • T3CNT - Timer 3 Counter • T3CTL - Timer 3 Control • T3CCTLn - Timer 3 Channel n Compare Control • T3CCn - Timer 3 Channel n Compare Value T3CNT (0xCA) – Timer 3 Counter Bit 7:0 Name CNT[7:0] Reset 0x00 R/W R Description Timer count byte. Contains the current value of the 8-bit counter • T4CNT - Timer 4 Counter • T4CTL - Timer 4 Control • T4CCTLn - Timer 4 Channel n Compare Control • T4CCn - Timer 4 Channel n Compare Value • TIMIF - Timer 1/3/4 Interrupt Mask/Flag T3CTL (0xCB) – Timer 3 Control Bit 7:5 Name DIV[2:0] Reset 000 R/W R/W Description Prescaler divider value. Generates the active clock edge used to update the counter as follows: 000 001 010 011 100 101 110 111 Tick frequency /1 Tick frequency /2 Tick frequency /4 Tick frequency /8 Tick frequency /16 Tick frequency /32 Tick frequency /64 Tick frequency /128 Note: Changes to these bits has immediate effect on the frequency of the active clock edges. 4 START 0 R/W Start timer 0 1 3 OVFIM 1 R/W0 Suspended Normal operation Overflow interrupt mask 0 1 Interrupt disabled Interrupt enabled 2 CLR 0 R0/W1 Clear counter. Writing a 1 resets the counter to 0x00. This bit will be 0 when returning from PM2 and PM3 1:0 MODE[1:0] 00 R/W Timer 3 mode select. The timer operating mode is selected as follows: 00 01 10 11 Free running, repeatedly count from 0x00 to 0xFF Down, count from T3CC0 to 0x00 Modulo, repeatedly count from 0x00 to T3CC0 Up/down, repeatedly count from 0x00 to T3CC0 and from T3CC0 down to 0x00 SWRS033E Page 134 of 239 CC1110Fx / CC1111Fx T3CCTL0 (0xCC) – Timer 3 Channel 0 Capture/Compare Control Bit 7 6 IM Name Reset 1 R/W R0 R/W Description Not used Channel 0 interrupt mask 0 1 5:3 CMP[2:0] 000 R/W Interrupt disabled Interrupt enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T3CC0 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Set output on compare, clear on 0xFF Clear output on compare, set on 0x00 Not used 2 MODE 0 R/W Timer 3 channel 0 compare mode enable 0 1 Disable Enable 1:0 00 R/W Reserved. Always write 00 T3CC0 (0xCD) – Timer 3 Channel 0 Compare Value Bit 7:0 Name VAL[7:0] Reset 0x00 R/W R/W Description Timer 3 channel 0 compare value SWRS033E Page 135 of 239 CC1110Fx / CC1111Fx T3CCTL1 (0xCE) – Timer 3 Channel 1 Compare Control Bit 7 6 IM Name Reset 1 R/W R0 R/W Description Not used Channel 1 interrupt mask 0 1 5:3 CMP[2:0] 000 R/W Interrupt disabled Interrupt enabled Channel 1 compare output mode select. Specified action on output when timer value equals compare value in T3CC1 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Set output on compare, clear on T3CC0 Clear output on compare, set on T3CC0 Not used 2 MODE 0 R/W Timer 3 channel 1 compare mode enable 0 1 Disable Enable 1:0 00 R/W Reserved. Always write 00 T3CC1 (0xCF) – Timer 3 Channel 1 Compare Value Bit 7:0 Name VAL[7:0] Reset 0x00 R/W R/W Description Timer 3 channel 1 compare value T4CNT (0xEA) – Timer 4 Counter Bit 7:0 Name CNT[7:0] Reset 0x00 R/W R Description Timer count byte. Contains the current value of the 8-bit counter SWRS033E Page 136 of 239 CC1110Fx / CC1111Fx T4CTL (0xEB) – Timer 4 Control Bit 7:5 Name DIV[2:0] Reset 000 R/W R/W Description Prescaler divider value. Generates the active clock edge used to update the counter as follows: 000 001 010 011 100 101 110 111 Tick frequency /1 Tick frequency /2 Tick frequency /4 Tick frequency /8 Tick frequency /16 Tick frequency /32 Tick frequency /64 Tick frequency /128 Note: Changes to these bits has immediate effect on the frequency of the active clock edges. 4 START 0 R/W Start timer 0 1 3 OVFIM 1 R/W0 Suspended Normal operation Overflow interrupt mask 0 1 Interrupt disabled Interrupt enabled 2 CLR 0 R0/W1 Clear counter. Writing a 1 resets the counter to 0x00. This bit will be 0 when returning from PM2 and PM3 1:0 MODE[1:0] 00 R/W Timer 4 mode select. The timer operating mode is selected as follows: 00 01 10 11 Free running, repeatedly count from 0x00 to 0xFF Down, count from T4CC0 to 0x00 Modulo, repeatedly count from 0x00 to T4CC0 Up/down, repeatedly count from 0x00 to T4CC0 and from T4CC0 down to 0x00 SWRS033E Page 137 of 239 CC1110Fx / CC1111Fx T4CCTL0 (0xEC) – Timer 4 Channel 0 Capture/Compare Control Bit 7 6 IM Name Reset 1 R/W R0 R/W Description Not used Channel 0 interrupt mask 0 1 5:3 CMP[2:0] 000 R/W Interrupt disabled Interrupt enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T4CC0 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Set output on compare, clear on 0xFF Clear output on compare, set on 0x00 Not used 2 MODE 0 R/W Timer 4 channel 0 compare mode enable 0 1 Disable Enable 1:0 00 R/W Reserved. Always write 00 T4CC0 (0xED) – Timer 4 Channel 0 Compare Value Bit 7:0 Name VAL[7:0] Reset 0x00 R/W R/W Description Timer 4 channel 0 compare value SWRS033E Page 138 of 239 CC1110Fx / CC1111Fx T4CCTL1 (0xEE) – Timer 4 Channel 1 Compare Control Bit 7 6 IM Name Reset 1 R/W R0 R/W Description Not used Channel 0 interrupt mask 0 1 5:3 CMP[2:0] 000 R/W Interrupt disabled Interrupt enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T4CC0 000 001 010 011 100 101 110 111 Set output on compare Clear output on compare Toggle output on compare Set output on compare-up, clear on 0 (clear on compare-down in up/down mode) Clear output on compare-up, set on 0 (set on compare-down in up/down mode) Set output on compare, clear on T4CC0 Clear output on compare, set on T4CC0 Not used 2 MODE 0 R/W Timer 4 channel 1 compare mode enable 0 1 Disable Enable 1:0 00 R/W Reserved. Always write 00 T4CC1 (0xEF) – Timer 4 Channel 1 Compare Value Bit 7:0 Name VAL[7:0] Reset 0x00 R/W R/W Description Timer 4 channel 1 compare value SWRS033E Page 139 of 239 CC1110Fx / CC1111Fx TIMIF (0xD8) – Timers 1/3/4 Interrupt Mask/Flag Bit 7 6 OVFIM Name Reset 1 R/W R0 R/W Description Not used Timer 1 overflow interrupt mask 0 1 5 T4CH1IF 0 R/W0 Interrupt disabled Interrupt enabled Timer 4 channel 1 interrupt flag. Writing a 1 has no effect 0 1 No interrupt is pending Interrupt is pending 4 T4CH0IF 0 R/W0 Timer 4 channel 0 interrupt flag. Writing a 1 has no effect 0 1 No interrupt is pending Interrupt is pending 3 T4OVFIF 0 R/W0 Timer 4 overflow interrupt flag. Writing a 1 has no effect 0 1 No interrupt is pending Interrupt is pending 2 T3CH1IF 0 R/W0 Timer 3 channel 1 interrupt flag. Writing a 1 has no effect 0 1 No interrupt is pending Interrupt is pending 1 T3CH0IF 0 R/W0 Timer 3 channel 0 interrupt flag. Writing a 1 has no effect 0 1 No interrupt is pending Interrupt is pending 0 T3OVFIF 0 R/W0 Timer 3 overflow interrupt flag. Writing a 1 has no effect 0 1 No interrupt is pending Interrupt is pending SWRS033E Page 140 of 239 CC1110Fx / CC1111Fx 13.10 ADC • Selectable decimation rates which also sets the resolution (7 to 12 bits). • Eight individual input channels, singleended or differential (CC1111Fx has only six channels) • Reference voltage selectable as internal, external single ended, external differential, or VDD. • Interrupt request generation • DMA triggers at end of conversions • Temperature sensor input • Battery measurement capability 13.10.1 ADC Introduction The ADC supports up to 12-bit analog-todigital conversion. The ADC includes an analog multiplexer with up to eight individually configurable channels, reference voltage generator, and conversion results written to memory through DMA. Several modes of operation are available. All referanses to VDD applies to voltage on the pin AVDD. The main features of the ADC are as follows: Figure 38: ADC Block Diagram 13.10.2 ADC Operation This section describes the general setup and operation of the ADC and describes the usage of the ADC control and status registers accessed by the CPU. 13.10.2.1 ADC Core The ADC is capable of converting an analog input into a digital representation with up to 12 bits resolution. The ADC uses a selectable positive reference voltage. 13.10.2.2 ADC Inputs The signals on the P0 port pins can be used as ADC inputs. Note: P0_6 and P0_7 do not exist on CC1111Fx, hence only six input channels are available (AIN0 – AIN5) To configure a P0 pin to be used as an ADC input the corresponding bit in the ADCCFG register must be set to 1. The default value in this register disables the ADC inputs. Please see section 13.4.7 on page 95 for more details on how to configure the ADC input pins. In the following these port pin will be referred to as the AIN0 - AIN7 pins. The ADC can be set up to automatically perform a sequence of conversions and optionally perform an extra conversion. It is possible to configure the inputs as singleended or differential inputs. In the case where differential inputs are selected, the differential inputs consist of the input pairs AIN0 - AIN1, AIN2 - AIN3, AIN4 - AIN5, and AIN6 - AIN7. Note that neither a negative supply, nor a supply larger than VDD (unregulated power) can be applied to these pins. It is the difference between the pairs that are converted in differential mode. In addition to the input pins AIN0 - AIN7, the output of an on-chip temperature sensor can be selected as an input to the ADC for temperature measurements. It is also possible to select a voltage corresponding to VDD/3 as an ADC input. This input allows the implementation of e.g. a battery monitor in applications where this feature is required. SWRS033E Page 141 of 239 CC1110Fx / CC1111Fx 13.10.2.3 ADC Conversion Sequences The ADC will perform a sequence of conversions, and the results can be moved to memory (through DMA) without any interaction from the CPU. The ADCCON2.SCH register bits are used to define an ADC conversion sequence from the ADC inputs. If some of the inputs in this sequence are not configured to be analog input signals in the ADCCFG register, these will be skipped. For differential inputs both input pins must be configured to be analog input signals. • 0000 ≤ ADCCON2.SCH ≤ 0111: Singleended inputs • 1000 ≤ ADCCON2.SCH ≤ 1011: Differential inputs • 1100 ≤ ADCCON2.SCH ≤ 1111: GND, internal voltage reference, temp. sensor, and VDD/3 When ADCCON2.SCH is set to a value less than 1000 a conversion sequence will contain a conversion from each ADC input, starting at AIN0 and ending at the input programmed in ADCCON2.SCH. When ADCCON2.SCH is set to a value ranging from 1000 to 1011, the sequence will start at the differential input pair (AIN0 – AIN1) and stop at the input pair given by ADCCON2.SCH. For even higher settings, only single conversions are performed. In addition to this sequence of conversions, the ADC can be programmed to perform a single conversion (see next section). 13.10.2.4 ADC Operating Modes This section describes the operating modes and initialization of conversions. The ADC has three control registers: ADCCON1, ADCCON2, and ADCCON3. These registers are used to configure the ADC and to report status. The ADCCON1.EOC bit is a status bit that is set high when a conversion ends and cleared when ADCH is read. The ADCCON1.ST bit is used to start a sequence of conversions. A sequence will start when this bit is set high, ADCCON1.STSEL=11, and no conversion is currently running. When the sequence is completed, this bit is automatically cleared. The ADCCON1.STSEL bits select which event that will start a new sequence of conversions. The options which can be selected are rising edge on external pin P2_0, end of previous sequence, a Timer 1 channel 0 compare event, or ADCCON1.ST is 1. ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed when no conversion is running. The ADCCON2.SDIV bits select the decimation rate (and thereby also the resolution and time required to complete a conversion and sample rate). The decimation rate should only be changed when no conversion is running. The ADCCON2.SCH register bits are used to define an ADC conversion sequence. The ADC can be programmed to perform a single conversion (single-ended, differential, GND, internal voltage reference, temperature sensor, or VDD/3). This is called an extra conversion and is controlled with the ADCCON3 register. This conversion is triggered by writing to ADCCON3. If this register is written while the ADC is running, the conversion will take place as soon as the sequence has completed. If the register is written while the ADC is not running, the conversion will take place immediately after the ADCCON3 register is updated. The ADCCON3 register controls which input to use, reference voltage, and decimation rate for the extra conversion. The coding of the register bits is exactly as for ADCCON2. Note: If a sequence of conversions is started without setting any of the P0 pins as analog inputs, ADCCON2.SCH and ADCCON1.EOC will still be updated, as if the conversions had taken place. 13.10.2.5 ADC Reference Voltage The positive reference voltage for analog-todigital conversions is selectable as either an internally generated 1.25 V voltage, the VDD on AVDD pin, an external voltage applied to the AIN7 input pin, or a differential voltage applied to the AIN6 - AIN7 inputs (AIN6 must have the highest input voltage). It is possible to select the reference voltage as the input to the ADC in order to perform a conversion of the reference voltage e.g. for calibration purposes. Similarly, it is possible to select the ground terminal GND as an input. Note: P0_6 and P0_7 do not exist on CC1111Fx, hence it is not possible to use external voltage reference for the ADC on the CC1111Fx. SWRS033E Page 142 of 239 CC1110Fx / CC1111Fx 13.10.2.6 ADC Conversion Results The digital conversion result is represented in two's complement form. For single ended configurations the result is always positive (the result is the difference between ground and the input signal AINn, where n is 0, 1, 2, …, 7) and will be a value between 0 and 2047. The maximum value is reached when the input amplitude is equal VREF, the selected voltage reference. For differential configurations the difference between two pin pairs are converted and this difference can be negatively signed. For 12-bit resolution the digital conversion result is 2047 when the analog input is equal to VREF, and the conversion result is -2048 when the analog input is equal to -VREF. The digital conversion result is available in ADCH and ADCL when ADCCON1.EOC is set to 1. Note that the conversion result always resides in MSB section of ADCH:ADCL. When reading the ADCCON2.SCH bits, the number returned will indicate what the last conversion was. Notice that when the value written to ADCCON2.SCH is less than 1100, the number returned will be the number written + 1. For example, after a sequence of conversions from AIN0 to AIN4 has completed, ADCCON2.SCH will be read as 0101, while after a single conversion of the temperature sensor has completed, the register field will be read as 1110 (same as the value written to it). If an extra conversion has been initiated by writing to ADCCON3.ECH, ADCCON2.SCH will be updated, after the conversion has completed, with the same value as written to ADCCON3.ECH, even if this value was less than 1100. 13.10.2.7 ADC Conversion Timing The high speed crystal oscillator should be selected as system clock when the ADC is used and CLKCON.CLKSPD should be 000. The ADC runs on a clock which is the system clock divided by 6 to give a 4.33/4 MHz ADC clock. Both the delta-sigma modulator and the decimation filter use the ADC clock for their calculations. Using other frequencies will affect the results, and conversion time. All data presented within this data sheet assume the use of the high speed crystal oscillator. The time required to perform a conversion depends on the selected decimation rate. When, for instance, the decimation rate is set to 128, the decimation filter uses exactly 128 ADC clock periods to calculate the result. When a conversion is started, the input multiplexer is allowed 16 ADC clock periods to settle in case the channel has been changed since the previous conversion. The 16 clock cycles settling time applies to all decimation rates. This means that the conversion time, Tconv, is given by: Tconv = (decimation rate + 16) x T where 0.22 µs ≤ T ≤ 0.23 µs for CC1110Fx, depending on the frequency of the high speed crystal oscillator T = 0.25 µs for CC1111Fx 13.10.2.8 ADC Interrupts The ADC will only generate an interrupt when an extra conversion has completed. 13.10.2.9 ADC DMA Triggers DMA triggers 20 – 28 are associated with single-ended or differential conversion sequences (ADCCON2.SCH ≤ 1100). The ADC will generate a DMA trigger event when a new sample is ready from a conversion in the sequence. The same is the case if a single conversion is completed (ADCCON2.SCH ≥ 1100). Be aware that DMA trigger number 27 and 28 are shared with the I2S module. In addition there is one DMA trigger, ADC_CHALL, which is active when new data is ready from any of the conversions in the ADC conversion sequence and from the single conversion defined by ADCCON2.SCH. A completion of an extra conversion will not generate a trigger event. The DMA triggers are listed in Table 51 on page 108. SWRS033E Page 143 of 239 CC1110Fx / CC1111Fx 13.10.3 ADC Registers This section describes the ADC registers. ADCL (0xBA) – ADC Data Low Bit 7:4 Name ADC[3:0] Reset 0000 R/W R Description Least significant part of ADC conversion result. The decimation rate configures through ADCCON2.SDIV determines how many of these bits are relevant to use. 3:0 0000 R ADCH (0xBB) – ADC Data High Bit 7:0 Name ADC[11:4] Reset 0x00 R/W R Description Most significant part of ADC conversion result. The decimation rate configures through ADCCON2.SDIV determines how many of these bits are relevant to use. ADCCON1 (0xB4) – ADC Control 1 Bit 7 Name EOC Reset 0 R/W R H0 Description End of conversion. Cleared when ADCH has been read. If a new conversion is completed before the previous data has been read, the EOC bit will remain high. 0 1 6 ST 0 R/W1 Conversion not complete Conversion completed Start conversion. Read as 1 until conversion has completed 0 1 No conversion in progress Start a conversion sequence if ADCCON1.STSEL=11 and no sequence is running. 5:4 STSEL[1:0] 11 R/W Start select. Selects which event that will start a new conversion sequence. 00 01 10 11 External trigger on P2_0 pin. Full speed. Do not wait for triggers. Timer 1 channel 0 compare event ADCCON1.ST=1 3:2 RCTRL[1:0] 00 R/W Controls the 16 bit random generator. When set to 01, the setting will automatically return to 00 when operation has completed. 00 01 10 11 Normal (13x unrolling) or operation completed Clock the LFSR once (no unrolling). Reserved Stopped. Random generator is turned off. 1:0 11 R/W Reserved. Always write 11 SWRS033E Page 144 of 239 CC1110Fx / CC1111Fx ADCCON2 (0xB5) – ADC Control 2 Bit 7:6 Name SREF[1:0] Reset 00 R/W R/W Description Selects reference voltage used for the sequence of conversions 00 01 10 11 5:4 SDIV[1:0] 01 R/W Internal 1.25V reference External reference on AIN7 pin (only CC1110Fx) VDD on AVDD pin External reference on AIN6-AIN7 differential input (only CC1110Fx) Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00 01 10 11 64 dec rate (7 bits resolution) 128 dec rate (9 bits resolution) 256 dec rate (10 bits resolution) 512 dec rate (12 bits resolution) 3:0 SCH[3:0] 00 R/W Sequence Channel Select. Selects the end of the sequence. SCH ≤ 0111: A conversion sequence will contain a conversion from each ADC input, starting at AIN0 and ending at the input programmed in ADCCON2.SCH. 1000 ≤ SCH ≤ 1011: The sequence will start at the differential input pair (AIN0 – AIN1) and stop at the input pair given by ADCCON2.SCH. SCH ≥ 1100: Only single conversions are performed. When reading the ADCCON2.SCH bits, the number returned will indicate what the last conversion was. Please see section 13.10.2.6 for details. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 GND Positive voltage reference Temperature sensor VDD/3 SWRS033E Page 145 of 239 CC1110Fx / CC1111Fx ADCCON3 (0xB6) – ADC Control 3 Bit 7:6 Name EREF[1:0] Reset 00 R/W R/W Description Selects reference voltage used for the extra conversion 00 01 10 11 5:4 EDIV[1:0] 00 R/W Internal 1.25V reference External reference on AIN7 pin (only CC1110Fx) VDD on AVDD pin External reference on AIN6-AIN7 differential input (only CC1110Fx) Sets the decimation rate used for the extra conversion. The decimation rate also determines the resolution and time required to complete the conversion. 00 01 10 11 64 dec rate (7 bits resolution) 128 dec rate (9 bits resolution) 256 dec rate (10 bits resolution) 512 dec rate (12 bits resolution) 3:0 ECH[3:0] 0000 R/W Extra channel select. An extra conversion will be triggered by writing to these bits. If they are written while the ADC is running, the conversion will take place as soon as the sequence has completed. If the bits are written while the ADC is not running, the conversion will take place immediately after this register has been updated. The bits are automatically cleared when the extra conversion has finished. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 GND Positive voltage reference Temperature sensor VDD/3 SWRS033E Page 146 of 239 CC1110Fx / CC1111Fx 13.11 Random Number Generator 13.11.1 Introduction The random number following features. generator has the The random number generator is a 16-bit Linear Feedback Shift Register (LFSR) with polynomial X + X + X + 1 (i.e. CRC16). It uses different levels of unrolling depending on the operation it performs. The basic version (no unrolling) is shown below. 16 15 2 • Generate pseudo-random bytes which can be read by the CPU. • Calculate CRC16 of bytes that are written to RNDH. • Seeded by value written to RNDL. 15 The random number generator is turned off when ADCCON1.RCTRL=11. 9 8 7 6 5 4 3 2 + 14 13 12 11 10 + 1 0 in_bit + Figure 39: Basic Structure of the Random Number Generator 13.11.2 Random Number Generator Operation The operation of the random number generator is controlled by the ADCCON1.RCTRL bits. The current value of the 16-bit shift register in the LFSR can be read from the RNDH and RNDL registers. 13.11.2.1 Semi Random Sequence Generation The default operation (ADCCON1.RCTRL=00) is to clock the LSFR once (13x unrolling) thus give a new pseudo-random byte from LSB of the LSFR each time the RNDL register is read. Another way is to update the LFSR is to set ADCCON1.RCTRL=01. This will clock the LFSR once (no unrolling) and the ADCCON1.RCTRL bits will automatically be cleared when the operation has completed. 13.11.2.2 Seeding The LFSR can be seeded by writing to the RNDL register twice. Each time the RNDL register is written, the 8 LSB of the LFSR is copied to the 8 MSB and the 8 LSBs are replaced with the new data byte that was written to RNDL. 13.11.2.3 CRC16 The LFSR can also be used to calculate the CRC value of a sequence of bytes. Writing to the RNDH register will trigger a CRC calculation. The new byte is processed from the MSB end and an 8x unrolling is used, so that a new byte can be written to RNDH every clock cycle. Note that the LFSR must be properly seeded by writing to RNDL, before the CRC calculations start. Usually the seed value should be 0x0000 or 0xFFFF. Using 0xFFFF as seed value will give the CRC used by the radio. For the following byte sequence: 0x03, 0x41, 0x42, 0x43 The CRC will be 0xB4BC when using 0xFFFF as seed value. 13.11.3 Registers The random number generator registers are described in this section. SWRS033E Page 147 of 239 CC1110Fx / CC1111Fx RNDL (0xBC) – Random Number Generator Data Low Byte Bit [7:0] Name RNDL[7:0] Reset 0xFF R/W R/W Description Random value/seed or CRC result, low byte When used for random number generation writing this register twice will seed the random number generator. Writing to this register copies the 8 LSBs of the LFSR to the 8 MSBs and replaces the 8 LSBs with the data value written. The value returned when reading from this register is the 8 LSBs of the LSFR. When used for random number generation, reading this register returns the 8 LSBs of the random number. When used for CRC calculations, reading this register returns the 8 LSBs of the CRC result. RNDH (0xBD) – Random Number Generator Data High Byte Bit [7:0] Name RNDH[7:0] Reset 0xFF R/W R/W Description Random value or CRC result/input data, high byte When written, a CRC16 calculation will be triggered, and the data value written is processed starting with the MSB bit. The value returned when reading from this register is the 8 MSBs of the LSFR. When used for random number generation, reading this register returns the 8 MSBs of the random number. When used for CRC calculations, reading this register returns the 8 MSBs of the CRC result. SWRS033E Page 148 of 239 CC1110Fx / CC1111Fx 13.12 AES Coprocessor The CC1110Fx/CC1111Fx data encryption is performed using a dedicated coprocessor which supports the Advanced Encryption Standard, AES. The coprocessor allows encryption/decryption to be performed with minimal CPU usage. The coprocessor has the following features: • ECB, CBC, CFB, OFB, CTR, and CBC- MAC modes. • Hardware support for CCM mode • 128-bits key and IV/Nonce • DMA transfer trigger capability 13.12.1 AES Operation To encrypt a message, procedure must be followed: the following • ENCCS, Encryption control and status register • ENCDI, Encryption input register • ENCDO, Encryption output register Read/write to the control and status register is done by the CPU, while read/write the output/input registers is intended for use together with direct memory access (DMA). When using DMA, one channel is used for input data and one for output data. The DMA channels must be initialized before a start command is written to the ENCCS. Writing a start command generates a DMA trigger and the transfer is started. After each block is processed, the interrupt flag, S0CON.ENCIF, is asserted, and an interrupt request generated if IEN0.ENCIE is set to 1. The interrupt is used to issue a new start command to the ENCCS. 13.12.5 Modes of Operation ECB and CBC modes are performed as described in section 13.12.1 When using CFB, OFB, and CTR mode, the 128 bits blocks are divided into four 32 bit blocks. 32 bits are loaded into the AES coprocessor and the resulting 32 bits are read out. This continues until all 128 bits have been encrypted. The only time one has to consider this is if data is loaded/read directly using the CPU. When using DMA, this is handled automatically by the DMA triggers generated by the AES coprocessor, thus DMA is preferred. Both encryption and performed similarly. decryption are • Load key • Load initialization vector (IV)/nonce • Download and upload data for encryption/decryption. The AES coprocessor works on blocks of 128 bits. A block of data is loaded into the coprocessor, encryption is performed, and the result must be read out before the next block can be processed. Before each block load, a dedicated start command must be sent to the coprocessor. 13.12.2 Key and IV Before a key or IV/nonce load starts, an appropriate load key or IV/nonce command must be issued to the coprocessor. When loading the IV it is important to also set the correct mode. A key load or IV load operation aborts any processing that could be running. The key, once loaded, stays valid until a key reload takes place. The IV must be downloaded before the beginning of each message (not block). Both key and IV are cleared by a reset of the device and when PM2 or PM3 are entered. 13.12.3 Padding of Input Data AES works on blocks of 128 bits. If the last block contains less than 128 bits, it must be padded with zeros when written to the coprocessor. 13.12.4 Interface to CPU The CPU communicates coprocessor using three SFRs: with the The CBC-MAC mode is a variant of the CBC mode. When performing CBC-MAC, data is downloaded to the coprocessor one 128 bits block at a time, except for the last block. Before the last block is loaded, the mode must be changed to CBC. The last block is then downloaded and the block uploaded will be the MAC value. CBC-MAC decryption is similar to encryption. The message MAC uploaded must be compared with the MAC to be verified. 13.12.6 AES Interrupts The AES interrupt flag, S0CON.ENCIF, is asserted when encryption or decryption of a block is completed. An interrupt request is generated if IEN0.ENCIE is set to 1 SWRS033E Page 149 of 239 CC1110Fx / CC1111Fx 13.12.7 AES DMA Triggers There are two DMA triggers associated with the AES coprocessor. These are ENC_DW, which is active when input data needs to be downloaded to the ENCDI register, and ENC_UP, which is active when output data needs to be uploaded from the ENCDO register. The ENCDI and ENCDO registers should be set as destination and source locations for ENCCS (0xB3) – Encryption Control and Status Bit 7 6:4 MODE[2:0] Name Reset 0 000 R/W R0 R/W Description Not used Encryption/decryption mode 000 001 010 011 100 101 110 111 3 RDY 1 R CBC CFB OFB CTR ECB CBC MAC Reserved Reserved DMA channels used to transfer data to or from the AES coprocessor. 13.12.8 AES Registers The AES coprocessor registers are described below. These registers will be in their reset state when returning to active mode from PM2 and PM3. Encryption/decryption ready status 0 1 Encryption/decryption in progress Encryption/decryption is completed 2:1 CMD[1:0] 0 R/W Command to be performed when a 1 is written to ST. 00 01 10 11 encrypt block decrypt block load key load IV/nonce 0 ST 0 R/W1 H0 Start processing command set by CMD. Must be issued for each command or 128 bits block of data. Cleared by hardware ENCDI (0xB1) – Encryption Input Data Bit 7:0 Name DIN[7:0] Reset 0x00 R/W R/W Description Encryption input data. ENCDO (0xB2) – Encryption Output Data Bit 7:0 Name DOUT[7:0] Reset 0x00 R/W R/W Description Encryption output data. SWRS033E Page 150 of 239 CC1110Fx / CC1111Fx 13.13 Watchdog Timer The watchdog timer (WDT) is intended as a recovery method in situations where the software hangs. The WDT shall reset the system when software fails to clear the WDT within a selected time interval. The watchdog can be used in applications where high reliability is required. If the watchdog function is not needed in an application, it is possible to configure the watchdog timer to be used as an interval timer that can be used to generate interrupts at selected time intervals. The features of the watchdog timer are as follows: • • • • Four selectable timer intervals Watchdog mode Timer mode Interrupt request generation in timer mode • Clock independent from system clock The operation of the WDT module is controlled by the WDCTL register. The watchdog timer consists of a 15-bit counter clocked by the one of the low speed oscillators. Note that the content of the 15-bit counter is not user-accessible. The content of the 15-bit counter is reset to 0x0000 when a PM2 or PM3 is entered. 13.13.1 Watchdog Mode The watchdog timer is disabled after a system reset. To set the WDT in watchdog mode the WDCTL.MODE bit must be set to 0. The watchdog timer counter starts incrementing when the enable bit WDCTL.EN is set to 1. When the timer is enabled in watchdog mode it is not possible to disable the timer. Therefore, writing a 0 to WDCTL.EN has no effect if a 1 was already written to this bit when WDCTL.MODE was 0. The WDT operates with a watchdog timer clock frequency of 32.768 kHz (low speed crystal oscillator) or 32 - 36 kHz (calibrated low power RC oscillator). The timer interval depend on the count value settings (64, 512, 8192, and 32768 respectively) configured in WDCTL.INT. If the counter reaches the selected timer interval value (watchdog timeout), the watchdog timer generates a reset signal for the system. If a watchdog clear sequence is performed before the counter reaches the selected timer interval value, the counter is reset to 0x0000 and continues incrementing its value. The watchdog clear sequence consists of writing 1010 to WDCTL.CLR[3:0] followed by writing 0101 to the same register bits within one half of a watchdog clock period. If this complete sequence is not performed, the watchdog timer generates a reset signal for the system. Note that as long as a correct watchdog clear sequence begins within the selected timer interval, the counter is reset when the complete sequence has been received. When the watchdog timer has been enabled in watchdog mode, it is not possible to change the mode by writing to the WDCTL.MODE bit. The timer interval value can be changed by writing to the WDCTL.INT[1:0] bits. Note that a change in the timer interval value should be followed by a clearing of the watchdog timer to avoid an unwanted watchdog reset. In watchdog mode, the WDT does not produce an interrupt request. 13.13.2 Timer Mode To set the WDT in normal timer mode, the WDCTL.MODE bit is set to 1. When register bit WDCTL.EN is set to 1, the timer is started and the counter starts incrementing. When the counter reaches the selected interval value, the IRCON2.WDTIF flag is asserted and an interrupt request is generated if watchdog timer interrupt is enabled (IEN2.WDTIE=1). In timer mode, it is possible to clear the timer contents by writing a 1 to WDCTL.CLR[0]. When the timer is cleared the contents of the counter is set to 0x0000. The timer is stopped by setting WDCTL.EN=0 and restarted from 0x000 by setting WDCTL.EN=1. The timer interval is set by the WDCTL.INT[1:0] bits. In timer mode, a reset will not be produced when the timer interval value is reached. 13.13.3 Watchdog Mode and Power Modes In active mode and PM0 the WDT runs and resets the chip upon timeout. To avoid reset, the watchdog timer must be cleared before the counter expires. SWRS033E Page 151 of 239 CC1110Fx / CC1111Fx Power Mode PM1 Comments The WDT runs but does not reset the chip upon timeout. If active mode is entered just as the timer expires, the chip will be reset immediately, hence the WDT needs to be cleared regularly (before timeout) also when in PM1. The WDT is disabled and reset, and the configuration is retained. The counter will start from 0x0000 when active mode is entered from PM2 or PM3 PM2 and PM3 Table 54: Watchdog Mode and Power Modes 13.13.4 Watchdog Timer Register WDCTL (0xC9) – Watchdog Timer Control Bit 7:4 Name CLR[3:0] Reset 0000 R/W R/W Description Clear timer. When 1010 followed by 0101 is written to these bits, the counter is reset to 0x0000. Note that the watchdog will only be cleared when 0101 is written within 0.5 watchdog clock period after 1010 was written. Writing to these bits when EN is 0 has no effect. Enable timer. When a 1 is written to this bit the timer is enabled and starts incrementing. Writing a 0 to this bit in timer mode stops the timer. Writing a 0 to this bit in watchdog mode has no effect. 0 1 2 MODE 0 R/W Timer disabled Timer enabled 3 EN 0 R/W Mode select. 0 1 Watchdog mode Timer mode 1:0 INT[1:0] 00 R/W Timer interval select. These bits select the timer interval defined as a given number of low speed oscillator periods. Timer interval # of periods 32.768 kHz crystal oscillator 32 kHz RCOSC (calibrated, CC1111Fx) 1.024 s 0.256 s 16 ms 2 ms 34.667 kHz RCOSC (calibrated, CC1110Fx running @ 26 MHz) 0.945 s 0.236 s 14.769 ms 1.846 ms 00 01 10 11 32768 8192 512 64 1s 0.25 s 15.625 ms 1.953 ms SWRS033E Page 152 of 239 CC1110Fx / CC1111Fx 13.14 USART USART0 and USART1 are serial communications interfaces that can be operated separately in either asynchronous UART mode or in synchronous SPI mode. The two USARTs are identical in functionality but are assigned to separate I/O pins. Refer to section 13.4 on page 91 for I/O configuration. 13.14.1 UART Mode For asynchronous serial interfaces, the UART mode is provided. In UART mode the interface uses a two-wire or four-wire interface consisting of the pins RXD and TXD, and optionally RTS and CTS. The UART mode includes the following features: • • • • • 8 or 9 data bits Odd, even, or no parity Configurable start and stop bit level Configurable LSB or MSB first transfer Independent receive and transmit interrupts • Independent receive and transmit DMA triggers • Parity and framing error status transmit data, and an interrupt request is generated if IEN2.UTXxIE=1. This happens immediately after the transmission has been started, hence a new data byte value can be loaded into the data buffer while the byte is being transmitted. 13.14.1.2 UART Receive Data reception on the UART is initiated when a 1 is written to the UxCSR.RE bit. The UART will then search for a valid start bit on the RXDx input pin and set the UxCSR.ACTIVE bit high. When a valid start bit has been detected the received byte is shifted into the receive register. The UxCSR.RX_BYTE bit and the CPU interrupt flag, TCON.URXxIF, is set to 1 when the operation has completed and an interrupt request is generated if IEN0.URXxIE=1. At the same time UxCSR.ACTIVE will go low. The received data byte is available through the UxDBUF register. When UxDBUF is read, UxCSR.RX_BYTE is cleared by hardware. 13.14.1.3 UART Hardware Flow Control Hardware flow control is enabled when the UxUCR.FLOW bit is set to 1. The RTS output will then be driven low when the receive register is empty and reception is enabled. Transmission of a byte will not occur before the CTS input go low. 13.14.1.4 UART Character Format If the BIT9 and PARITY bits in register UxUCR are set high, parity generation and detection is enabled. The parity is computed and transmitted as the ninth bit, and during reception, the parity is computed and compared to the received ninth bit. If there is a parity error, the UxCSR.ERR bit is set high. This bit is cleared when UxCSR is read. The number of stop bits to be transmitted is set to one or two bits determined by the register bit UxUCR.SPB. The receiver will always check for one stop bit. If the first stop bit received during reception is not at the expected stop bit level, a framing error is signaled by setting register bit UxCSR.FE high. UxCSR.FE is cleared when UxCSR is read. The receiver will check both stop bits when UxUCR.SPB=1. Note that the USARTx RX complete CPU interrupt flag, TCON.URXxIF, and the UxCSR.RX_BYTE bit will be asserted when the first stop bit is checked OK. If the second stop bit is not OK, The UART mode provides full duplex asynchronous transfers and the synchronization of bits in the receiver does not interfere with the transmit function. A UART byte transfer consists of a start bit, eight data bits, an optional ninth data or parity bit, and one or two stop bits. Note that the data transferred is referred to as a byte, although the data can actually consist of eight or nine bits. The UART operation is controlled by the USART x Control and Status registers, UxCSR, and the USART x UART Control register, UxUCR, where x is the USART number, 0 or 1. The UART mode is UxCSR.MODE is set to 1. 13.14.1.1 UART Transmit A UART transmission is initiated when the USART Receive/Transmit Data Buffer, UxDBUF register is written. The byte is transmitted on the TXDx output pin. The UxDBUF register is double-buffered. The UxCSR.ACTIVE bit goes high when the byte transmission starts and low when it ends. When the transmission ends, the UxCSR.TX_BYTE bit is set to 1. The USARTx TX complete CPU interrupt flag (IRCON2.UTXxIF) is asserted when the UxDBUF register is ready to accept new selected when SWRS033E Page 153 of 239 CC1110Fx / CC1111Fx the framing error bit, UxCSR.FE, will be asserted. This means that this bit is updated 1 bit duration later than the 2 other above mentioned bits. The UxCSR.ACTIVE bit will be de-asserted after the second stop bit (if UxUCR.SPB=1). 13.14.2 SPI Mode This section describes the SPI mode of operation for synchronous communication. In SPI mode, the USART communicates with an external system through a 3-wire or 4-wire interface. The interface consists of the pins MOSI, MISO, SCK and SSN. Refer to section 13.4 on page 91 for I/O configuration. The SPI mode includes the following features: • • • • 3-wire (master) and 4-wire SPI interface Master and slave modes Configurable SCK polarity and phase Configurable LSB or MSB first transfer therefore not safe to use. Instead, the assertion of the UxCSR.TX_BYTE bit should be used as an indication on when new data can be written to UxDBUF. For DMA transfers this is handled automatically, but with the limitation that the UxGDR.CPHA bit must be set to zero. For systems requiring setting UxGDR.CPHA=1, the DMA can not be used. Also note that the USARTx TX complete interrupt occurs approximately 1 byte period prior to the USARTx RX complete interrupt. In SPI master mode, only the MOSI, MISO, and SCK should be configured as peripherals (see section 13.4.6.1 and 13.4.6.2). If the external slave requires a slave select signal (SSN) this can be implemented by using a general-purpose I/O pin and control from SW. 13.14.2.2 SPI Slave Operation An SPI byte transfer in slave mode is controlled by the external system. The data on the MOSI input is shifted into the receive register controlled by the serial clock SCK, which is an input in slave mode. At the same time the byte in the transmit register is shifted out onto the MISO output. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. When the transfer ends, the UxCSR.RX_BYTE bit is set to 1 At the end of the transfer, the USARTx RX complete CPU interrupt flag, TCON.URXxIF, is asserted and the received data byte is available in UxDBUF. An interrupt request is generated if IEN0.URXxIE=1. The USARTx TX complete CPU interrupt flag, IRCON2.UTXxIF, is asserted at the start of the operation and an interrupt request is generated if IEN2.UTXxIE=1. The expected polarity and clock phase of SCK is selected by UxGCR.CPOL and UxGCR.CPHA as shown in Figure 40. The expected order of the byte transfer is selected by the UxGCR.ORDER bit. 13.14.2.3 Slave Select pin (SSN) When the USART is operating in SPI slave mode, a 4-wire interface is used with the Slave Select (SSN) pin as an input to the SPI (edge controlled). The SPI slave becomes active after a falling edge on SSN and will receive data on the MOSI input and send data on the MISO output. After a rising edge on SSN, the SPI slave is inactive and will not receive data. Note that the MISO output is not tri-stated The SPI mode is selected when UxCSR.MODE is set to 0. In SPI mode, the USART can be configured to operate either as an SPI master or as an SPI slave by setting UxCSR.SLAVE to 0 or 1, recpectively. 13.14.2.1 SPI Master Operation An SPI byte transfer in master mode is initiated when the UxDBUF register is written. The USART generates the SCK signal using the baud rate generator (see section 13.14.3) and shifts the provided byte from the transmit register onto the MOSI output. At the same time the receive register shifts in the received byte from the MISO input pin. The polarity and clock phase of the serial clock SCK is selected by UxGCR.CPOL and UxGCR.CPHA. The order of the byte transfer is selected by the UxGCR.ORDER bit. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. When the transfer ends, the UxCSR.TX_BYTE bit is set to 1. At the end of the transfer, the USARTx RX complete CPU interrupt flag, TCON.URXxIF, is asserted and the received data byte is available in UxDBUF. An interrupt request is generated if IEN0.URXxIE=1 Since UxDBUF is double-buffered, the assertion of the USARTx TX complete CPU interrupt flag (IRCON2.UTXxIF) happens just after a transmission has been initiated, and is SWRS033E Page 154 of 239 CC1110Fx / CC1111Fx when the SPI slave is inactive. Also note that the rising edge on SSN must be aligned to the end of the byte sent / received. If this is not the case, the next received byte will be corrupted. If there is a rising edge on SSN in the middle of a byte, this should be followed by a USART flush to avoid corruption of the following byte. In SPI master mode, the SSN pin is not used. When the USART operates as an SPI master and a slave select signal is needed by an external SPI slave device, a general purpose I/O pin should be used to implement the slave select signal function in software. Figure 40: SPI Dataflow 13.14.3 Baud Rate Generation An internal baud rate generator set up the UART baud rate when operating in UART mode and the SPI master clock frequency when operating in SPI mode. The UxBAUD.BAUD_M[7:0] and UxGCR.BAUD_E[4:0] registers define the baud rate used for UART transfers and the rate of the serial clock (SCK) for SPI transfers. The baud rate is given by the following equation: difference in actual baud rate to standard baud rate value as a percentage error. The maximum baud rate for UART mode is F/16 (UxGCR.BAUD_E[4:0]=16 and UxBAUD.BAUD_M[7:0]=0). The maximum baud rate for SPI master mode and thus SCK frequency is F/8 (UxGCR.BAUD_E[4:0]=17 and UxBAUD.BAUD_M[7:0]=0). If SPI master mode does not need to receive data, the maximum SPI rate is F/2 (UxGCR.BAUD_E[4:0]=19 and UxBAUD.BAUD_M[7:0]=0). Setting higher baud rates than this will give erroneous results. For SPI slave mode the maximum baud rate is always F/8. Note that the baud rate must be configured before any other UART or SPI operations take place (the baud rate should never be changed when UxCSR.ACTIVE is asserted). Baudrate = (256 + BAUD _ M ) ∗ 2 BAUD _ E ∗F 2 28 where F is the system clock frequency set by the selected system clock source. The register values required for standard baud rates are shown in Table 55 (F = 26 MHz) and Table 56 (24 MHz). The tables also give the SWRS033E Page 155 of 239 CC1110Fx / CC1111Fx Baud rate [bps] 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 230400 UxBAUD.BAUD_M 131 131 131 34 131 34 131 34 131 34 34 UxGCR.BAUD_E 6 7 8 9 9 10 10 11 11 12 13 Error (%) 0.04 0.04 0.04 0.13 0.04 0.13 0.04 0.13 0.04 0.13 0.13 Table 55: Commonly used Baud Rate Settings for 26 MHz System Clock Baud rate [bps] 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 230400 UxBAUD.BAUD_M 163 163 163 59 163 59 163 59 163 59 59 UxGCR.BAUD_E 6 7 8 9 9 10 10 11 11 12 13 Error (%) 0.08 0.08 0.09 0.13 0.10 0.14 0.10 0.14 0.10 0.14 0.14 Table 56: Commonly used Baud Rate Settings for 24 MHz System Clock 13.14.4 USART Flushing The current operation can be aborted (operation stopped and all data buffers cleared) by setting UxUCR.FLUSH=1.Asserting the FLUSH bit should either be aligned with USART interrupts or a wait time of one bit duration (at current baud rate) should be added after setting the bit to 1 before accessing the USART registers. 13.14.5 USART Interrupts Each USART has two interrupts. These are the USART x RX complete interrupt (TCON.URXxIF) and the USART x TX complete interrupt (IRCON2.UTXxIF). The interrupts are enabled by setting IEN0.URXxIE=1 and IEN2.UTXxIE=1, respectively. Please see the previous sections on how the interrupt flags are asserted in the different modes of operation (UART RX, UART TX, SPI master, and SPI Slave). The interrupt enables summarized below. Interrupt enable bits: • • • • • • • • USART0 RX : IEN0.URX0IE USART1 RX : IEN0.URX1IE USART0 TX : IEN2.UTX0IE USART1 TX : IEN2.UTX1IE USART0 RX : TCON.URX0IF USART1 RX : TCON.URX1IF USART0 TX : IRCON2.UTX0IF USART1 TX : IRCON2.UTX1IF and flags are Interrupt flags: SWRS033E Page 156 of 239 CC1110Fx / CC1111Fx 13.14.6 USART DMA Triggers There are two DMA triggers associated with each USART (URX0, UTX0, URX1, and UTX1). The DMA triggers are activated by RX complete and TX complete events i.e. the same events that might generate USART interrupt requests. A DMA channel can be configured using a USART Receive/transmit buffer, UxDBUF, as source or destination address. Note: For systems requiring setting UxGDR.CPHA=1, the DMA can not be used. U0CSR (0x86) – USART 0 Control and Status Bit 7 Name MODE Reset 0 R/W R/W Description USART 0 mode select 0 1 6 RE 0 R/W SPI mode UART mode Refer to Table 51 on page 108 for an overview of the DMA triggers. 13.14.7 USART Registers The registers for the USART are described in this section. For each USART there are five registers consisting of the following (x refers to USART number i.e. 0 or 1): • • • • UxCSR USART x Control and Status UxUCR USART x UART Control UxGCR USART x Generic Control UxDBUF USART x Receive/Transmit Data Buffer • UxBAUD USART x Baud Rate Control UART 0 receiver enable 0 1 Receiver disabled Receiver enabled 5 SLAVE 0 R/W SPI 0 master or slave mode select 0 1 SPI master SPI slave 4 FE 0 R/W0 UART 0 framing error status 0 1 No framing error detected Byte received with incorrect stop bit level Note: TCON.URX0IF and U0CSR.RX_BYTE bit will be asserted when the first stop bit is checked OK, meaning that if two stop bits are sent and the second stop bit is not OK, this bit is asserted 1 bit duration later than the 2 other above mentioned bits. 3 ERR 0 R/W0 UART 0 parity error status 0 1 No parity error detected Byte received with parity error 2 RX_BYTE 0 R/W0 Receive byte status 0 1 No byte received Received byte ready 1 TX_BYTE 0 R/W0 Transmit byte status 0 1 Byte not transmitted Last byte written to Data Buffer register transmitted 0 ACTIVE 0 R USART 0 transmit/receive active status 0 1 USART 0 idle USART 0 busy in transmit or receive mode SWRS033E Page 157 of 239 CC1110Fx / CC1111Fx U0UCR (0xC4) – USART 0 UART Control Bit 7 Name FLUSH Reset 0 R/W R0/W1 Description Flush unit. When set to 1, this event will immediately stop the current operation and return the unit to idle state. This bit will be 0 when returning from PM2 and PM3 6 FLOW 0 R/W UART 0 hardware flow control enable. Selects use of hardware flow control with RTS and CTS pins 0 1 5 D9 0 R/W Flow control disabled Flow control enabled UART 0 data bit 9 contents. This value is used when 9 bit transfer is enabled. When parity is disabled the value written to D9 is transmitted as the th 9 bit when BIT9=1. If parity is enabled then this bit sets the parity level as follows. 0 1 Even parity Odd parity 4 BIT9 0 R/W UART 0 9-bit data enable 0 1 8 bits transfer 9 bits transfer (content of the 9 bit is given by D9 and PARITY.) th 3 PARITY 0 R/W UART 0 parity enable 0 1 Parity disabled Parity enabled 2 SPB 0 R/W UART 0 number of stop bits 0 1 1 stop bit 2 stop bits 1 STOP 1 R/W UART 0 stop bit level 0 1 Low stop bit High stop bit 0 START 0 R/W UART 0 start bit level. The polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 1 Low start bit High start bit U0GCR (0xC5) – USART 0 Generic Control Bit 7 Name CPOL Reset 0 R/W R/W Description SPI 0 clock polarity 0 1 6 CPHA 0 R/W Negative clock polarity (SCK low when idle) Positive clock polarity (SCK high when idle) SPI 0 clock phase 0 1 Data centered on first edge of SCK period Data centered on second edge of SCK period 5 ORDER 0 R/W Bit order for transfers 0 1 LSB first MSB first 4:0 BAUD_E[4:0] 0x00 R/W Baud rate exponent value. BAUD_E along with BAUD_M decides the UART 0 baud rate and the SPI 0 clock (SCK) frequency SWRS033E Page 158 of 239 CC1110Fx / CC1111Fx U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer Bit 7:0 Name DATA[7:0] Reset 0x00 R/W R/W Description USART 0 receive and transmit data buffer. Writing data to U0DBUF places the data into the internal transmit buffer. Reading U0DBUF returns the contents of the receive buffer. U0BAUD (0xC2) – USART 0 Baud Rate Control Bit 7:0 Name BAUD_M[7:0] Reset 0x00 R/W R/W Description Baud rate mantissa value. BAUD_M along with BAUD_E decides the UART 0 baud rate and the SPI 0 clock (SCK) frequency U1CSR (0xF8) – USART 1 Control and Status Bit 7 Name MODE Reset 0 R/W R/W Description USART 1 mode select 0 1 6 RE 0 R/W SPI mode UART mode UART 1 receiver enable 0 1 Receiver disabled Receiver enabled 5 SLAVE 0 R/W SPI 1 master or slave mode select 0 1 SPI master SPI slave 4 FE 0 R/W0 UART 1 framing error status 0 1 No framing error detected Byte received with incorrect stop bit level Note that TCON.URX1IF and U1CSR.RX_BYTE bit will be asserted when the first stop bit is checked OK, meaning that if two stop bits are sent and the second stop bit is not OK, this bit is asserted 1 bit duration later than the 2 other above mentioned bits. 3 ERR 0 R/W0 UART 1 parity error status 0 1 No parity error detected Byte received with parity error 2 RX_BYTE 0 R/W0 Receive byte status 0 1 No byte received Received byte ready 1 TX_BYTE 0 R/W0 Transmit byte status 0 1 Byte not transmitted Last byte written to Data Buffer register transmitted 0 ACTIVE 0 R USART 1 transmit/receive active status 0 1 USART 1 idle USART 1 busy in transmit or receive mode SWRS033E Page 159 of 239 CC1110Fx / CC1111Fx U1UCR (0xFB) – USART 1 UART Control Bit 7 Name FLUSH Reset 0 R/W R0/W1 Description Flush unit. When set to 1, this event will immediately stop the current operation and return the unit to idle state. This bit will be 0 when returning from PM2 and PM3 6 FLOW 0 R/W UART 1 hardware flow control enable. Selects use of hardware flow control with RTS and CTS pins 0 1 5 D9 0 R/W Flow control disabled Flow control enabled UART 1 data bit 9 contents. This value is used when 9 bit transfer is enabled. When parity is disabled the value written to D9 is transmitted as the th 9 bit when BIT9=1. If parity is enabled then this bit sets the parity level as follows. 0 1 Even parity Odd parity 4 BIT9 0 R/W UART 1 9-bit data enable 0 1 8 bits transfer 9 bits transfer (content of the 9 bit is given by D9 and PARITY.) th 3 PARITY 0 R/W UART 1 parity enable 0 1 Parity disabled Parity enabled 2 SPB 0 R/W UART 1 number of stop bits 0 1 1 stop bit 2 stop bits 1 STOP 1 R/W UART 1 stop bit level 0 1 Low stop bit High stop bit 0 START 0 R/W UART 1 start bit level. The polarity of the idle line is assumed to be the opposite of the selected start bit level. 0 1 Low start bit High start bit SWRS033E Page 160 of 239 CC1110Fx / CC1111Fx U1GCR (0xFC) – USART 1 Generic Control Bit 7 Name CPOL Reset 0 R/W R/W Description SPI 1 clock polarity 0 1 6 CPHA 0 R/W Negative clock polarity (SCK low when idle) Positive clock polarity (SCK high when idle) SPI 1 clock phase 0 1 Data centered on first edge of SCK period Data centered on second edge of SCK period 5 ORDER 0 R/W Bit order for transfers 0 1 LSB first MSB first 4:0 BAUD_E[4:0] 0x00 R/W Baud rate exponent value. BAUD_E along with BAUD_M decides the UART 1 baud rate and the SPI 1 clock (SCK) frequency U1DBUF (0xF9) – USART 1 Receive/Transmit Data Buffer Bit 7:0 Name DATA[7:0] Reset 0x00 R/W R/W Description USART 1 receive and transmit data buffer. Writing data to U1DBUF places the data into the internal transmit buffer. Reading U1DBUF returns the contents of the receive buffer. U1BAUD (0xFA) – USART 1 Baud Rate Control Bit 7:0 Name BAUD_M[7:0] Reset 0x00 R/W R/W Description Baud rate mantissa value. BAUD_M along with BAUD_E decides the UART 1 baud rate and the SPI 1 clock (SCK) frequency SWRS033E Page 161 of 239 CC1110Fx / CC1111Fx 13.15 I2S The CC1110Fx/CC1111Fx provides an industry standard I2S interface. The I2S interface can be used to transfer digital audio samples between the CC1110Fx/CC1111Fx and an external audio device. The I2S interface can be configured to operate as master or slave and may use mono as well as stereo samples. When mono mode is enabled, the same audio sample will be used for both channels. Both full and half duplex is supported and automatic µ-Law compression and expansion can be used. The I2S interface consists of 4 signals: • • • • Continuous Serial Clock (SCK) Word Select (WS) Serial Data In (RX) Serial Data Out (TX) Please see section 13.4.6.6 for details on I/O pin mapping for the I2S interface. When the module is in master mode, it drives the SCK and WS lines. When the I2S interface is in slave mode, these lines are driven by an external master. The data on the serial data lines is transferred one bit per SCK cycle, most significant bit first. The WS signal selects the channel of the current word transfer (left = 0, right = 1). It also determines the length of each word. There is a transition on the WS line one bit time before the first word is transferred and before the last bit of each word. Figure 41 shows the I2S signaling. Only a single serial data signal is shown in this figure. The SD signal could be the RX or TX signal depending on the direction of the data. SCK WS SD SAMPLE n-1, RIGHT CHANNEL MSB SAMPLE n, LEFT CHANNEL LSB MSB SAMPLE n+1, RIGHT CHANNEL LSB MSB Figure 41: I2S Digital Audio Signaling 13.15.1 Enabling I2S The I2SCFG0.ENAB bit must be set to 1 to enable the I2S transmitter/receiver. However, when I2SCFG0.ENAB is 0, the I2S can still be used as a stand-alone µ-Law compression/expansion engine. Refer to section 13.15.12 on page 165 for more details about this. 13.15.2 I2S Interrupts The I2S has two interrupts: • I2S RX complete interrupt (I2SRX) • I2S TX complete interrupt (I2STX) The I2S interrupt enable bits are found in the I2SCFG0 register. The interrupt flags are located in the I2SSTAT register. The interrupt enables and flags are summarized below. Interrupt enable bits: • I2S RX: I2SCFG0.RXIEN • I2S TX: I2SCFG0.TXIEN Interrupt flags: • I2S RX: I2SSTAT.RXIRQ • I2S TX: I2SSTAT.TXIRQ The TX interrupt flag I2SSTAT.TXIRQ is asserted together with IRCON2.I2STXIF when the internal TX buffer is empty and the I2S fetches the new data previously written to the I2SDATH:I2SDATL registers. The TX interrupt flag, I2SSTAT.TXIRQ, is cleared when I2SDATH register is written. An interrupt request is only generated when I2SCFG0.TXIEN and IEN2.I2STXIE are both set to 1. The RX interrupt flag I2SSTAT.RXIRQ is asserted together with TCON.I2SRXIF when the internal RX buffer is full and the contents of the RX buffer is copied to the pair of internal data registers that can be read from the I2SDATH:I2SDATL registers. The RX interrupt flag, I2SSTAT.RXIRQ, is cleared when the I2SDATH register is read. An interrupt request is only generated when I2SCFG0.RXIEN and IEN0.I2SRXIE are both set to 1. SWRS033E Page 162 of 239 CC1110Fx / CC1111Fx Notice that interrupts will also be generated if the corresponding RXIRQ or TXIRQ flags are set from software, given that the interrupts are enabled. The I2S shares interrupt vector with USART 1, and the ISR must take this into account if both modules are used. Refer to section 11.5 on page 61 for more details about interrupts. 13.15.3 I S DMA Triggers There are two DMA triggers associated with the I2S interface, I2SRX and I2STX. The DMA triggers are activated by RX complete and TX complete events, i.e. the same events that can generated the I2S interrupt requests. The DMA triggers are not masked by the interrupt enable bits, I2SCFG0.RXIEN and I2SCFG0.TXIEN, hence a DMA channel can be configured to use the I2S receive/transmit data registers, I2SDATH:I2SDATL, as source or destination address and let RX and TX complete trigger the DMA. Notice that the DMA triggers I2SRX and ADC_CH6 share the same DMA trigger number (# 27) in the same way as I2STX and ADC_CH7 share DMA trigger number 28. This means that I2SRX can not be used together with ADC_CH6 and I2STX can not be used together with ADC_CH7. On the CC1111Fx ADC channels 6 and 7 cannot be used since P0_6 and P0_7 I/O pins are not available. Refer to Table 51 on page 108 for an overview of the DMA triggers. 13.15.4 Underflow/Overflow If the I S attempts to read from the internal TX buffer when it is empty, an underflow condition occurs. The I2S will then continue to read from the data in the TX buffer, and I2SSTAT.TXUNF will be asserted. If the I2S attempts to write to the internal RX buffer while it is full, an overflow condition occurs. The contents of the RX buffer will be overwritten and the I2SSTAT.RXOVF flag will be asserted. Thus, when debugging an application, software may check for underflow/overflow when an interrupt is generated or when the application completes. The TXUNF / RXOVF flags should be cleared in software. 13.15.5 Writing a Word (TX) When each sample fits into a single byte or µLaw compressed samples (always 8 bits) are written, i.e. µ-Law expansion is enabled 2 2 (I2SCFG0.ULAWE=1), only register needs to be written. the I2SDATH When each sample is more than 8 bits the low byte must be written to the I2SDATL register before the high byte is written to the I2SDATH register, hence writing the I2SDATH register indicates the completion of the write operation. When the I2S is configured to send stereo, i.e. I2SCFG0.TXMONO is 0, the I2SSTAT.TXLR flag can be used to determine whether the leftor right-channel sample is to be written to the data registers. 13.15.6 Reading a Word (RX) If each sample fits into a single byte or if µ-Law compression is enabled (I2SCFG0.ULAWC=1), only the I2SDATH register needs to be read. When each sample is more than 8 bits the low byte must be read from the I2SDATL register before the high byte is being read from the I2SDATH register, hence reading from the I2SDATH register indicates the completion of the read operation. When the I2S is configured to receive stereo, i.e. I2SCFG0.RXMONO is 0, the I2SSTAT.RXLR flag can be used to determine whether the sample currently in the data registers is a left- or right-channel sample. 13.15.7 Full vs. Half Duplex The I2S interface supports full duplex and half duplex operation. In full duplex both the RX and TX lines will be used. Both the I2SCFG0.TXIEN and I2SCFG0.RXIEN interrupt enable bits must be set to 1 if interrupts are used and both DMA triggers I2STX and I2SRX must be used. When half duplex is used only one of the RX and TX lines are typically connected. Only the appropriate interrupt flag should be set and only one of the DMA triggers should be used. 13.15.8 Master Mode The I2S is configured as a master device by setting I2SCFG0.MASTER to 1. When the module is in master mode, it drives the SCK and WS lines. SWRS033E Page 163 of 239 CC1110Fx / CC1111Fx 13.15.8.1 Clock Generation When the I S is configured as master, the frequency of the SCK clock signal must be set to match the sample rate. The clock frequency must be set before master mode is enabled. SCK is generated by dividing the system clock using a fractional clock divider. The amount of division is given by the 15 bit numerator, NUM , and 9-bit denominator, DENOM, as shown in the following formula: Fsck = Fclk NUM 2( ) DENOM 2 Please note that to stay within the timing requirements of the I2S specification [7], a minimum value of 3.35 should be used for the (NUM / DENOM) fraction. The fractional divider is made such that most normal sample rates should be supported for most normal word sizes with a 24 MHz system clock frequency (CC1111Fx). Examples of supported configurations for a 24 MHz system clock are given in Table 57. Table 58 shows the configuration values for a 26 MHz system clock frequency. Notice that the generated I2S frequency is not exact for the 44.1 kHz, 16 bits word size configuration at 26 MHz. The numbers are calculated using the following formulas, where Fs is the sample rate and W is the word size: where NUM > 3.35 DENOM Fclk is the system clock frequency and Fsck is the I2S SCK sample clock frequency. The value of the numerator is set in the -sters and the denominator value is set in I2SCLKF2.DENOM[8]:I2SCLKF0.DENOM[7:0]. Fsck (kHz) 8 8 44.1 48 Word Size (W) 8 16 16 16 CLKDIV 93.75 46.875 8.503401 7.8125 I2SCLKF2 0x01 0x01 0x04 0x00 Fs = CLKDIV = Fsck 2 *W I2SCLKF2.NUM[14:8]:I2SCLKF1.NUM[7:0]regi Fclk NUM = DENOM 4 * W * Fs I2SCLKF1 0x77 0x77 0xE2 0x7D I2SCLKF0 0x04 0x08 0x93 0x10 Exact Yes Yes Yes Yes Table 57: Example I2S Clock Configurations (CC1111Fx, 24 MHz) Fsck (kHz) 8 8 44.1 48 Word Size (W) 8 16 16 16 2 CLKDIV 101.5625 50.78125 9.21201 8.46354 I2SCLKF2 0x06 0x06 0x8A 0x06 I2SCLKF1 0x59 0x59 0x2F 0x59 I2SCLKF0 0x10 0x20 0x1B 0xC0 Exact Yes Yes No Yes Table 58: Example I S Clock Configurations (CC1110Fx, 26 MHz) 13.15.8.2 Word Size The word size must be set before master mode is enabled. The word size is the number of bits used for each sample and can be set to a value between 1 and 33. To set the word size, write word size – 1 to the I2SCFG1.WORDS[4:0] bits. Setting the word size to a value of 17 or more causes the I2S to pad each word with 0’s in the least significant bits since the data registers provide maximum 16 bits. This feature allows samples to be sent to an I2S device that takes a higher resolution than 16 bits. If the size of the received samples exceeds 16 bits, only the 16 most significant bits will be put in the data registers and the remaining low order bits will be discarded. 13.15.9 Slave Mode The I2S is configured as a slave device by setting I2SCFG0.MASTER to 0. When in slave mode the SCK and WS signals are generated by an external I2S master and are inputs to the I2S interface. 13.15.9.1 Word Size When the I2S operates in slave mode, the word size is determined by the master that generates the WS signal. SWRS033E Page 164 of 239 CC1110Fx / CC1111Fx The I2S will provide bits from the internal 16-bit buffer until the buffer is empty. If the buffer becomes empty and the master still requests more bits, the I2S will send 0’s (low order bits). If more than 16 bits are being received, the low order bits are discarded. 13.15.10 2 13.15.12 2 µ-Law Compression and Expansion Mono The I S interface can be configured to perform µ-Law compression and expansion. µ-Law compression is enabled by setting the I2SCFG0.ULAWC bit to 1 and µ-Law expansion is enabled by setting the I2SCFG0.ULAWE bit to 1. When the I2S interface is enabled, i.e. the I2SCFG0.ENAB bit is 1, and µ-Law expansion is enabled, every byte of µ-Law compressed data written to the I2SDATH register is expanded to a 16-bit sample before being transmitted. When the I2S interface is enabled and µ-Law compression is enabled each sample received is compressed to an 8-bit µLaw sample and put in the I2SDATH register. When the I2S interface is disabled, i.e. the I2SCFG0.ENAB bit is 0, it can still be used to perform µ-Law compression/expansion for other resources in the system. To perform an expansion, I2SCFG0.ULAWE must be 1 and I2SCFG0.ULAWC must be 0 before writing a byte of compressed data to the I2SDATH register. The expansion takes one clock cycle to perform, and then the result can be read from the I2SDATH:I2SDATL registers. To perform a compression I2SCFG0.ULAWE must be 01 and I2SCFG0.ULAWC must be 1. To start the compression, an un-compressed 16-bit sample should be written to the I2SDATH:I2SDATL registers. The compression takes one clock cycle to perform, and then the result can be read from the I2SDATH register. Only one of the flags I2SCFG0.ULAWC and I2SCFG0.ULAWE should be set to 1 when the I2SCFG0.ENAB bit is 0. 13.15.13 I2S Registers The I S also supports mono audio samples. To receive mono samples, I2SCFG0.RXMONO should be set to 1. Words from the right channel will then not be read into the data registers. This feature is included because some mono devices repeat their audio data in both channels and the left channel is the default mono channel. To send mono samples, I2SCFG0.TXMONO should be set to 1. Each word will then be repeated in both channels before a new word is fetched from the data registers. This is to enable sending a mono audio signal to a stereo audio sink device. 13.15.11 2 Word Counter The I S contains a 10-bit word counter, which is counting transitions on the WS line. The counter can be cleared by triggers or by writing to the I2SWCNT register. When a trigger occurs, or a value is written to I2SWCNT, the current value of the word counter is copied into the I2SSTAT.WCNT[9:8]:I2SWCNT.WCNT[7:0]regi sters and the word counter is cleared. Three triggers can be used to copy/clear the word counter. • USB SOF: USB Start of Frame. Occurs every ms (CC1111Fx only) • T1_CH0: Timer 1, compare, channel 0 • IOC_1: IO pin input transition (P1_3) Which trigger to use is configured through the TRIGNUM field in the I2SCFG1 register. When the I2S is configured not to use any trigger (I2SCFG1.TRIGNUM=0), the word counter can only be copied/cleared from software. The word counter will saturate if it reaches its maximum value. Software should configure the trigger-interval and sample-rate to ensure this never happens. This section describes all the registers used for I2S control and status. The I2S registers reside in XDATA memory space in the region 0xDF400xDF48. Table 33 on page 52 gives an overview of register addresses while the tables in this section describe each register. Notice that the reset values for the registers reflect a configuration with 16-bit stereo samples and 44.1 kHz sample rate. The I2S is not enabled at reset. CC1111Fx: The word counter is typically used to calculate the average sample rate over a long period of time (e.g. 1 second) needed by adaptive isochronous USB endpoints. The USB SOF event must then be used as trigger. SWRS033E Page 165 of 239 CC1110Fx / CC1111Fx 0xDF40: I2SCFG0 – I2S Configuration Register 0 Bit 7 Field Name TXIEN Reset 0 R/W R/W Description Transmit interrupt enable 0 1 6 RXIEN 0 R/W Interrupt disabled Interrupt enabled Receive interrupt enable 0 1 Interrupt disabled Interrupt enabled 5 ULAWE 0 R/W µ-Law expansion enable 0 1 Expansion disabled Expansion enabled ENAB=0 ENAB=1 Enable expansion of data to transmit Expand data written to I2SDATH 4 ULAWC 0 R/W µ-Law compression enable 0 1 Compression disabled Compression enabled ENAB=0 ENAB=1 Enable compression of data received Compress data written to I2SDATH:I2SDATL 3 TXMONO 0 R/W TX mono enable 0 1 Stereo mode Each sample of audio data will be repeated in both channels before a new sample is fetched. This is to enable sending a mono signal to a stereo audio sink device. 2 RXMONO 0 R/W RX mono enable 0 1 Stereo mode Data from the right channel will be discarded, i.e. not be read into the data registers. This feature is included because some mono devices repeat their audio data in both channels and left is the default mono channel. 1 MASTER 0 R/W Master mode enable 0 1 Slave (CLK and WS are read from the pads) Master (generate the CLK and WS) 0 ENAB 0 R/W I S interface enable 0 1 Disable (I S can be used as a µ-Law compression/expansion unit) Enable 2 2 SWRS033E Page 166 of 239 CC1110Fx / CC1111Fx 0xDF41: I2SCFG1 – I2S Configuration Register 1 Bit 7:3 Field Name WORDS[4:0] Reset 01111 R/W R/W Description This field gives the word size – 1. The word size is the bit-length of one sample for one channel. Used to generate the WS signal when in master mode. Reset value 01111 corresponds to 16 bit samples. 2:1 TRIGNUM[1:0] 00 R/W Word counter copy / clear trigger 00 01 10 11 0 IOLOC 0 R/W No trigger. Counter copied / cleared by writing to the I2SWCNT register USB SOF (CC1111Fx only) IOC_1 (P1_3) T1_CH0 2 The pin locations for the I S signals. This bit selects between the two alternative pin mapping alternatives. Refer to Table 50 on page 93 for an overview of pin locations. 0 1 Alt. 1 in Table 50 is used Alt. 2 in Table 50 is used 2 Note: The I S interface will have precedence in cases where other periherals (exept for the debug interface) are configured to be on the same location. 0xDF42: I2SDATL – I2S Data Low Byte Bit 7:0 Field Name I2SDAT[7:0] Reset 0x00 R/W R/W Description Data register low byte. If this register is not written between two writes to the I2SDATH register, the low byte of the TX register will be cleared. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 0xDF43: I2SDATH – I2S Data High Byte Bit 7:0 Field Name I2SDAT[15:8] Reset 0x00 R/W R/W Description Data register high byte. When this register is read, I2SSTAT.RXIRQ is de-asserted and the RX buffer is considered empty. When this register is written, I2SSTAT.TXIRQ is de-asserted and the TX buffer is considered full. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 0xDF44: I2SWCNT – I2S Word Count Register Bit 7:0 Field Name WCNT[7:0] Reset 0x00 R/W R/W Description This register contains the 8 low order bits of the 10-bit internal word counter at the time of the last trigger. If this register is written (any value),the value of the internal word counter is copied into this register and I2SSTAT.WCNT[9:8], and the internal word counter is cleared. Refer to section 13.15.11 for details about how to use this register. SWRS033E Page 167 of 239 CC1110Fx / CC1111Fx 0xDF45: I2SSTAT – I2S Status Register Bit 7 6 5 Field Name TXUNF RXOVF TXLR Reset 0 0 0 R/W R/W R/W R Description TX buffer underflow. This bit must be cleared by software Rx buffer overflow. This bit must be cleared by software 0 Left channel should be placed in transmit buffer 1 Right channel should be placed in transmit buffer 4 RXLR 0 R 0 Left channel currently in receive buffer 1 Right channel currently in receive buffer 3 TXIRQ 0 R/W 1 H0 TX interrupt flag. This bit is cleared by hardware when the I2SDATH register is written. 0 Interrupt not pending 1 Interrupt pending 2 RXIRQ 0 R/W 1 H0 1:0 WCNT[9:8] 00 R RX Interrupt flag. This is cleared by hardware when the I2SDATH register is read. 0 Interrupt not pending 1 Interrupt pending Upper 2 bits of the 10-bit internal word counter at the time of the last trigger 0xDF46: I2SCLKF0 – I2S Clock Configuration Register 0 Bit 7:0 Field Name DENOM[7:0] Reset 0x93 R/W R/W Description The clock division denominator low bits 0xDF47: I2SCLKF1 – I2S Clock Configuration Register 1 Bit 7:0 Field Name NUM[7:0] Reset 0xE2 R/W R/W Description Clock division numerator low bits 0xDF48: I2SCLKF2 – I2S Clock Configuration Register 2 Bit 7 6:0 Field Name DENOM[8] NUM[14:8] Reset 0 0x04 R/W R/W R/W Description Clock division denominator high bits Clock division numerator high bits SWRS033E Page 168 of 239 CC1110Fx / CC1111Fx 13.16 USB Controller Note: The USB controller is only available on the CC1111Fx. The CC1111Fx contains a Full-Speed USB 2.0 compatible USB controller for serial communication with a PC or other equipment with USB host functionality. Note: This section will focus on describing the functionality of the USB controller, and it is assumed that the reader has a good understanding of USB and is familiar with the terms and concepts used. Refer to the Universal Serial Bus Specification for details [6]. Standard USB nomenclature is used regarding IN and OUT. I.e., IN is always into the host (PC) and OUT is out of the host (into the CC1111Fx) The USB controller monitors the USB bus for relevant activity and handles packet transfers. The CC1111Fx will always operate as a slave on the USB bus and responds only on requests from the host (a packet can only be sent (or received) when the USB host sends a request in the form of a token). Appropriate response to USB interrupts and loading/unloading of packets into/from endpoint FIFOs is the responsibility of the firmware. The firmware must be able to reply correctly to all standard requests from the USB host and work according to the protocol implemented in the driver on the PC. The USB Controller has the following features: • Full-Speed operation (up to 12 Mbps) • 5 endpoints (in addition to endpoint 0) that can be used as IN, OUT, or IN/OUT and can be configured as bulk/interrupt or isochronous. • 1 KB SRAM FIFO available for storing USB packets • Endpoints supporting packet sizes from 8 – 512 bytes • Support for double buffering of USB packets Figure 42 shows a block diagram of the USB controller. The USB PHY is the physical interface with input and output drivers. The USB SIE is the Serial Interface Engine which controls the packet transfer to/from the endpoints. The USB controller is connected to the rest of the system through the Memory Arbiter. USB Controller EP0 EP1 DP USB PHY DM USB SIE EP3 EP4 EP5 EP2 Memory Arbiter 1 KB SRAM (FIFOs) Figure 42: USB Controller Block Diagram 13.16.1 48 MHz Clock A 48 MHz external crystal must be used for the USB Controller to operate correctly. This 48 MHz clock is divided by two internally to generate a maximum system clock frequency of 24 MHz. It is important that the crystal oscillator is stable before the USB Controller is accessed. See 13.1.5.1 for details on how to set up the crystal oscillator. 13.16.2 USB Enable The USB Controller must be enabled before it is used. This is performed by setting the SLEEP.USB_EN bit to 1. Setting Page 169 of 239 SWRS033E CC1110Fx / CC1111Fx SLEEP.USB_EN controller. to 0 will reset the USB 13.16.3 USB Interrupts There are 3 interrupt flag registers with associated interrupt enable mask registers. Description Contains flags for common USB interrupts Contains interrupt flags for endpoint 0 and all the IN endpoints Contains interrupt flags for all OUT endpoints Associated Interrupt Enable Mask Register Interrupt Flag USBCIF USBIIF USBOIF USBCIE USBIIE USBOIE Note: All interrupts except SOF and suspend are initially enabled after reset Table 59: USB Interrupt Flags Interrupt Enable Mask Registers In addition to the interrupt flags in the registers shown in Table 59, there are two CPU interrupt flags associated with the USB controller; IRCON2.USBIF and IRCON.P0IF. For an interrupt request to be generated, IEN1.P0IE and/or IEN2.USBIE must be set to 1 together with the desired interrupt enable bits from the USBCIE, USBIIE, and USBOIE registers. When an interrupt request has been generated, the CPU which will start executing the ISR if there are no higher priority interrupts pending. The USB controller uses interrupt #6 for USB interrupts. This interrupt number is shared with Port 2 inputs, hence the interrupt routine must also handle Port 2 interrupts if they are enabled. The interrupt routine should read all the interrupt flag registers and take action depending on the status of the flags. The interrupt flag registers will be cleared when they are read and the status of the individual interrupt flags should therefore be saved in memory (typically in a local variable on the stack) to allow them to be accessed multiple times. At the end of the ISR, after the interrupt flags have been read, the interrupt flags should be cleared to allow for new USB/P2 interrupts to be detected. The port 2 interrupt status flags in the P2IFG register should be cleared prior to clearing IRCON2.P2IF (see section 11.5.2). Refer to Table 39 and Table 40 for a complete list of interrupts, and section 11.5 for more details about interrupts. 13.16.3.1 USB Resume Interrupt P0_7 does not exist on the CC1111Fx, but the corresponding interrupt is used for USB resume interrupt. This means that to be able to wake up the CC1111Fx from PM1/suspend when resume signaling has been detected on the USB bus, IEN1.P0IE must be set to 1 together with PICTL.P0IENH. PICTL.P0ICON must be 0 to enable interrupts on rising edge. The P0 ISR should check the P0IFG.USB_RESUME, and resume if this bit is set to 1. If PM1 is entered from within an ISR due to a suspend interrupt, it is important that the priority of the P0 interrupt is set higher than the priority of the interrupt from which PM1 was entered. See section 13.16.9 for more details about suspend and resume. 13.16.4 Endpoint 0 Endpoint 0 (EP0) is a bi-directional control endpoint and during the enumeration phase all communication is performed across this endpoint. Before the USBADDR register has been set to a value other than 0, the USB controller will only be able to communicate through endpoint 0. Setting the USBADDR register to a value between 1 and 127 will bring the USB function out of the Default state in the enumeration phase and into the Address state. All configured endpoints will then be available for the application. The EP0 FIFO is only used as either IN or OUT and double buffering is not provided for endpoint 0. The maximum packet size for endpoint 0 is fixed at 32 bytes. Endpoint 0 is controlled through the USBCS0 register by setting the USBINDEX register to 0. The USBCNT0 register contains the number of bytes received. 13.16.5 Endpoint 0 Interrupts The following events may generate an EP0 interrupt request: • A data packet has been received (USBCS0.OUTPKT_RDY=1) • A data packet that was loaded into the EP0 FIFO has been sent to the USB host (USBCS0.INPKT_RDY should be set to 1 when a new packet is ready to SWRS033E Page 170 of 239 CC1110Fx / CC1111Fx be transferred. This bit will be cleared by HW when the data packet has been sent) • An IN transaction has been completed (the interrupt is generated during the Status stage of the transaction) •A STALL has been sent (USBCS0.SENT_STALL=1) • A control transfer ends due to a premature end of control transfer (USBCS0.SETUP_END=1) Any of these events will cause the USBIIF.EP0IF to be asserted regardless of the status of the EP0 interrupt mask bit USBIIE.EP0IE. If the EP0 interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.USBIF will also be asserted. An interrupt request is only generated if IEN2.USBIE and USBIIE.EP0IE are both set to 1. 13.16.5.1 Error Conditions When a protocol error occurs, the USB controller sends a STALL handshake. The USBCS0.SENT_STALL bit is asserted and an interrupt request is generated if the endpoint 0 interrupt is properly enabled. A protocol error can be any of the following: • An OUT token is received after USBCS0.DATA_END has been set to complete the OUT Data stage (the host tries to send more data than expected) • An IN token is received after USBCS0.DATA_END has been set to complete the IN Data stage (the host tries to receive more data than expected) • The USB host tries to send a packet that exceeds the maximum packet size during the OUT Data stage • The size of the DATA1 packet received during the Status stage is not 0 The firmware can also terminate the current transaction by setting the USBCS0.SEND_STALL bit to 1. The USB controller will then send a STALL handshake in response to the next requests from the USB host. If an EP0 interrupt is caused by the assertion of the USBCS0.SENT_STALL bit, this bit should be de-asserted and firmware should consider the transfer as aborted (free memory buffers etc.). If EP0 receives an unexpected token during the Data stage, the USBCS0.SETUP_END bit will be asserted and an EP0 interrupt will be generated (if enabled properly). EP0 will then switch to the IDLE state. Firmware should then set the USBCS0.CLR_SETUP_END bit to 1 and abort the current transfer. If USBCS0.OUTPKT_RDY is asserted, this indicates that another Setup Packet has been received that firmware should process. 13.16.5.2 SETUP Transactions (IDLE State) The control transfer consists of 2 – 3 stages of transactions (Setup – Data - Status or Setup Status). The first transaction is a Setup transaction. A successful Setup transaction comprises three sequential packets (a token packet, a data packet, and a handshake packet), where the data field (payload) of the data packet is exactly 8 bytes long and are referred to as the Setup Packet. In the Setup stage of a control transfer, EP0 will be in the IDLE state. The USB controller will reject the data packet if the Setup Packet is not 8 bytes. Also, the USB controller will examine the contents of the Setup Packet to determine whether or not there is a Data stage in the control transfer. If there is a Data stage, EP0 will switch state to TX (IN transaction) or RX (OUT transaction) when the USBCS0.CLR_OUTPKT_RDY bit is set to 1 (if USBCS0.DATA_END=0). When a packet is received, the USBCS0.OUTPKT_RDY bit will be asserted and an interrupt request is generated (EP0 interrupt) if the interrupt has been enabled. Firmware should perform the following when a Setup Packet has been received: 1. Unload the Setup Packet from the EP0 FIFO 2. Examine the contents and perform the appropriate operations 3. Set the USBCS0.CLR_OUTPKT_RDY bit to 1. This denotes the end of the Setup stage. If the control transfer has no Data stage, the USBCS0.DATA_END bit must also be set. If there is no Data stage, the USB Controller will stay in the IDLE state. 13.16.5.3 IN Transactions (TX state) If the control transfer requires data to be sent to the host, the Setup stage will be followed by one or more IN transactions in the Data stage. In this case the USB controller will be in TX state and only accept IN tokens. A successful IN transaction comprises two or three sequential packets (a token packet, a data SWRS033E Page 171 of 239 CC1110Fx / CC1111Fx packet, and a handshake packet17). If more than 32 bytes (maximum packet size) is to be sent, the data must be split into a number of 32 byte packets followed by a residual packet. If the number of bytes to send is a multiple of 32, the residual packet will be a zero length data packet, hence a packet size less than 32 bytes denotes the end of the transfer. Firmware should load the EP0 FIFO with the first data packet and set the USBCS0.INPKT_RDY bit as soon as possible after the USBCS0.CLR_OUTPKT_RDY bit has been set. The USBCS0.INPKT_RDY will be cleared and an EP0 interrupt will be generated when the data packet has been sent. Firmware might then load more data packets as necessary. An EP0 interrupt will be generated for each packet sent. Firmware must set USBCS0.DATA_END in addition to USBCS0.INPKT_RDY when the last data packet has been loaded. This will start the Status stage of the control transfer. EP0 will switch to the IDLE state when the Status stage has completed. The Status stage may fail if the USBCS0.SEND_STALL bit is set to 1. The USBCS0.SENT_STALL bit will then be asserted and an EP0 interrupt will be generated as explained in section 13.16.5.1. If USBCS0.INPKT_RDY is not set when receiving an IN token, the USB Controller will reply with a NAK to indicate that the endpoint is working, but temporarily has no data to send. 13.16.5.4 OUT Transactions (RX state) If the control transfer requires data to be received from the host, the Setup stage will be followed by one or more OUT transactions in the Data stage. In this case the USB controller will be in RX state and only accept OUT tokens. A successful OUT transaction comprises two or three sequential packets (a token packet, a data packet, and a handshake packet18). If more than 32 bytes (maximum packet size) is to be received, the data must be split into a number of 32 byte packets followed by a residual packet. If the number of bytes to receive is a multiple of 32, the residual packet will be a zero length data packet, hence 17 a data packet with payload less than 32 bytes denotes the end of the transfer. The USBCS0.OUTPKT_RDY bit will be set and an EP0 interrupt will be generated when a data packet has been received. The firmware should set USBCS0.CLR_OUTPKT_RDY when the data packet has been unloaded from the EP0 FIFO. When the last data packet has been received (packet size less than 32 bytes) firmware should also set the USBCS0.DATA_END bit. This will start the Status stage of the control transfer. The size of the data packet is kept in the USBCNT0 registers. Note that this value is only valid when USBCS0.OUTPKT_RDY=1. EP0 will switch to the IDLE state when the Status stage has completed. The Status stage may fail if the DATA1 packet received is not a zero length data packet or if the USBCS0.SEND_STALL bit is set to 1. The USBCS0.SENT_STALL bit will then be asserted and an EP0 interrupt will be generated as explained in section 13.16.5.1. 13.16.6 Endpoints 1 – 5 Each endpoint can be used as an IN only, an OUT only, or IN/OUT. For an IN/OUT endpoint there are basically two endpoints, an IN endpoint and an OUT endpoint associated with the endpoint number. Configuration and control of IN endpoints is performed through the USBCSIL and USBCSIH registers. The USBCSOL and USBCSOH registers are used to configure and control OUT endpoints. Each IN and OUT endpoint can be configured as either Isochronous (USBCSIH.ISO=1 and/or USBCSOH.ISO=1) or Bulk/Interrupt (USBCSIH.ISO=0 and/or USBCSOH.ISO=0) endpoints. Bulk and Interrupt endpoints are handled identically by the USB controller but will have different properties from a firmware perspective. The USBINDEX register must have the value of the endpoint number before the Indexed Endpoint Registers are accessed (see Table 35 on page 53). 13.16.6.1 FIFO Management Each endpoint has a certain number of FIFO memory bytes available for incoming and outgoing data packets. Table 60 shows the FIFO size for endpoints 1 - 5. It is the firmware that is responsible for setting the USBMAXI and USBMAXO registers correctly for each endpoint to prevent data from being overwritten. For isochronous transfers there would not be a handshake packet from the host For isochronous transfers there would not be a handshake packet from the CC1111Fx 18 SWRS033E Page 172 of 239 CC1110Fx / CC1111Fx When both the IN and the OUT endpoint of an endpoint number do not use double buffering, the sum of USBMAXI and USBMAXO must not exceed the FIFO size for the endpoint. Figure 43 a) shows how the IN and OUT FIFO memory for an endpoint is organized with single buffering. The IN FIFO grows down from the top of the endpoint memory region while the OUT FIFO grows up from the bottom of the endpoint memory region. When the IN or OUT endpoint of an endpoint number use double buffering, the sum of USBMAXI and USBMAXO must not exceed half the FIFO size for the endpoint. Figure 43 b) illustrates the IN and OUT FIFO memory for an endpoint that uses double buffering. Notice that the second OUT buffer starts from the middle of the memory region and grows upwards. The second IN buffer also starts from the middle of the memory region but grows downwards. To configure an endpoint as IN only, set USBMAXO to 0 and to configure an endpoint as OUT only, set USBMAXI to 0. For unused endpoints, both USBMAXO and USBMAXI should be set to 0. EP Number 1 2 3 4 5 FIFO Size (in bytes) 32 64 128 256 512 Table 60: FIFO Sizes for EP 1 – 5 0 0 IN FIFO USBMAXI - 1 USBMAXI - 1 USBMAX0 - 1 0 0 IN FIFO (Buffer 1) OUT FIFO (Buffer 2) IN FIFO (Buffer 2) USBMAX0 - 1 USBMAXI - 1 USBMAX0 - 1 OUT FIFO 0 0 OUT FIFO (Buffer 1) b) a) Figure 43: IN/OUT FIFOs, a) Single Buffering b) Double Buffering 13.16.6.2 Double Buffering To enable faster transfer and reduce the need for retransmissions, CC1111Fx implements double buffering, allowing two packets to be buffered in the FIFO in each direction. This is highly recommended for isochronous endpoints, which are expected to transfer one data packet every USB frame without any retransmission. For isochronous endpoint one data packet will be sent/received every USB frame. However, the data packet may be sent/received at any time during the USB frame period and there is a chance that two data packets may be sent/received at a few micro seconds interval. For isochronous endpoints, an incoming packet will be lost if there is no buffer available and a zero length data packet will be sent if there is no data packet ready for transmission when the USB host requests data. Double buffering is not as critical for bulk and interrupt endpoints as it is for isochronous endpoint since packets will not be lost. Double buffering, however, may improve the effective data rate for bulk endpoints. To enable double buffering for an IN endpoint, USBCSIH.IN_DBL_BUF must be set to 1. To enable double buffering for an OUT endpoint, set USBCSOH.OUT_DBL_BUF to 1. 13.16.6.3 FIFO Access The endpoint FIFOs are accessed by reading and writing to the registers in Table 36 on page 53. Writing to a register causes the byte written to be inserted into the IN FIFO. Reading a register causes the next byte in the OUT FIFO to be extracted and the value of this byte to be returned. Page 173 of 239 SWRS033E CC1110Fx / CC1111Fx When a data packet has been written to an IN FIFO, the USBCSIL.INPKT_RDY bit must be set to 1. If double buffering is enabled, the USBCSIL.INPKT_RDY bit will be cleared immediately after it has been written and another data packet can be loaded. This will not generate an IN endpoint interrupt, since an interrupt is only generated when a packet has been sent. When double buffering is used firmware should check the status of the USBCSIL.PKT_PRESENT bit before writing to the IN FIFO. If this bit is 0, two data packets can be written. Double buffered isochronous endpoints should only need to load two packets the first time the IN FIFO is loaded. After that, one packet is loaded for every USB frame. To send a zero length data packet, USBCSIL.INPKT_RDY should be set to 1 without loading a data packet into the IN FIFO. A data packet can be read from the OUT FIFO when the USBCSOL.OUTPKT_RDY bit is 1. An interrupt will be generated when this occurs, if enabled. The size of the data packet is kept in the USBCNTH:USBCNTL registers. Note that this value is only valid when USBCSOL.OUTPKT_RDY=1. When the data packet has been read from the OUT FIFO, the USBCSOL.OUTPKT_RDY bit must be cleared. If double buffering is enabled there may be two data packets in the FIFO. If another data packet is ready when the USBCSOL.OUTPKT_RDY bit is cleared the USBCSOL.OUTPKT_RDY bit will be asserted immediately and an interrupt will be generated (if enabled) to signal that a new data packet has been received. The USBCSOL.FIFO_FULL bit will be set when there are two data packets in the OUT FIFO. The AutoClear feature is supported for OUT endpoints. When enabled, the USBCSOL.OUTPKT_RDY bit is cleared automatically when USBMAXO bytes have been read from the OUT FIFO. The AutoClear feature is enabled by setting USBCSOH.AUTOCLEAR=1. The AutoClear feature can be used to reduce the time the data packet occupies the OUT FIFO buffer and is typically used for bulk endpoints. A complementary AutoSet feature is supported for IN endpoints. When enabled, the USBCSIL.INPKT_RDY bit is set automatically when USBMAXI bytes have been written to the IN FIFO. The AutoSet feature is enabled by setting USBCSIH.AUTOSET=1. The AutoSet feature can reduce the overall time it takes to send a data packet and is typically used for bulk endpoints. 13.16.6.4 Endpoint 1 – 5 Interrupts The following events may generate an IN EPx interrupt request (x indicates the endpoint number): • A data packet that was loaded into the IN FIFO has been sent to the USB host (USBCSIL.INPKT_RDY should be set to 1 when a new packet is ready to be transferred. This bit will be cleared by HW when the data packet has been sent) •A STALL has been sent (USBCSIL.SENT_STALL=1). Only Bulk/Interrupt endpoints can be stalled • The IN FIFO is flushed due to the USBCSIH.FLUSH_PACKET bit being set to 1 Any of these events will cause USBIIF.INEPxIF to be asserted regardless of the status of the IN EPx interrupt mask bit USBIIE.INEPxIE. If the IN EPx interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.USBIF will also be asserted. An interrupt request is only generated if IEN2.USBIE and USBIIE.INEPxIE are both set to 1. The x in the register names refer to the endpoint number 1 - 5) The following events may generate an OUT EPx interrupt request: • A data packet has been received (USBCSOL.OUTPKT_RDY=1) •A STALL has been sent (USBCSIL.SENT_STALL=1). Only Bulk/Interrupt endpoints can be stalled Any of these events will cause USBOIF.OUTEPxIF to be asserted regardless of the status of the OUT EPx interrupt mask bit USBOIE.OUTEPxIE. If the OUT EPx interrupt mask bit is set to 1, the CPU interrupt flag IRCON2.USBIF will also be asserted. An interrupt request is only generated if IEN2.USBIE and USBOIE.OUTEPxIE are both set to 1. 13.16.6.5 Bulk/Interrupt IN Endpoint Interrupt IN transfers occur at regular intervals while bulk IN transfers utilize available bandwidth not allocated to isochronous, interrupt, or control transfers. Interrupt IN endpoints may set the USBCSIH.FORCE_DATA_TOG bit. When this bit is set the data toggle bit is continuously toggled regardless of whether an ACK was received or not. This feature is typically used SWRS033E Page 174 of 239 CC1110Fx / CC1111Fx by interrupt IN endpoints that are used to communicate rate feedback for Isochronous endpoints. A Bulk/Interrupt IN endpoint can be stalled by setting the USBCSIL.SEND_STALL bit to 1. When the endpoint is stalled, the USB controller will respond with a STALL handshake to IN tokens. The USBCSIL.SENT_STALL bit will then be set and an interrupt will be generated, if enabled. A bulk transfer longer than the maximum packet size is performed by splitting the transfer into a number of data packets of maximum size followed by a smaller data packet containing the remaining bytes. If the transfer length is a multiple of the maximum packet size, a zero length data packet is sent last. This means that a packet with a size less than the maximum packet size denotes the end of the transfer. The AutoSet feature can be useful in this case, since many data packets will be of maximum size. 13.16.6.6 Isochronous IN Endpoint An Isochronous IN endpoint is used to transfer periodic data from the USB controller to the host (one data packet every USB frame). If there is no data packet loaded in the IN FIFO when the USB host requests data, the USB controller sends a zero length data packet and the USBCSIL.UNDERRUN bit will be asserted. Double buffering requires that a data packet is loaded into the IN FIFO during the frame preceding the frame where it should be sent. If the first data packet is loaded before an IN token is received, the data packet will be sent during the same frame as it was loaded and hence violate the double buffering strategy. Thus, when double buffering is used, the USBPOW.ISO_WAIT_SOF bit should be set to 1 to avoid this. Setting this bit will ensure that a loaded data packet is not sent until the next SOF token has been received. The AutoSet feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame. 13.16.6.7 Bulk/Interrupt OUT Endpoint Interrupt OUT transfers occur at regular intervals while bulk OUT transfers utilize available bandwidth not allocated to isochronous, interrupt, or control transfers. A Bulk/Interrupt OUT endpoint can be stalled by setting the USBCSOL.SEND_STALL bit to 1. When the endpoint is stalled, the USB controller will respond with a STALL handshake when the host is done sending the data packet. The data packet is discarded and is not placed in the OUT FIFO. The USB controller will assert the USBCSOL.SENT_STALL bit when the STALL handshake is sent and generate an interrupt request if the OUT endpoint interrupt is enabled. As the AutoSet feature is useful for bulk IN endpoints, the AutoClear feature is useful for OUT endpoints since many packets will be of maximum size. 13.16.6.8 Isochronous OUT Endpoint An Isochronous OUT endpoint is used to transfer periodic data from the host to the USB controller (one data packet every USB frame). If there is no buffer available when a data packet is being received, the USBCSOL.OVERRUN bit will be asserted and the packet data will be lost. Firmware can reduce the chance for this to happen by using double buffering and use DMA to effectively unload data packets. An isochronous data packet in the OUT FIFO may have bit errors. The hardware will detect this condition and set USBCSOL.DATA_ERROR. Firmware should therefore always check this bit when unloading a data packet. The AutoClear feature will typically not be used for isochronous endpoints since the packet size will increase or decrease from frame to frame. 13.16.7 DMA DMA should be used to fill the IN endpoint FIFOs and empty the OUT endpoint FIFOs. Using DMA will improve the read/write performance significantly compared to using the 8051 CPU. It is therefore highly recommended to use DMA unless timing is not critical or only a few bytes are to be transferred. There are no DMA triggers for the USB controller, meaning that DMA transfers must be triggered by firmware. The word size can be byte (8 bits) or word (16 bits). When word size transfer is used the ENDIAN register must be set correctly (see section 11.2.3.6). The ENDIAN.USBRLE bit selects whether a word is read as little or big endian from the OUT FIFOs and the ENDIAN.USBWLE bit selects whether a word is written as little or big endian to the IN FIFOs. SWRS033E Page 175 of 239 CC1110Fx / CC1111Fx Writing and reading words for the different settings is shown in Figure 44 and Figure 45 respectively. Notice that the setting for these bits will be used for all endpoints. Consequently, it is not possible to have multiple DMA channels active at once that use different endianness. The ENDIAN register must be configured to use big endian for both read and write for a word size transfer to produce the same result as a byte size transfer of an even number of bytes. Word size transfers are slightly more efficient than byte transfers. Refer to section regarding DMA. 13.5 for more details Figure 44: Writing Big/Little Endian Figure 45: Reading Big/Little Endian 13.16.8 USB Reset When reset signaling is detected on the bus, the USBCIF.RSTIF flag will be asserted. If USBCIE.RSTIE is enabled, IRCON2.USBIF will also be asserted and an interrupt request is generated if IEN2.USBIE=1. The firmware should take appropriate action when a USB reset occurs. A USB reset should place the device in the Default state where it will only respond to address 0 (the default address). One or more resets will normally take place during the enumeration phase right after the USB cable is connected. The following actions are performed by the USB controller when a USB reset occurs: • • • • USBADDR is set to 0 USBINDEX is set to 0 All endpoint FIFOs are flushed USBCS0, USBCSIL, USBCSIH, USBCSOL, USBCSOH are cleared. • All interrupts, except SOF and suspend, are enabled • An interrupt request is generated (if IEN2.USBIE=1 and USBCIE.RSTIE=1) SWRS033E Page 176 of 239 CC1110Fx / CC1111Fx Firmware should close all pipes and wait for a new enumeration phase when USB reset is detected. 13.16.9 Suspend and Resume The USB controller will assert USBCIF.SUSPENDIF and enter suspend mode when the USB bus has been continuously idle for 3 ms, provided that USBPOW.SUSPEND_EN=1. IRCON2.USBIF will be asserted if USBCIE.SUSPENDIE is enabled, and an interrupt request is generated if IEN2.USBIE=1. While in suspend mode, only limited current can be sourced from the USB bus. See the USB 2.0 Specification [6] for details about this. To be able to meet the suspend-current requirement, the CC1111Fx should be taken down to PM1 when suspend is detected. The CC1111Fx should not enter PM2 or PM3 since this will reset the USB controller. Any valid non-idle signaling on the USB bus will cause the USBCIF.RESUMIF to be asserted and an interrupt request to be generated and wake up the system if the USB resume interrupt is configured correctly. Refer to 13.16.3.1 for details about how to set up the USB resume interrupt. Any valid non-idle signaling on the USB bus will cause the USBCIF.RESUMIF to be asserted and an interrupt request to be generated and wake up the system if the USB resume interrupt is configured correctly. Refer to 13.16.3.1 for details about how to set up the USB resume interrupt. When the system wakes up (enters active mode) from suspend, no USB registers must be accessed before the 48 MHZ crystal oscillator has stabilized. A USB reset will also wake up the system from suspend. A USB resume interrupt request will be generated, if the interrupt is configured as described in 13.16.3.1, but the USBCIF.RSTIF interrupt flag will be set instead of the USBCIF.RESUMIF interrupt flag. 13.16.10 Remote Wakeup The USB controller can resume from suspend by signaling resume to the USB hub. Resume is performed by setting USBPOW.RESUME to 1 for approximately 10 ms. According to the USB 2.0 Specification [6], the resume signaling must be present for at least 1 ms and no more than 15 ms. It is, however, recommended to keep the resume signaling for approximately 10 ms. Notice that support for remote wakeup must be declared in the USB descriptor, and that the USB host must grant the device the privilege to perform remote wakeup (through a SET_FEATURE request). 13.16.11 USB Registers This section describes all USB registers used for control and status for the USB. The USB registers reside in XDATA memory space in the region 0xDE00 - 0xDE3F. These registers can be divided into three groups: The Common USB Registers, the Indexed Endpoint Registers, and the Endpoint FIFO Registers. Table 34, Table 35, and Table 36 give an overview of the registers in the three groups respectively, while the remaining of this section will describe each register in detail. The Indexed Endpoint Registers represent the currently selected endpoint. The USBINDEX register is used to select the endpoint. Notice that the upper register addresses 0xDE2C – 0xDE3F are reserved. SWRS033E Page 177 of 239 CC1110Fx / CC1111Fx 0xDE00: USBADDR – Function Address Bit 7 6:0 Field Name UPDATE USBADDR[6:0] Reset 0 0x00 R/W R R/W Description This bit is set when the USBADDR register is written and cleared when the address becomes effective. Device address 0xDE01: USBPOW – Power/Control Register Bit 7 Field Name ISO_WAIT_SOF Reset 0 R/W R/W Description When this bit is set to 1, the USB controller will send zero length data packets from the time INPKT_RDY is asserted and until the first SOF token has been received. This only applies to isochronous endpoints. Not used During reset signaling, this bit is set to1 Drive resume signaling for remote wakeup. According to the USB Specification the duration of driving resume must be at least 1 ms and no more than 15 ms. It is recommended to keep this bit set for approximately 10 ms. Suspend mode entered. This bit will only be used when SUSPEND_EN=1. Reading the USBCIF register or asserting RESUME will clear this bit. Suspend Enable. When this bit is set to 1, suspend mode will be entered when USB bus has been idle for 3 ms. 6:4 3 2 RST RESUME 0 0 R0 R R/W 1 0 SUSPEND SUSPEND_EN 0 0 R R/W 0xDE02: USBIIF – IN Endpoints and EP0 Interrupt Flags Bit 7:6 5 4 3 2 1 0 INEP5IF INEP4IF INEP3IF INEP2IF INEP1IF EP0IF Field Name Reset 00 0 0 0 0 0 0 R/W R0 R, H0 R, H0 R, H0 R, H0 R, H0 R, H0 Description Reserved Interrupt flag for IN endpoint 5. Cleared by HW when read Interrupt flag for IN endpoint 4. Cleared by HW when read Interrupt flag for IN endpoint 3. Cleared by HW when read Interrupt flag for IN endpoint 2. Cleared by HW when read Interrupt flag for IN endpoint 1. Cleared by HW when read Interrupt flag for endpoint 0. Cleared by HW when read 0xDE04: USBOIF – Out Endpoints Interrupt Flags Bit 7:6 5 4 3 2 1 0 OUTEP5IF OUTEP4IF OUTEP3IF OUTEP2IF OUTEP1IF Field Name Reset 00 0 0 0 0 0 R/W R0 R, H0 R, H0 R, H0 R, H0 R, H0 R0 Description Reserved Interrupt flag for OUT endpoint 5. Cleared by HW when read Interrupt flag for OUT endpoint 4. Cleared by HW when read Interrupt flag for OUT endpoint 3. Cleared by HW when read Interrupt flag for OUT endpoint 2. Cleared by HW when read Interrupt flag for OUT endpoint 1. Cleared by HW when read Not used SWRS033E Page 178 of 239 CC1110Fx / CC1111Fx 0xDE06: USBCIF – Common USB Interrupt Flags Bit 7:4 3 2 1 0 SOFIF RSTIF RESUMEIF SUSPENDIF Field Name Reset 0 0 0 0 R/W R0 R, H0 R, H0 R, H0 R, H0 Description Not used Start-Of-Frame interrupt flag. Cleared by HW when read Reset interrupt flag. Cleared by HW when read Resume interrupt flag. Cleared by HW when read Suspend interrupt flag. Cleared by HW when read 0xDE07: USBIIE – IN Endpoints and EP0 Interrupt Enable Mask Bit 7:6 5 INEP5IE Field Name Reset 00 1 R/W R/W R/W Description Reserved. Always write 00 IN endpoint 5 interrupt enable 0 1 4 INEP4IE 1 R/W Interrupt disabled Interrupt enabled IN endpoint 4 interrupt enable 0 1 Interrupt disabled Interrupt enabled 3 INEP3IE 1 R/W IN endpoint 3 interrupt enable 0 1 Interrupt disabled Interrupt enabled 2 INEP2IE 1 R/W IN endpoint 2 interrupt enable 0 1 Interrupt disabled Interrupt enabled 1 INEP1IE 1 R/W IN endpoint 1 interrupt enable 0 1 Interrupt disabled Interrupt enabled 0 EP0IE 1 R/W Endpoint 0 interrupt enable 0 1 Interrupt disabled Interrupt enabled SWRS033E Page 179 of 239 CC1110Fx / CC1111Fx 0xDE09: USBOIE – Out Endpoints Interrupt Enable Mask Bit 7:6 5 OUTEP5IE Field Name Reset 00 1 R/W R/W R/W Description Reserved. Always write 00 OUT endpoint 5 interrupt enable 0 1 4 OUTEP4IE 1 R/W Interrupt disabled Interrupt enabled OUT endpoint 4 interrupt enable 0 1 Interrupt disabled Interrupt enabled 3 OUTEP3IE 1 R/W OUT endpoint 3 interrupt enable 0 1 Interrupt disabled Interrupt enabled 2 OUTEP2IE 1 R/W OUT endpoint 2 interrupt enable 0 1 Interrupt disabled Interrupt enabled 1 OUTEP1IE 1 R/W OUT endpoint 1 interrupt enable 0 1 Interrupt disabled Interrupt enabled 0 - R0 Not used 0xDE0B: USBCIE – Common USB Interrupt Enable Mask Bit 7:4 3 SOFIE Field Name Reset 0 R/W R0 R/W Description Not used Start-Of-Frame interrupt enable 0 1 2 RSTIE 1 R/W Interrupt disabled Interrupt enabled Reset interrupt enable 0 1 Interrupt disabled Interrupt enabled 1 RESUMEIE 1 R/W Resume interrupt enable 0 1 Interrupt disabled Interrupt enabled 0 SUSPENDIE 0 R/W Suspend interrupt enable 0 1 Interrupt disabled Interrupt enabled 0xDE0C: USBFRML – Current Frame Number (Low byte) Bit 7:0 Field Name FRAME[7:0] Reset 0x00 R/W R Description Low byte of 11-bit frame number SWRS033E Page 180 of 239 CC1110Fx / CC1111Fx 0xDE0D: USBFRMH – Current Frame Number (High byte) Bit 7:3 2:0 FRAME[10:8] Field Name Reset 000 R/W R0 R Description Not used 3 MSB of 11-bit frame number 0xDE0E: USBINDEX – Current Endpoint Index Register Bit 7:4 3:0 USBINDEX[3:0] Field Name Reset 0000 R/W R0 R/W Description Not used Endpoint selected. Must be set to value in the range 0 – 5 0xDE10: USBMAXI – Max. Packet Size for IN Endpoint{1-5} Bit 7:0 Field Name USBMAXI[7:0] Reset 0x00 R/W R/W Description Maximum packet size in units of 8 bytes for IN endpoint selected by USBINDEX register. The value of this register should correspond to the wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint. This register must not be set to a value grater than the available FIFO memory for the endpoint. 0xDE11: USBCS0 – EP0 Control and Status (USBINDEX=0) Bit 7 Field Name CLR_SETUP_END Reset 0 R/W R/W H0 6 CLR_OUTPKT_RDY 0 R/W H0 5 SEND_STALL 0 R/W H0 4 SETUP_END 0 R Description Set this bit to 1 to de-assert the SETUP_END bit of this register. This bit will be cleared automatically. Set this bit to 1 to de-assert the OUTPKT_RDY bit of this register. This bit will be cleared automatically. Set this bit to 1 to terminate the current transaction. The USB controller will send the STALL handshake and this bit will be de-asserted. This bit is set if the control transfer ends due to a premature end of control transfer. The FIFO will be flushed and an interrupt request (EP0) will be generated if the interrupt is enabled. Setting CLR_SETUP_END=1 will deassert this bit This bit is used to signal the end of a data transfer and must be asserted in the following three situations: 1 2 3 When the last data packet has been loaded and USBCS0.INPKT_RDY is set to 1 When the last data packet has been unloaded and USBCS0.CLR_OUTPKT_RDY is set to 1 When USBCS0.INPKT_RDY has been asserted without having loaded the FIFO (for sending a zero length data packet). 3 DATA_END 0 R/W H0 The USB controller will clear this bit automatically 2 SENT_STALL 0 R/W H1 1 INPKT_RDY 0 R/W H0 0 OUTPKT_RDY 0 R This bit is set when a STALL handshake has been sent. An interrupt request (EP0) will be generated if the interrupt is enabled This bit must be cleared from firmware. Set this bit when a data packet has been loaded into the EP0 FIFO to notify the USB controller that a new data packet is ready to be transferred. When the data packet has been sent, this bit is cleared and an interrupt request (EP0) will be generated if the interrupt is enabled. Data packet received. This bit is set when an incoming data packet has been placed in the OUT FIFO. An interrupt request (EP0) will be generated if the interrupt is enabled. Set CLR_OUTPKT_RDY=1 to de-assert this bit. SWRS033E Page 181 of 239 CC1110Fx / CC1111Fx 0xDE11: USBCSIL – IN EP{1-5} Control and Status Low Bit 7 Field Name Reset R/W R0 Description Not used 6 CLR_DATA_TOG 0 R/W H0 Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the next data packet to be a DATA0 packet. This bit is automatically cleared. This bit is set when a STALL handshake has been sent. The FIFO will be flushed and the INPKT_RDY bit in this register will be de-asserted. An interrupt request (IN EP{1 - 5}) will be generated if the interrupt is enabled. This bit must be cleared from firmware. Set this bit to 1 to make the USB controller reply with a STALL handshake when receiving IN tokens. Firmware must clear this bit to end the STALL condition. It is not possible to stall an isochronous endpoint, thus this bit will only have effect if the IN endpoint is configured as bulk/interrupt. Set to 1 to flush next packet that is ready to transfer from the IIN FIFO. The INPKT_RDY bit in this register will be cleared. If there are two packets in the IN FIFO due to double buffering, this bit must be set twice to completely flush the IN FIFO. This bit is automatically cleared. In isochronous mode, this bit is set if an IN token is received when INPKT_RDY=0, and a zero length data packet is transmitted in response to the IN token. In Bulk/Interrupt mode, this bit is set when a NAK is returned in response to an IN token. Firmware should clear this bit. This bit is 1 when there is at least one packet in the IN FIFO. Set this bit when a data packet has been loaded into the IN FIFO to notify the USB controller that a new data packet is ready to be transferred. When the data packet has been sent, this bit is cleared and an interrupt request (IN EP{1 - 5}) will be generated if the interrupt is enabled. 5 SENT_STALL 0 R/W 4 SEND_STALL 0 R/W 3 FLUSH_PACKET 0 R/W H0 2 UNDERRUN 0 R/W 1 0 PKT_PRESENT INPKT_RDY 0 0 R R/W H0 0xDE12: USBCSIH – IN EP{1-5} Control and Status High Bit 7 Field Name AUTOSET Reset 0 R/W R/W Description When this bit is 1, the USBCSIL.INPKT_RDY bit is automatically asserted when a data packet of maximum size (specified by USBMAXI) has been loaded into the IN FIFO. Selects IN endpoint type 0 1 5:4 3 FORCE_DATA_TOG 10 0 R/W R/W Bulk/Interrupt Isochronous 6 ISO 0 R/W Reserved. Always write 10 Setting this bit will force the IN endpoint data toggle to switch and the data packet to be flushed from the IN FIFO even though an ACK was received. This feature can be useful when reporting rate feedback for isochronous endpoints. Not used Double buffering enable (IN FIFO) 0 1 Double buffering disabled Double buffering enabled 2:1 0 IN_DBL_BUF 0 R0 R/W 0xDE13: USBMAXO – Max. Packet Size for OUT{1-5} Endpoint Bit 7:0 Field Name USBMAXO[7:0] Reset 0x00 R/W R/W Description Maximum packet size in units of 8 bytes for OUT endpoint selected by USBINDEX register. The value of this register should correspond to the wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint. This register must not be set to a value grater than the available FIFO memory for the endpoint. SWRS033E Page 182 of 239 CC1110Fx / CC1111Fx 0xDE14: USBCSOL – OUT EP{1-5} Control and Status Low Bit 7 Field Name CLR_DATA_TOG Reset 0 R/W R/W H0 6 SENT_STALL 0 R/W Description Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the next data packet to be a DATA0 packet. This bit is automatically cleared. This bit is set when a STALL handshake has been sent. An interrupt request (OUT EP{1 - 5}) will be generated if the interrupt is enabled. This bit must be cleared from firmware Set this bit to 1 to make the USB controller reply with a STALL handshake when receiving OUT tokens. Firmware must clear this bit to end the STALL condition. It is not possible to stall an isochronous endpoint, thus this bit will only have effect if the IN endpoint is configured as bulk/interrupt. Set to 1 to flush next packet that is to be read from the OUT FIFO. The OUTPKT_RDY bit in this register will be cleared. If there are two packets in the OUT FIFO due to double buffering, this bit must be set twice to completely flush the OUT FIFO. This bit is automatically cleared. This bit is set if there is a CRC or bit-stuff error in the packet received. Cleared when OUTPKT_RDY is cleared. This bit will only be valid if the OUT endpoint is isochronous. This bit is set when an OUT packet cannot be loaded into the OUT FIFO. Firmware should clear this bit. This bit is only valid in isochronous mode This bit is asserted when no more packets can be loaded into the OUT FIFO full. This bit is set when a packet has been received and is ready to be read from OUT FIFO. An interrupt request (OUT EP{1 - 5}) will be generated if the interrupt is enabled. This bit should be cleared when the packet has been unloaded from the FIFO. 5 SEND_STALL 0 R/W 4 FLUSH_PACKET 0 R/W H0 3 DATA_ERROR 0 R 2 1 0 OVERRUN FIFO_FULL OUTPKT_RDY 0 0 0 R/W R R/W 0xDE15: USBCSOH – OUT EP{1-5} Control and Status High Bit 7 Field Name AUTOCLEAR Reset 0 R/W R/W Description When this bit is set to 1, the USBCSOL.OUTPKT_RDY bit is automatically cleared when a data packet of maximum size (specified by USBMAXO) has been unloaded to the OUT FIFO. Selects OUT endpoint type 0 1 5:4 3:1 0 OUT_DBL_BUF 00 0 R/W R0 R/W Bulk/Interrupt Isochronous 6 ISO 0 R/W Reserved. Always write 00 Not used Double buffering enable (OUT FIFO) 0 1 Double buffering disabled Double buffering enabled 0xDE16: USBCNT0 – Number of Received Bytes in EP0 FIFO (USBINDEX=0) Bit 7:6 5:0 USBCNT0[5:0] Field Name Reset 000000 R/W R0 R Description Not used Number of received bytes into EP 0 FIFO. Only valid when OUTPKT_RDY is asserted 0xDE16: USBCNTL – Number of Bytes in EP{1 – 5} OUT FIFO Low Bit 7:0 Field Name USBCNT[7:0] Reset 0x00 R/W R Description 8 LSB of number of received bytes into OUT FIFO selected by USBINDEX register. Only valid when USBCSOL.OUTPKT_RDY is asserted. SWRS033E Page 183 of 239 CC1110Fx / CC1111Fx 0xDE17: USBCNTH – Number of Bytes in EP{1 – 5} OUT FIFO High Bit 7:3 2:0 USBCNT[10:8] Field Name Reset 000 R/W R0 R Description Not used 3 MSB of number of received bytes into OUT FIFO selected by USBINDEX register. Only valid when USBCSOL.OUTPKT_RDY is set 0xDE20: USBF0 – Endpoint 0 FIFO Bit 7:0 Field Name USBF0[7:0] Reset 0x00 R/W R/W Description Endpoint 0 FIFO. Reading this register unloads one byte from the EP0 FIFO. Writing to this register loads one byte into the EP0 FIFO. Note: The FIFO memory for EP0 is used for both incoming and outgoing data packets. 0xDE22: USBF1 – Endpoint 1 FIFO Bit 7:0 Field Name USBF1[7:0] Reset 0x00 R/W R/W Description Endpoint 1 FIFO register. Reading this register unloads one byte from the EP1 OUT FIFO. Writing to this register loads one byte into the EP1 IN FIFO. 0xDE24: USBF2 – Endpoint 2 FIFO Bit 7:0 Field Name USBF2[7:0] Reset 0x00 R/W R/W Description See Endpoint 1 FIFO description. 0xDE26: USBF3 – Endpoint 3 FIFO Bit 7:0 Field Name USBF3[7:0] Reset 0x00 R/W R/W Description See Endpoint 1 FIFO description. 0xDE28: USBF4 – Endpoint 4 FIFO Bit 7:0 Field Name USBF4[7:0] Reset 0x00 R/W R/W Description See Endpoint 1 FIFO description. 0xDE2A: USBF5 – Endpoint 5 FIFO Bit 7:0 Field Name USBF5[7:0] Reset 0x00 R/W R/W Description See Endpoint 1 FIFO description. SWRS033E Page 184 of 239 CC1110Fx / CC1111Fx 14 Radio RADIO CONTROL DEMODULATOR ADC LNA FEC / INTERLEAVER PACKET HANDLER RF_P RF_N 0 90 FREQ SYNTH MODULATOR PA Figure 46: CC1110Fx/CC1111Fx Radio Module A simplified block diagram of the radio module in the CC1110Fx/CC1111Fx is shown in Figure 46. The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode. The 26/48 MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. An SFR interface is used for data buffer access from the CPU. Configuration and status registers are accessed through registers mapped to XDATA memory. The digital baseband includes support for channel configuration, packet handling, and data buffering. CC1110Fx/CC1111Fx features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization are performed digitally. The transmitter part of CC1110Fx/CC1111Fx is based on direct synthesis of the RF frequency. Note: In this section of the document, fRef is used to denote the reference frequency for the synthesizer. For CC1110Fx fref = f XOSC and for CC1111Fx, f ref = 14.1 Command Strobes The CPU uses a set of command strobes to control operation of the radio. Command strobes may be viewed as single byte instructions which each start an internal sequence in the radio. These command . strobes are used to enable the frequency synthesizer, enable receive mode, enable transmit mode, etc. (see Figure 47). The 6 command strobes are listed in Table 61 on page 187. f XOSC 2 SWRS033E CPU INTERFACE ADC Page 185 of 239 CC1110Fx / CC1111Fx SIDLE Default state when the radio is not receiving or transmitting. Idle Used for calibrating frequency synthesizer upfront (entering Manual freq. receive or transmit mode can synth. calibration then be done quicker). Transitional state. SCAL SRX or STX or SFSTXON SFSTXON Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe. Frequency synthesizer startup, optional calibration, settling Frequency synthesizer is turned on, can optionally be calibrated, and then settles to correct frequency. Transitional state Frequency synthesizer on STX SRX STX TXOFF_MODE=01 SFSTXON or RXOFF_MODE=01 Transmit mode STX or RXOFF_MODE=10 SRX or TXOFF_MODE=11 Receive mode TXOFF_MODE=00 RXOFF_MODE=00 Transmission is turned off and this state is entered if the RFD register becomes empty in the middle of a packet. Typ. current consumption: 1.8 mA Optional transitional state. TX Overflow Optional freq. synth. calibration RX Overflow Reception is turned off and this state is entered if the RFD register overflows. SIDLE SIDLE Idle Figure 47: Simplified State Diagram with Typical Usage and Current Consumption in Radio at 250 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized) SWRS033E Page 186 of 239 CC1110Fx / CC1111Fx RFST Value 0x00 Command Strobe Name SFSTXON Description Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0) Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1. In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear. Enter IDLE state (frequency synthesizer turned off). No operation. 0x01 0x02 0x03 0x04 All others SCAL SRX STX SIDLE SNOP Table 61: Command Strobes 14.2 Radio Registers The operation of the radio is configured through a set of RF registers. These RF registers are mapped to XDATA memory space as shown in Figure 14 on page 43 . In addition to configuration registers, the RF registers also provide status information from the radio. Section 11.2.3.4 on page 50 gives a full description of all RF registers. 14.3 Interrupts There ar two interrupt vector assigned to the radio. These are the RFTXRX interrupt (interrupt #0) and the RF interrupt (interrupt #16): • RFTXRX: RX data ready or TX data complete (related to the RFD register) • RF: All other general RF interrupts The RF interrupt vector combines the interrupts shown in the RFIM register shown on page 189. Note that these RF interrupts are rising-edge triggered meaning that an interrupt is generated when e.g. the SFD status flag goes from 0 to 1. The RF interrupt flags are described in the next section. 14.3.1 Interrupt Registers 14.3.1.1 RFTXRX For an interrupt request to be generated when TCON.RFTXRXIF is asserted, IEN0.RFTXRXIE must be 1. 14.3.1.2 RF There are 8 different events that can generate an RF interrupt request. These events are: • • • • • • • • TX underflow RX overflow RX timeout Packet received/transmitted. Also used to detect overflow/underflow conditions CS PQT reached CCA SFD The RFTXTX interrupt is related to the RFD register. The CPU interrupt flag RFTXRXIF found in the TCON register is asserted when there are data in the RFD register ready to be read (RX), and when a new byte can be written (TX). Each of these events has a corresponding interrupt flag in the RFIF register which is asserted when the event occurs. If the corresponding mask bit is set in the RFIM register, the CPU interrupt flag S1CON.RFIF will also be asserted in addition to the interrupt flag in RFIF. If IEN2.RFIE=1 when S1CON.RFIF is asserted, and interrupt request will be generated. Refer to 11.5 for details about the interrupts. SWRS033E Page 187 of 239 CC1110Fx / CC1111Fx RFIF (0xE9) – RF Interrupt Flags Bit 7 Name IRQ_TXUNF Reset 0 R/W R/W0 Description TX underflow 0 1 6 IRQ_RXOVF 0 R/W0 No interrupt pending Interrupt pending RX overflow 0 1 No interrupt pending Interrupt pending 5 IRQ_TIMEOUT 0 R/W0 RX timeout, no packet has been received in the programmed period 0 1 No interrupt pending Interrupt pending 4 IRQ_DONE 0 R/W0 Packet received/transmitted. Also used to detect underflow/overflow conditions 0 1 No interrupt pending Interrupt pending 3 IRQ_CS 0 R/W0 Carrier sense 0 1 No interrupt pending Interrupt pending 2 IRQ_PQT 0 R/W0 Preamble quality threshold reached 0 1 No interrupt pending Interrupt pending 1 IRQ_CCA 0 R/W0 Clear Channel Assessment 0 1 No interrupt pending Interrupt pending 0 IRQ_SFD 0 R/W0 Start of Frame Delimiter, sync word detected 0 1 No interrupt pending Interrupt pending SWRS033E Page 188 of 239 CC1110Fx / CC1111Fx RFIM (0x91) – RF Interrupt Mask Bit 7 Name IM_TXUNF Reset 0 R/W R/W Description TX underflow 0 1 6 IM_RXOVF 0 R/W Interrupt disabled Interrupt enabled RX overflow 0 1 Interrupt disabled Interrupt enabled 5 IM_TIMEOUT 0 R/W RX timeout, no packet has been received in the programmed period. 0 1 Interrupt disabled Interrupt enabled 4 IM_DONE 0 R/W Packet received/transmitted. Also used to detect underflow/overflow conditions 0 1 Interrupt disabled Interrupt enabled 3 IM_CS 0 R/W Carrier sense 0 1 Interrupt disabled Interrupt enabled 2 IM_PQT 0 R/W Preamble quality threshold reached. 0 1 Interrupt disabled Interrupt enabled 1 IM_CCA 0 R/W Clear Channel Assessment 0 1 Interrupt disabled Interrupt enabled 0 IM_SFD 0 R/W Start of Frame Delimiter, sync word detected 0 1 Interrupt disabled Interrupt enabled 14.4 TX/RX Data Transfer Data to transmit is written to the RF Data register, RFD. Received data is read from the same register. The RFD register can be viewed as a 1 byte FIFO. That means that if a byte is received in the RFD register, and it is not read before the next byte is received, the radio will enter RX_OVERFLOW state and the RFIF.IRQ_RXOVF flag will be set together with RFIF.IRQ_DONE. In TX, the radio will enter TX_UNDERFLOW state (RFIF.IRQ_TXUVF and RFIF.IRQ_DONE will be asserted) if too few bytes are written to the RFD register compared to what the radio expect. To exit RX_OVERFLOW and/or TX_UNDERFLOW state, an SIDLE strobe command should be issued. Note: The RFD register content will not be retianed in PM2 and PM3 RX and TX FIFOs can be implemented in memory and it is recommended to use the SWRS033E Page 189 of 239 DMA to transfer data between the FIFOs and the RF Data register, RFD. The DMA channel used to transfer received data to memory when the radio is in RX mode would have RFD as the source (SRCADDR[15:0]), the RX FIFO in memory as destination (DRSTADDR[15:0]), and RADIO as DMA trigger (TRIG[4:0]). For description on the usage of DMA, refer to section 13.5 on page 102. A simple example of transmitting data is shown in Figure 48. This example does not use DMA. CC1110Fx / CC1111Fx ; Tranmit the following data: 0x02, 0x12, 0x34 ; (Assume that the radio has already been configured, the high speed ; crystal oscillator is selected as system clock, and CLKCON.CLKSPD=000) C1: C2: C3: MOV JNB CLR MOV JNB CLR MOV JNB CLR MOV RFST,#03H RFTXRXIF,C1 RFTXRXIF RFD,#02H RFTXRXIF,C2 RFTXRXIF RFD,#12H RFTXRXIF,C3 RFTXRXIF RFD,#34H ; ; ; ; ; ; ; ; ; ; ; Start TX with STX command strobe Wait for interrupt flag telling radio is ready to accept data, then write first data byte to radio (packet length = 2) Wait for radio Send first byte in payload Wait for radio Send second byte in payload Done Figure 48: Simple RF Transmit Example 14.5 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. Min Data Rate [kBaud] 0.8 3.17 6.35 12.7 25.4 50.8 101.6 203.1 406.3 Typical Data Rate [kBaud] 1.2 / 2.4 4.8 9.6 19.6 38.4 76.8 153.6 250 500 Max Data Rate [kBaud] 3.17 6.35 12.7 25.4 50.8 101.6 203.1 406.3 500 Data rate Step Size [kBaud] 0.0062 0.0124 0.0248 0.0496 0.0992 0.1984 0.3967 0.7935 1.5869 RDATA = (256 + DRATE _ M ) ⋅ 2 2 28 DRATE _ E ⋅ f ref The following approach can be used to find suitable values for a given data rate: ⎢ ⎛R ⋅ 2 20 ⎞⎥ ⎟⎥ DRATE _ E = ⎢log 2 ⎜ DATA ⎜ ⎟ f ref ⎢ ⎝ ⎠⎥ ⎣ ⎦ 28 RDATA ⋅ 2 DRATE _ M = − 256 f ref ⋅ 2 DRATE _ E If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. The datarate can be set from 1.2 kBaud to 500 kBaud with the minimum step size as found in Table 62. 14.6 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth. The following formula gives the relation between the register settings and the channel filter bandwidth: Table 62: Data Rate Step Size See section 13.1.5.2 on page 81 for limitations in data rate when using other system clock speeds than the default. BWchannel = f ref 8 ⋅ (4 + CHANBW _ M )·2CHANBW _ E For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. The following example illustrates this: Page 190 of 239 SWRS033E CC1110Fx / CC1111Fx With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of 500 kHz, which is 400 kHz. Assuming 915 MHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915 MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400 kHz, the transmitted signal bandwidth should be maximum 400 kHz – 2·37 kHz, which is 326 kHz. The CC1110Fx/CC1111Fx supports channel filter bandwidths shown in Table 63 and Table 64 respectively. MDMCFG4. CHANBW_M 00 01 10 11 MDMCFG4.CHANBW_E 00 812 650 541 464 01 406 325 270 232 10 203 162 135 116 11 102 81 68 58 Table 63: Channel Filter Bandwidths [kHz] (assuming fref = 26 MHz) MDMCFG4. CHANBW_M 00 01 10 11 MDMCFG4.CHANBW_E 00 750 600 500 429 01 375 300 250 214 10 188 150 125 107 11 94 75 63 54 Table 64: Channel Filter Bandwidths [kHz] (assuming fref = 24 MHz) 14.7 Demodulator, Symbol Synchronizer, and Data Decision gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after the sync word has been found. 14.7.2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 14.5 on page 190. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate. 14.7.3 Byte Synchronization Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet by the modulator in transmit mode.The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 14.10.1). The sync word detector correlates against the userconfigured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is CC1110Fx/CC1111Fx contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see section 14.10.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 14.7.1 Frequency Offset Compensation When using 2-FSK, GFSK, or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data. This value is available in the FREQEST status register. Writing the value from FREQEST into FSCTRL0.FREQOFF the frequency synthesizer is automatically adjusted according to the estimated frequency offset. The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMIT configuration register. If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm may drift to the boundaries when trying to track noise. The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the SWRS033E Page 191 of 239 CC1110Fx / CC1111Fx configured through the SYNC1 and SYNC0 registers and is sent MSB first. In order to make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for 14.8 Packet Handling Hardware Support The CC1110Fx/CC1111Fx has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet: • A programmable number of preamble bytes • A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word. • A CRC checksum computed over the data field The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes. In addition, the following can be implemented on the data field and the optional 2-byte CRC checksum: • Whitening of the data with a PN9 sequence. • Forward error correction by the use of interleaving and coding of the data (convolutional coding). In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled): • • • • • Preamble detection Sync word detection CRC computation and CRC check One byte address check Packet length check (length byte checked against a programmable maximum length) • De-whitening • De-interleaving and decoding Optionally, two status bytes (see Table 65 and Table 66) with RSSI value, Link Quality Indication, and CRC status can be appended to the received packet. Bit 7 Bit 7:0 Field Name RSSI Description RSSI value the preamble quality must be exceeded in order for a detected sync word to be accepted. See Section 14.10.2 on page 196 for more details. Table 65: Received Packet Status Byte 1 (first byte appended after the data) Field name CRC_OK Description 1: CRC for received data OK (or CRC disabled) 0: CRC error in received data 6:0 LQI The Link Quality Indicator estimates how easily a received signal can be demodulated Table 66: Received Packet Status Byte 2 (second byte appended after the data) Note that register fields that control the packet handling features should only be altered when CC1110Fx/CC1111Fx is in the IDLE state. 14.8.1 Data Whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies). Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening the data in the receiver. With CC1110Fx/CC1111Fx, this can be done automatically by setting PKTCTRL0.WHITE_DATA=1. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted as shown in Figure 49. At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver. The PN9 sequence is reset to all 1’s. Data whitening can only be used when PKTCTRL0.CC2400_EN=0 (default). SWRS033E Page 192 of 239 CC1110Fx / CC1111Fx Figure 49: Data Whitening in TX Mode 14.8.2 Packet Format The format of the data packet can be configured and consists of the following items: • Preamble • Synchronization word Optional data whitening Optionally FEC encoded/decoded Optional CRC-16 calculation Address field Length field Sync word CRC-16 • Length byte or constant programmable packet length • Optional Address byte • Payload • Optional 2 byte CRC Legend: Inserted automatically in TX, processed and removed in RX. Optional user-provided fields processed in TX, processed but not removed in RX. Unprocessed user data (apart from FEC and/or whitening) Preamble bits (1010...1010) Data field 8 x n bits 16/32 bits 8 bits 8 bits 8 x n bits 16 bits Figure 50: Packet Format The preamble pattern is an alternating sequence of ones and zeros (101010101…). The minimum length of the preamble is programmable through the NUM_PREAMBLE field in the MDMCFG1 register. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes have been transmitted, the modulator will send the sync word, and then data from the RFD register. If no data has been written to the RFD register when the radio is done transmitting the programmed number of preamble bytes, the modulator will continue to send preamble bytes until the first byte is written to RFD. It will then send the sync word followed by the data written to RFD. The synch. word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using MDMCFG2.SYNC_MODE set to 3 or 7. The sync word will then be repeated twice. CC1110Fx/CC1111Fx supports both fixed packet length protocols and variable packet length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and Page 193 of 239 SWRS033E CC1110Fx / CC1111Fx the optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. 14.8.3 Packet Filtering in Receive Mode byte (optionally 4-byte) sync word and then the content of the RFD register. If CRC is enabled, the checksum is calculated over all the data pulled from the RFD register and the result is sent as two extra bytes following the payload data. If fewer bytes are written to the RFD registers than what the radio expects the radio will enter TX_UNDERFLOW state and the RFIF.IRQ_TXUNF flag will be set together with RFIF.IRQ_DONE. An SIDLE strobe needs to be issued to return to IDLE state. If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1. If FEC/Interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is enabled by setting MDMCFG1.FEC_EN=1. 14.8.5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronism and will receive the first payload byte. If FEC/Interleaving is enabled, the FEC decoder will start to decode the first payload byte. The interleaver will de-scramble the bits before any other processing is done to the data. If whitening is enabled, the data will be dewhitened at this stage. When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum. At the end of the payload, the packet handler will optionally write two extra packet status bytes that contain CRC status, link quality indication and RSSI value. If a byte is received in the RFD register, and it is not read before the next byte is received, the CC2500 supports two different types of packetfiltering: address filtering and maximum length filtering. 14.8.3.1 Address Filtering Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 or both 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is accepted and the RFTXRXIF flag is asserted and a DMA trigger is generated. If the address match fails, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). The RFIF.IRQ_DONE flag will be asserted but the DMA will not be triggered. 14.8.3.2 Maximum Length Filtering In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). The RFIF.IRQ_DONE flag will be asserted but the DMA will not be triggered. 14.8.4 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into RFD. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to RFD is interpreted as the destination address, if this feature is enabled in the device that receives the packet. The modulator will first send the programmed number of preamble bytes. If data has been written to RFD, the modulator will send the two- SWRS033E Page 194 of 239 CC1110Fx / CC1111Fx radio will enter RX_OVERFLOW state and the RFIF.IRQ_RXOVF flag will be set together 14.9 Modulation Formats with RFIF.IRQ_DONE. An SIDLE strobe needs to be issued to return to IDLE state. CC1110Fx/CC1111Fx supports frequency and phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Manchester encoding is not supported at the same time as using the FEC/Interleaver option. 14.9.1 Frequency Shift Keying 2-FSK can optionally be shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by: The MSK modulation format implemented in CC1110Fx/CC1111Fx inverts the sync word and data compared to e.g. signal generators. 14.9.3 Amplitude Modulation CC1110Fx/CC1111Fx supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift Keying (ASK). OOK modulation simply turns on or off the PA to modulate 1 and 0 respectively. The CC1110Fx/CC1111Fx allows programming of the ASK variant supported by the modulation depth (the difference between 1 and 0), and shaping of the pulse amplitude. Pulse shaping will produce a more bandwidth constrained output spectrum. f dev = f ref 217 ⋅ (8 + DEVIATION _ M ) ⋅ 2 DEVIATION _ E The symbol encoding is shown in Table 67. Format 2-FSK/GFSK Symbol ‘0’ ‘1’ Coding – Deviation + Deviation Table 67: Symbol Encoding for 2-FSK/GFSK Modulation 14.9.2 Minimum Shift Keying When using MSK19, the complete transmission (preamble, sync word, and payload) will be MSK modulated. Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol. 19 Identical to offset QPSK with half-sine shaping (data coding may differ) SWRS033E Page 195 of 239 CC1110Fx / CC1111Fx 14.10 Received Signal Qualifiers and Link Quality Information CC1110Fx/CC1111Fx has several qualifiers that can be used to increase the likelihood that a valid sync word is detected. 14.10.1 Sync Word Qualifier If sync word detection in RX is enabled in register MDMCFG2 the CC1110Fx/CC1111Fx will not start writing received data to the RFD register and perform the packet filtering described in Section 14.8.3 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table 68. Carrier sense in Table 68 is described in Section 14.10.4. MDMCFG2. SYNC_MODE 000 001 010 011 100 101 110 111 No preamble/sync 15/16 sync word bits detected 16/16 sync word bits detected 30/32 sync word bits detected No preamble/sync, carrier sense above threshold 15/16 + carrier sense above threshold 16/16 + carrier sense above threshold 30/32 + carrier sense above threshold Sync Word Qualifier Mode A “Preamble Quality Reached” signal can be observed on P1_5, P1_6, or P1_7 by setting IOCFGx.GDOx_CFG=1000. It is also possible to determine if preamble quality is reached by checking the PQT_REACHED bit in the PKTSTATUS register. This signal / bit asserts when the received signal exceeds the PQT. 14.10.3 RSSI The RSSI value is an estimate of the signal level in the chosen channel. This value is based on the current gain setting in the RX chain and the measured signal level in the channel. In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state. The RSSI value is in dBm with ½ dB resolution. The RSSI update rate, fRSSI, depends on the receiver filter bandwidth (BWchannel defined in Section 14.6) and AGCCTRL0.FILTER_LENGTH. f RSSI = 2 ⋅ BWchannel 8 ⋅ 2 FILTER _ LENGTH Table 68: Sync Word Qualifier mode 14.10.2 Preamble Quality Threshold (PQT) The Preamble Quality Threshold (PQT) syncword qualifier adds the requirement that the received sync word must be preceded with a preamble with a quality above a programmed threshold. Another use of the preamble quality threshold is as a qualifier for the optional RX termination timer. See section 14.12.3 on page 203 for details. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. The threshold is configured with the register field PKTCTRL1.PQT. A threshold of 4·PQT for this counter is used to gate sync word detection. By setting the value to zero, the preamble quality qualifier of the sync word is disabled. If PKTCTRL1.APPEND_STATUS is enabled the RSSI value at sync word detection is automatically added to the first byte appended after the data payload. The RSSI value read from the RSSI status register is a 2’s complement number. The following procedure can be used to convert the RSSI reading to an absolute power level (RSSI_dBm). 1) Read the RSSI status register 2) Convert the reading from a hexadecimal number to a decimal number (RSSI_dec) 3) If RSSI_dec ≥ 128 then RSSI_dBm = (RSSI_dec - 256)/2 – RSSI_offset 4) Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 – RSSI_offset Table 69 provides typical values for the RSSI_offset. Figure 51 and Figure 52 shows typical plots of RSSI readings as a function of input power level for different data rates. SWRS033E Page 196 of 239 CC1110Fx / CC1111Fx Data rate [kBaud] 1.2 38.4 250 RSSI_offset [dB], 315 MHz 74 73 74 RSSI_offset [dB], 433 MHz 75 74 73 RSSI_offset [dB], 868 MHz 73 73 77 Table 69: Typical RSSI_offset Values 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 RSSI Readout [dBm] Input Power [dBm] 1.2 kBaud 38.4 kBaud 250 kBaud Figure 51: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz 0 -10 -20 -30 RSSI Readout [dBm] -40 -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBaud 38.4 kBaud 250 kBaud Figure 52: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz 14.10.4 Carrier Sense (CS) The Carrier Sense (CS) flag is used as a sync word qualifier and for CCA. The CS flag can be set based on two conditions, which can be individually adjusted: • CS is asserted when the RSSI is above a programmable absolute threshold, and de-asserted when RSSI is below the same threshold (with hysteresis). SWRS033E Page 197 of 239 CC1110Fx / CC1111Fx • CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and de-asserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. Carrier Sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. The signal can also be observed on P1_5, P1_6, or P1_7 by setting IOCFGx.GDOx_CFG=1110 and in the status register bit PKTSTATUS.CS. Other uses of Carrier Sense include the TX-ifCCA function (see Section 14.10.7 on page 198) and the optional fast RX termination (see Section 14.12.3 on page 203). MAX_LNA_GAIN[2:0] MAX_DVGA_GAIN[1:0] 00 000 MAX_LNA_GAIN[2:0] 001 010 011 100 101 110 111 -99 -97 -93.5 -91.5 -90.5 -88 -84.5 -82.5 01 -93 -90.5 -87 -86 -84 -82.5 -78.5 -76 10 -87 -85 -82 -80 -78 -76 -73 -70 11 -81.5 -78.5 -76 -74 -72.5 -70 -67 -64 Table 70: Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 2.4 kBaud MAX_DVGA_GAIN[1:0] 00 000 001 010 011 100 101 110 111 -96 -94.5 -92.5 -91 -87.5 -85 -83 -78 01 -90 -89 -87 -85 -82 -79.5 -76.5 -72 10 -84 -83 -81 -78.5 -76 -73.5 -70.5 -66 11 -78.5 -77.5 -75 -73 -70 -67.5 -65 -60 CS can be used to avoid interference from other RF sources in the ISM bands. 14.10.5 CS Absolute Threshold The absolute threshold related to the RSSI value depends on the following register fields: • • • • AGCCTRL2.MAX_LNA_GAIN AGCCTRL2.MAX_DVGA_GAIN AGCCTRL1.CARRIER_SENSE_ABS_THR AGCCTRL2.MAGN_TARGET For a given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN setting the absolute threshold can be adjusted ±7 dB in steps of 1 dB using CARRIER_SENSE_ABS_THR. The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroom for blockers, and therefore close-in selectivity. It is strongly recommended to use SmartRF® Studio [9] to generate the correct MAGN_TARGET setting. Table 70 and Table 71 show the typical RSSI readout values at the CS threshold at 2.4 kBaud and 250 kBaud data rate respectively. The default CARRIER_SENSE_ABS_THR=0 (0 dB) and MAGN_TARGET=11 (33 dB) have been used. For other data rates the user must generate similar tables to find the CS absolute threshold. Table 71: Typical RSSI Value in dBm at CS Threshold with Default MAGN_TARGET at 250 kBaud If the threshold is set high, i.e. only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reduce power consumption in the receiver front end, since the highest gain settings are avoided. 14.10.6 CS Relative Threshold The relative threshold detects sudden changes in the measured signal level. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, and to select threshold of 6 dB, 10 dB or 14 dB RSSI change 14.10.7 Clear Channel Assessment (CCA) The Clear Channel Assessment CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on SWRS033E Page 198 of 239 CC1110Fx / CC1111Fx P1_5, P1_6, or P1_7 IOCFGx.GDOx_CFG=1001. by setting MCSM1.CCA_MODE selects the mode to use when determining CCA. When the STX or SFSTXON command strobe is given while CC1110Fx/CC1111Fx is in the RX state, the TX or FSTXON state is only entered if the clear channel requirements are fulfilled. The chip will otherwise remain in RX (if the channel becomes available, the radio will not enter TX or FSTXON state before a new strobe command is being issued). This feature is called TX-if-CCA. Note that when using this function the register TEST1 on page 222 should be set to 0x31. Four CCA requirements can be programmed: • Always (CCA disabled, always goes to TX) • If RSSI is below threshold 14.11 Forward Error Correction with Interleaving 14.11.1 Forward Error Correction (FEC) generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the m-bit window). The convolutional coder is a rate 1/2 code with a constraint length of m=4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. I.e. to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate. This will require a higher receiver bandwidth, and thus reduce sensitivity. In other words, the improved reception by using FEC and the degraded sensitivity from a higher receiver bandwidth will be counteracting factors. 14.11.2 Interleaving Data received through radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. • Unless currently receiving a packet • Both the above (RSSI below threshold and not currently receiving a packet) 14.10.8 Link Quality Indicator (LQI) The Link Quality Indicator is a metric of the current quality of the received signal. If PKTCTRL1.APPEND_STATUS is enabled, the value is automatically added to the last byte appended after the payload. The value can also be read from the LQI status register. The LQI gives an estimate of how easily a received signal can be demodulated by accumulating the magnitude of the error between ideal constellations and the received signal over the 64 symbols immediately following the sync word. LQI is best used as a relative measurement of the link quality (a high value indicates a better link than what a low value does), since the value is dependent on the modulation format. CC1110Fx/CC1111Fx has built in support for Forward Error Correction (FEC). To enable this option, set MDMCFG1.FEC_EN to 1. FEC is only supported in fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors. The use of FEC allows correct reception at a lower SNR, thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by: PER = 1 − (1 − BER) packet _ length , a lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors). The FEC scheme adopted for CC1110Fx/CC1111Fx is convolutional coding, in which n bits are CC1110Fx/CC1111Fx employs matrix interleaving, which is illustrated in Figure 53. The on-chip interleaving and de-interleaving buffers are 4 x 4 matrices. In the transmitter, the data bits from the rate ½ convolutional coder are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix. In the receiver, the Page 199 of 239 SWRS033E CC1110Fx / CC1111Fx received symbols are written into the rows of the matrix, whereas the data passed onto the convolutional decoder is read from the columns of the matrix. When FEC and interleaving is used at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RFD data register. When FEC and interleaving is used the minimum data payload is 2 bytes. Interleaver Write buffer Interleaver Read buffer Packet Engine FEC Encoder Modulator Interleaver Write buffer Interleaver Read buffer Demodulator FEC Decoder Packet Engine Figure 53: General Principle of Matrix Interleaving 14.12 Radio Control CC1110Fx/CC1111Fx has a built-in state machine that is used to switch between different operation states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. A simplified state diagram, together with typical usage and current consumption, is shown in Figure 47 on page 186. The complete radio control state diagram is shown in Figure 54. The numbers refer to the state number readable in the MARCSTATE status register. This register is primarily for test purposes. SWRS033E Page 200 of 239 CC1110Fx / CC1111Fx Figure 54: Complete Radio Control State Diagram 14.12.1 Active Modes The radio has two active modes: receive and transmit. These modes are activated directly by writing the SRX and STX command strobes to the RFST register. The frequency synthesizer must be calibrated regularly. CC1110Fx/CC1111Fx has one manual calibration option (using the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL setting: • Calibrate when going from IDLE to either RX or TX (or FSTXON) • Calibrate when going from either RX or TX to IDLE automatically • Calibrate every fourth time when going from either RX or TX to IDLE automatically If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibration takes a constant number of XOSC cycles (see Table 72 for timing details). Page 201 of 239 SWRS033E CC1110Fx / CC1111Fx When RX is activated, the chip will remain in receive mode until a packet is successfully received or the RX termination timer expires (see Section 14.12.3). Note: the probability that a false sync word is detected can be reduced by using PQT, CS, maximum sync word length, and sync word qualifier mode as describe in Section 14.10.1. After a packet is successfully received the radio controller will then go to the state indicated by the MCSM1.RXOFF_MODE setting. The possible destinations are: • IDLE • FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX. • TX: Start sending preambles • RX: Start search for a new packet Similarly, when TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are the same as for RX. It is possible to change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and an SRX strobe is written to the RFST register, the current transmission will be ended and the transition to RX will be done. If the radio controller is in RX when the STX or SFSTXON command strobes are used and MCSM1.CCA_MODE ≠ 00, the TX-if-CCA function will be used. Note that for TX-if-CCA Transition Time Description Idle to RX, no calibration Idle to RX, with calibration Idle to TX/FSTXON, no calibration Idle to TX/FSTXON, with calibration TX to RX switch RX to TX switch RX or TX to IDLE, no calibration RX or TX to IDLE, with calibration Manual calibration function the register TEST1 on page 222 should be set to 0x31. If the channel is not clear, the chip will remain in RX. For more details on clear channel assessment see Section 14.10.7 on page 198 for details. The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. 14.12.2 Timing The radio controller controls most timing in CC1110Fx/CC1111Fx, such as synthesizer calibration, PLL lock time and RX/TX turnaround times. Timing from IDLE to RX and IDLE to TX is constant, dependent on the auto calibration setting. RX/TX and TX/RX turnaround times are constant. The calibration time is constant 18739 clock periods (fRef). Table 72 shows the timing for key state transitions. Power on time and XOSC start-up times are variable, but within the limits stated in Table 11 and Table 12 Note that in a frequency hopping spread spectrum or a multi-channel protocol it is possible to reduce the calibration time from 721 µs to approximately 150 µs. This is explained in Section 14.18.2. fRef Periods 2298 ~21037 2298 ~21037 560 250 2 ~18739 ~18739 fRef = 26 MHz fRef = 24 MHz 88.4 µs 809 µs 88.4 µs 809 µs 21.5 µs 9.6 µs 0.1 µs 721 µs 721 µs 95.8 µs 876.5 µs 95.8 µs 876.5 µs 23.3 µs 10.4 µs 0.1 µs 780.8 µs 780.8 µs Table 72: State Transition Timing SWRS033E Page 202 of 239 CC1110Fx / CC1111Fx 14.12.3 RX Termination Timer CC1110Fx/CC1111Fx has optional functions for automatic termination of RX after a programmable time. The termination timer starts when in RX state. The timeout is programmable with the MCSM2.RX_TIME setting. When the timer expires, the radio controller will check the condition for staying in RX; if the condition is not met, RX will terminate. The programmable conditions are: • MCSM2.RX_TIME_QUAL=0: Continue receive if sync word has been found • MCSM2.RX_TIME_QUAL=1: Continue receive if sync word has been found or preamble quality is above threshold (PQT) 14.13 Frequency Programming The If the system can expect the transmission to have started when enabling the receiver, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section 14.10.4 on page 197 for details on Carrier Sense. For ASK/OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in ASK/OOK mode when the distance between “1” symbols is 8 or less. If RX terminates due to no carrier sense when the MCSM2.RX_TIME_RSSI function is used, or if no sync word was found when using the MCSM2.RX_TIME timeout function, the chip will always go back to IDLE. CC1110Fx/CC1111Fx is designed to minimize the frequency programming in programming needed in a channel-oriented system. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by: f carrier = f ref 216 ⋅ FREQ + CHAN ⋅ ( 256 + CHANSPC _ M ) ⋅ 2 CHANSPC _ E − 2 ( ( )) With a reference frequency, fRef, equal to 26 MHz, the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing one solution is to use 333 kHz channel spacing and select each third channel in CHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is given by: Note that the SmartRF® Studio software [9] automatically calculates the optimum register setting based on channel spacing and channel filter bandwidth. If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state. f IF = 14.14 VCO f ref ⋅ FREQ _ IF 210 The VCO is completely integrated on-chip. 14.14.1 VCO and PLL Self-Calibration The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, CC1110Fx/CC1111Fx includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of fRef periods for completing the PLL calibration is given in Table 72 on page 202. Page 203 of 239 SWRS033E CC1110Fx / CC1111Fx The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL 14.15 Output Power Programming The RF output power level from the device has two levels of programmability, as illustrated in Figure 55. Firstly, the PA_TABLE7PA_TABLE0 registers can hold up to eight user selected output power settings. Secondly, the 3-bit FREND0.PA_POWER value selects the PA_TABLE7-PA_TABLE0 register to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK modulation shaping. All the PA power settings in the PA_TABLE7-PA_TABLE0 registers, from index 0 up to the index set by FREND0.PA_POWER, values are used. The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWER to zero and then program the desired output power to PA_TABLE0 register. If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively, i.e. PA_TABLE0 and PA_TABLE1. Table 73 contains recommended PA_TABLE settings for various output levels and frequency bands. Using PA settings from 0x68 to 0x6F is not recommended. command strobe is activated in the IDLE mode. Note that the calibration values are maintained in power-down modes PM1/2/3, so the calibration is still valid after waking up from these power-down modes (unless supply voltage or temperature has changed significantly). 315 MHz Output Power [dBm] -30 -20 -15 -10 -5 0 5 7 10 Setting 0x12 0x0D 0x1C 0x34 0x2B 0x51 0x85 0xCB 0xC2 Current Consumption, Typ. [mA] 14 15 16 17 19 19 22 25 31 Setting 0x12 0x0E 0x1D 0x34 0x2C 0x60 0x84 0xC8 0xC0 433 MHz Current Consumption, Typ. [mA] 15 16 16 18 20 20 23 28 33 Setting 0x03 0x0E 0x1E 0x27 0x8F 0x50 0x84 0xCB 0xC2 868 MHz Current Consumption, Typ. [mA] 16 17 17 19 19 21 25 31 36 Setting 0x03 0x0D 0x1D 0x26 0x57 0x8E 0x83 0xC7 0xC0 915 MHz Current Consumption, Typ. [mA] 16 16 17 18 18 21 25 31 36 Table 73: Optimum PA_TABLE Settings for Various Output Power Levels and Frequency Bands 14.16 Shaping and PA Ramping With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate. The counter saturates at FREND0.PA_POWER and 0 respectively. This counter value can be viewed as an index for a lookup table in the power table (see Figure 55). Thus, in order to utilize the whole table, FREND0.PA_POWER should be 7 when ASK is active. The shaping of the ASK signal is dependent on the configuration of PA_TABLE7-PA_TABLE0 registers. Figure 56 shows some examples of ASK shaping. SWRS033E Page 204 of 239 CC1110Fx / CC1111Fx PA_TABLE7[7:0] PA_TABLE6[7:0] PA_TABLE5[7:0] PA_TABLE4[7:0] PA_TABLE3[7:0] PA_TABLE2[7:0] PA_TABLE1[7:0] PA_TABLE0[7:0] Index into PA_TABLE Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for ASK/OOK modulation. The PA uses this setting. e.g 6 PA_POWER[2:0] in FREND0 register The SmartRF® Studio software should be used to obtain optimum PA_TABLE settings for various output powers. Figure 55: PA_POWER and PA_TABLE Output Power PA_TABLE7 PA_TABLE6 PA_TABLE5 PA_TABLE4 PA_TABLE3 PA_TABLE2 PA_TABLE1 PA_TABLE0 1 0 0 1 0 1 1 0 Time Bit Sequence FREND0.PA_POWER = 3 FREND0.PA_POWER = 7 Figure 56: Shaping of ASK Signal SWRS033E Page 205 of 239 CC1110Fx / CC1111Fx 14.17 Selectivity Figure 57 to Figure 59 show the typical selectivity performance (adjacent and alternate rejection). 50.0 40.0 30.0 Selectivity [dB] 20.0 10.0 0.0 -0.5 -10.0 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 -20.0 Frequency offset [MHz] Figure 57: Typical Selectivity at 1.2 kBaud @ 868 MHz. IF Frequency is 152 kHz. MDMCFG2.DEM_DCFILT_OFF=0 50.0 40.0 30.0 Selectivity [dB] 20.0 10.0 0.0 -1.0 -10.0 -0.8 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 0.8 1.0 -20.0 Frequency offset [MHz] Figure 58: Typical Selectivity at 38.4 kBaud@ 868 MHz. IF Frequency is 152 kHz. MDMCFG2.DEM_DCFILT_OFF=0 50.0 40.0 30.0 Selectivity [dB] 20.0 10.0 0.0 -3.00 -10.0 -2.25 1.50 -1.00 -0.75 0.00 0.75 1.00 1.50 2.25 3.00 -20.0 Frequency offset [MHz] Figure 59: Typical Selectivity at 250 kBaud @ 868 MHz. IF Frequency is 304 kHz. MDMCFG2.DEM_DCFILT_OFF=0 14.18 System considerations and Guidelines SWRS033E Page 206 of 239 CC1110Fx / CC1111Fx 14.18.1 SRD/ISM Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz or 915 MHz frequency bands. The CC1110Fx/CC1111Fx is specifically designed for such use with its 300 - 348 MHz, 391 - 464 MHz, and 782 - 928 MHz operating ranges. The most important regulations when using the CC1110Fx/CC1111Fx in the 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 part 15 (USA). A summary of the most important aspects of these regulations can be found in [10] or [11]. Please note that compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to ensure that the system complies with regulations. 14.18.2 Frequency Hopping and Multi-Channel Systems The 433 MHz, 868 MHz, or 915 MHz are shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading. Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC1110Fx/CC1111Fx. There are 3 ways of obtaining the calibration data from the chip: 1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 µs and the blanking interval between each frequency hop is then approximately 810 µs when fRef is 26 MHz. When fRef is 24 MHz, these numbers are 780 µs and 875 µs respectively. 2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in memory. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. The PLL turn on time is approximately 90 µs when fRef is 26 MHz and 95 µs when fRef is 24 MHz. The blanking interval between each frequency hop is then approximately equal to the PLL turn on time. The VCO current calibration result is available in FSCAL2 and is not dependent on the RF frequency. Neither is the charge pump current calibration result available in FSCAL3. The same value can therefore be used for all frequencies. 3) Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4] strobe SRX (or STX) with MCSM0.FS_AUTOCAL=1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 µs to approximately 150 µs when fRef is 26 MHz and from 780 µs to 163 µs when fRef is 24 MHz. The blanking interval between each frequency hop is then approximately 240 µs us and 260 µs respectively. There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3) gives approximately 570 µs smaller blanking interval than solution 1 when fRef is 24 MHz and approximately 615 µs smaller blanking interval than solution 1 when fRef is 24 MHz ). 14.18.3 Wideband Modulation Spread Spectrum not Using Digital modulation systems under FCC part 15.247 includes 2-FSK and GFSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band. Pleas refer to DN006 [12] for further details conserning wideband modulation and CC1110Fx/CC1111Fx. Operating with high frequency separation, the CC1110Fx/CC1111Fx is suited for systems targeting compliance with digital modulation systems as defined by FCC part 15.247. An external power amplifier is needed to increase the output above +10 dBm. 14.18.4 Data Burst Transmissions The CC1110Fx/CC1111Fx high maximum opens data rate of up for burst Page 207 of 239 SWRS033E CC1110Fx / CC1111Fx transmissions. A low average data rate link (e.g. 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in active mode, and hence also reduce the average current consumption significantly. Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequency range. Note that sensitivity and thus transmission range is reduced in high data rate bursts compared to lower data rates. 14.18.5 Crystal Drift Compensation The CC1110Fx/CC1111Fx has a very fine frequency resolution (see Table 16). This feature can be used to compensate for frequency offset and drift. The frequency offset between an ‘external’ transmitter and the receiver is measured in the CC1110Fx/CC1111Fx and can be read back from the FREQEST status register as described in Section 14.7.1. The measured frequency offset can be used to calibrate the frequency using the ‘external’ transmitter as the reference. That is, the received signal of the device will match the receiver’s channel filter better. In the same way the centre frequency of the transmitted signal will match the ‘external’ transmitter’s signal. 14.18.6 Spectrum Efficient Modulation spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In ‘true’ 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift ‘softer’, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK. 14.18.7 Low Cost Systems A HC-49 type SMD crystal is used in the CC1110EM reference design [1]. Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used. 14.18.8 Battery Operated Systems In low power applications, PM2 or PM3 should be used when the CC1110Fx/CC1111Fx is not active. The Sleep Timer can be used in PM2. 14.18.9 Increasing Output Power In some applications it may be necessary to extend the link range. Adding an external power amplifier is the most effective way of doing this. The power amplifier should be inserted between the antenna and the balun, and two T/R switches are needed to disconnect the PA in RX mode. See Figure 60. CC1110Fx/CC1111Fx also has the possibility to use Gaussian shaped Antenna 2-FSK (GFSK). This Filter P A Balun CC1110Fx / CC1111Fx T/R switch T/R switch Figure 60: Block Diagram of CC1110Fx/CC1111Fx Usage with External Power Amplifier SWRS033E Page 208 of 239 CC1110Fx / CC1111Fx 14.19 Radio Registers This section describes all RF registers used for control and status for the radio. 0xDF2F: IOCFG2 – Radio Test Signal Configuration (P1_7) Bit 7 6 5:0 GDO2_INV GDO2_CFG[5:0] Field Name Reset 0 000000 R/W R0 R/W R/W Description Not used Invert output, i.e. select active low (1) / high (0) Debug output on P1_7 pin. See Table 74 for a description of internal signals which can be output on this pin for debug purpose 0xDF30: IOCFG1 – Radio Test Signal Configuration (P1_6) Bit 7 Field Name GDO_DS Reset 0 R/W R/W Description Enable / disable drive strength enhancement for all port outputs. To be used below 2.6 V 0 1 6 GDO1_INV 0 R/W Disable Enable Invert output 0 1 Active high Active low 5:0 GDO1_CFG[5:0] 000000 R/W Debug output on P1_6 pin. See Table 74 for a description of internal signals which can be output on this pin for debug purpose 0xDF31: IOCFG0 – Radio Test Signal Configuration (P1_5) Bit 7 6 5:0 GDO0_INV GDO0_CFG[5:0] Field Name Reset 0 000000 R/W R0 R/W R/W Description Not used Invert output, i.e. select active low (1) / high (0) Debug output on P1_5 pin. See Table 74 for a description of internal signals which can be output on this pin for debug purpose. 0xDF00: SYNC1 – Sync Word, High Byte Bit 7:0 Field Name SYNC[15:8] Reset 0xD3 R/W R/W Description 8 MSB of 16-bit sync word 0xDF01: SYNC0 – Sync Word, Low Byte Bit 7:0 Field Name SYNC[7:0] Reset 0x91 R/W R/W Description 8 LSB of 16-bit sync word 0xDF02: PKTLEN – Packet Length Bit 7:0 Field Name PACKET_LENGTH Reset 0xFF R/W R/W Description Indicates the packet length when fixed length packets are enabled. If variable length packets are used, this value indicates the maximum length packets allowed SWRS033E Page 209 of 239 CC1110Fx / CC1111Fx 0xDF03: PKTCTRL1 – Packet Automation Control Bit 7:5 Field Name PQT[2:0] Reset 000 R/W R/W Description Preamble quality estimator threshold. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. A threshold of 4·PQT for this counter is used to gate sync word detection. When PQT=0 a sync word is always accepted 4:3 2 APPEND_STATUS 1 R0 R/W Not used When enabled, two status bytes will be appended to the payload of the packet. The status bytes contain RSSI and LQI values, as well as the CRC OK flag Controls address check configuration of received packages. 00 01 10 11 No address check Address check, no broadcast Address check, 0 (0x00) broadcast Address check, 0 (0x00) and 255 (0xFF) broadcast 1:0 ADR_CHK[1:0] 00 R/W 0xDF04: PKTCTRL0 – Packet Automation Control Bit 7 6 WHITE_DATA Field Name Reset 1 R/W R0 R/W Description Not used Whitening enable. Data whitening can only be used when PKTCTRL0.CC2400_EN=0 (default). 0 1 5:4 PKT_FORMAT[1:0] 00 R/W Disabled Enabled Packet format of RX and TX data 00 01 10 11 Normal mode Reserved Random TX mode; sends random data using PN9 generator. Used for test. Works as normal mode, setting 00, in RX. Reserved 3 CC2400_EN 0 R/W CC2400 support enable. Use same CRC implementation as CC2400. The CC2400 CRC can only be used if PKTCTRL0.WHITE_DATA=0 0 1 Disable Enable 2 CRC_EN 1 R/W CRC calculation in TX and CRC check in RX enable 0 1 Disable Enable 1:0 LENGTH_CONFIG[1:0] 01 R/W Packet Length Configuration 00 01 10 11 Fixed packet length mode. Length configured in PKTLEN register Variable packet length mode. Packet length configured by the first byte after sync word Reserved Reserved SWRS033E Page 210 of 239 CC1110Fx / CC1111Fx 0xDF05: ADDR – Device Address Bit 7:0 Field Name DEVICE_ADDR[7:0] Reset 0x00 R/W R/W Description Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF). 0xDF06: CHANNR – Channel Number Bit 7:0 Field Name CHAN[7:0] Reset 0x00 R/W R/W Description The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency. 0xDF07: FSCTRL1 – Frequency Synthesizer Control Bit 7:6 5 4:0 FREQ_IF[4:0] Field Name Reset 0 01111 R/W R0 R/W R/W Description Not used Reserved The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. f IF = f ref 210 ⋅ FREQ _ IF The default value gives an IF frequency of 381 kHz when fRef = 26 MHz and 352 kHz when fRef = 24 MHz. 0xDF08: FSCTRL0 – Frequency Synthesizer Control Bit 7:0 Field Name FREQOFF[7:0] Reset 0x00 R/W R/W Description Frequency offset added to the base frequency before being used by the FS. (2’s complement). Resolution is fRef /2 14 Range is ±186 kHz to ±209 kHz for CC1110Fx and ±186 kHz for CC1111Fx 0xDF09: FREQ2 – Frequency Control Word, High Byte Bit 7:6 5:0 Field Name FREQ[23:22] FREQ[21:16] Reset 01 11110 R/W R R/W Description FREQ[23:22] FREQ[23:0] is the base frequency for the frequency synthesizer in 16 increments of fRef /2 . f carrier = f ref 216 ⋅ FREQ[23 : 0] 0xDF0A: FREQ1 – Frequency Control Word, Middle Byte Bit 7:0 Field Name FREQ[15:8] Reset 11000100 R/W R/W Description Ref. FREQ2 register 0xDF0B: FREQ0 – Frequency Control Word, Low Byte Bit 7:0 Field Name FREQ[7:0] Reset 11101100 R/W R/W Description Ref. FREQ2 register SWRS033E Page 211 of 239 CC1110Fx / CC1111Fx 0xDF0C: MDMCFG4 – Modem configuration Bit 7:6 5:4 Field Name CHANBW_E[1:0] CHANBW_M[1:0] Reset 10 00 R/W R/W R/W Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. Description BWchannel = f ref 8 ⋅ (4 + CHANBW _ M )·2 CHANBW _ E The default values give 203 kHz channel filter bandwidth when fRef = 26 MHz and 188 kHz when fRef = 24 MHz. 3:0 DRATE_E[3:0] 1100 R/W The exponent of the user specified symbol rate. 0xDF0D: MDMCFG3 – Modem Configuration Bit 7:0 Field Name DRATE_M[7:0] Reset 0x22 R/W R/W Description The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit th exponent. The 9 bit is a hidden ‘1’. The resulting data rate is: RDATA = (256 + DRATE _ M ) ⋅ 2 DRATE _ E ⋅ f 2 28 ref The default values give a data rate of 115.051 kBaud when fRef = 26 MHz and 106.201 kHz when fRef = 24 MHz. SWRS033E Page 212 of 239 CC1110Fx / CC1111Fx 0xDF0E: MDMCFG2 – Modem Configuration Bit 7 Field Name DEM_DCFILT_OFF Reset 0 R/W R/W Description Disable digital DC blocking filter before demodulator. The recommended IF frequency changes when the DC blocking is disabled. Please use SmartRF® Studio [9] to calculate correct register setting. 0 1 6:4 MOD_FORMAT[2:0] 000 R/W Enable Disable Better Sensitivity Current optimized. Only for data rates ≤ 250 kBaud The modulation format of the radio signal 000 001 010 011 100 101 110 111 2-FSK GFSK Reserved Reserved Reserved Reserved Reserved MSK 3 MANCHESTER_EN 0 R/W Manchester encoding/decoding enable 0 1 Disable Enable 2:0 SYNC_MODE[2:0] 010 R/W Sync-word qualifier mode. The values 000 and 100 disables preamble and sync word transmission in TX and preamble and sync word detection in RX. The values 001, 010, 101 and 110 enables 16-bit sync word transmission in TX and 16-bits sync word detection in RX. Only 15 of 16 bits need to match in RX when using setting 001 or 101. The values 011 and 111 enables repeated sync word transmission in TX and 32-bits sync word detection in RX (only 30 of 32 bits need to match). 000 001 010 011 100 101 110 111 No preamble/sync 15/16 sync word bits detected 16/16 sync word bits detected 30/32 sync word bits detected No preamble/sync, carrier-sense above threshold 15/16 + carrier-sense above threshold 16/16 + carrier-sense above threshold 30/32 + carrier-sense above threshold SWRS033E Page 213 of 239 CC1110Fx / CC1111Fx 0xDF0F: MDMCFG1 – Modem Configuration Bit 7 Field Name FEC_EN Reset 0 R/W R/W Description Enable Forward Error Correction (FEC) with interleaving for packet payload. FEC is only supported for fixed packet length mode, i.e. PKTCTRL0.LENGTH_CONFIG=0 0 1 6:4 NUM_PREAMBLE[2:0] 010 R/W Disable Enable Sets the minimum number of preamble bytes to be transmitted 000 001 010 011 100 101 110 111 2 3 4 6 8 12 16 24 3:2 1:0 CHANSPC_E[1:0] 10 R0 R/W Not used 2 bit exponent of channel spacing 0xDF10: MDMCFG0 – Modem Configuration Bit 7:0 Field Name CHANSPC_M[7:0] Reset 0xF8 R/W R/W Description 8-bit mantissa of channel spacing (initial 1 assumed). The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: ∆f CHANNEL = f ref 218 ⋅ (256 + CHANSPC _ M ) ⋅ 2 CHANSPC _ E The default values give 199.951 kHz channel spacing when fRef = 26 MHz and 184.570 kHz when fRef = 24 MHz. 0xDF11: DEVIATN – Modem Deviation Setting Bit 7 6:4 3 2:0 DEVIATION_M[2:0] DEVIATION_E[2:0] Field Name Reset 100 111 R/W R0 R/W R0 R/W Description Not used Deviation exponent Not used When MSK modulation is enabled: Sets fraction of symbol period used for phase change. Refer to the SmartRF® Studio software [9] for correct DEVIATN setting when using MSK. When 2-FSK/GFSK modulation is enabled: Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The resulting deviation is given by: f dev = f ref 2 17 ⋅ (8 + DEVIATION _ M ) ⋅ 2 DEVIATION _ E The default values give ±47.607kHz deviation when fRef = 26 MHz and 43.945 kHz when fRef = 24 MHz. SWRS033E Page 214 of 239 CC1110Fx / CC1111Fx 0xDF12: MCSM2 – Main Radio Control State Machine Configuration Bit 7:5 4 3 RX_TIME_RSSI RX_TIME_QUAL Field Name Reset 0 0 R/W R0 R/W R/W Description Not used Direct RX termination based on RSSI measurement (carrier sense). When the RX_TIME timer expires the chip stays in RX mode if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQT is reached when RX_TIME_QUAL=1. Timeout for sync word search in RX. The timeout is relative to the programmed tEvent0. 2:0 RX_TIME[2:0] 111 R/W The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and X is the reference frequency (fRef) in MHz: RX_TIME[2:0] 000 001 010 011 100 101 110 111 WOR_RES=0 3.6058 1.8029 0.9014 0.4507 0.2254 0.1127 0.0563 Until end of packet WOR_RES=1 18.0288 9.0144 4.5072 2.2536 1.1268 0.5634 0.2817 WOR_RES=2 32.4519 16.2260 8.1130 4.0565 2.0282 1.0141 0.5071 WOR_RES=3 46.8750 23.4375 11.7188 5.8594 2.9297 1.4648 0.7324 As an example, EVENT0 = 34666, WOR_RES = 0 and RX_TIME = 6 corresponds to 1.96 ms RX timeout 0xDF13: MCSM1 – Main Radio Control State Machine Configuration Bit 7:6 5:4 CCA_MODE[1:0] Field Name Reset 11 R/W R0 R/W Description Not used Selects CCA_MODE; Reflected in CCA signal 00 01 10 11 3:2 RXOFF_MODE[1:0] 00 R/W Always If RSSI below threshold Unless currently receiving a packet If RSSI below threshold unless currently receiving a packet Select what should happen (next state) when a packet has been received 00 01 10 11 IDLE FSTXON TX Stay in RX It is not possible to set RXOFF_MODE to be TX or FSTXON and at the same time use CCA. 1:0 TXOFF_MODE[1:0] 00 R/W Select what should happen (next state) when a packet has been sent (TX) 00 01 10 11 IDLE FSTXON Stay in TX (start sending preamble) RX SWRS033E Page 215 of 239 CC1110Fx / CC1111Fx 0xDF14: MCSM0 – Main Radio Control State Machine Configuration Bit 7:6 5:4 FS_AUTOCAL[1:0] Field Name Reset 00 R/W R0 R/W Description Not used Select calibration mode (when to calibrate) 00 01 10 11 3 2 1:0 CLOSE_IN_RX[1:0] 0 1 00 R/W R/W R/W Never (manually calibrate using SCAL strobe) When going from IDLE to RX or TX (or FSTXON) When going from RX or TX back to IDLE automatically Every 4th time when going from RX or TX to IDLE automatically Reserved. Refer to SmartRF® Studio software [9] for settings. Reserved. Refer to SmartRF® Studio software [9] for settings. Sets RX attenuation. Used in order to avoid saturation in RX when two or more chips are close (within ~3 m). RX attenuation, typical values: 00 01 10 11 0 dB 6 dB 12 dB 18 dB 0xDF15: FOCCFG – Frequency Offset Compensation Configuration Bit 7 6 5 FOC_BS_CS_GATE Field Name Reset 1 1 R/W R0 R/W R/W Description Not used Reserved. Always write 0 If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CARRIER_SENSE signal goes high. The frequency compensation loop gain to be used before a sync word is detected. 00 01 10 11 2 FOC_POST_K 1 R/W K 2K 3K 4K 4:3 FOC_PRE_K[1:0] 10 R/W The frequency compensation loop gain to be used after a sync word is detected. 0 1 Same as FOC_PRE_K K/2 1:0 FOC_LIMIT[1:0] 10 R/W The saturation point for the frequency offset compensation algorithm: 00 01 10 11 ±0 (no frequency offset compensation) ±BWCHAN / 8 ±BW CHAN / 4 ±BW CHAN / 2 SWRS033E Page 216 of 239 CC1110Fx / CC1111Fx 0xDF16: BSCFG – Bit Synchronization Configuration Bit 7:6 Field Name BS_PRE_KI[1:0] Reset 01 R/W R/W Description The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): 00 01 10 11 5:4 BS_PRE_KP[1:0] 10 R/W KI 2K I 3K I 4K I The clock recovery feedback loop proportional gain to be used before a sync word is detected 00 01 10 11 KP 2K P 3K P 4K P 3 BS_POST_KI 1 R/W The clock recovery feedback loop integral gain to be used after a sync word is detected. 0 1 Same as BS_PRE_KI K I /2 2 BS_POST_KP 1 R/W The clock recovery feedback loop proportional gain to be used after a sync word is detected. 0 1 Same as BS_PRE_KP KP 1:0 BS_LIMIT[1:0] 00 R/W The saturation point for the data rate offset compensation algorithm: 00 01 10 11 ±0 (No data rate offset compensation performed) ±3.125 % data rate offset ±6.25 % data rate offset ±12.5 % data rate offset SWRS033E Page 217 of 239 CC1110Fx / CC1111Fx 0xDF17: AGCCTRL2 – AGC Control Bit 7:6 Field Name MAX_DVGA_GAIN[1:0] Reset 00 R/W R/W Description Reduces the maximum allowable DVGA gain. 00 01 10 11 5:3 MAX_LNA_GAIN[2:0] 000 R/W All gain settings can be used The highest gain setting can not be used The 2 highest gain settings can not be used The 3 highest gain settings can not be used Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain. 000 001 010 011 100 101 110 111 Maximum possible LNA + LNA 2 gain Approx. 2.6 dB below maximum possible gain Approx. 6.1 dB below maximum possible gain Approx. 7.4 dB below maximum possible gain Approx. 9.2 dB below maximum possible gain Approx. 11.5 dB below maximum possible gain Approx. 14.6 dB below maximum possible gain Approx. 17.1 dB below maximum possible gain 2:0 MAGN_TARGET[2:0] 011 R/W These bits set the target value for the averaged amplitude from the digital channel filter (1 LSB = 0 dB). 000 001 010 011 100 101 110 111 24 dB 27 dB 30 dB 33 dB 36 dB 38 dB 40 dB 42 dB SWRS033E Page 218 of 239 CC1110Fx / CC1111Fx 0xDF18: AGCCTRL1 – AGC Control Bit 7 6 AGC_LNA_PRIORITY Field Name Reset 1 R/W R0 R/W Description Not used Selects between two different strategies for LNA and LNA2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA2 gain is decreased to minimum before decreasing LNA gain. Sets the relative change threshold for asserting carrier sense 00 01 10 11 3:0 CARRIER_SENSE_ABS_THR[3:0] 0000 R/W Relative carrier sense threshold disabled 6 dB increase in RSSI value 10 dB increase in RSSI value 14 dB increase in RSSI value 5:4 CARRIER_SENSE_REL_THR[1:0] 00 R/W Sets the absolute RSSI threshold for asserting carrier sense (Equal to channel filter amplitude when AGC has not decreased gain). The 2-complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN_TARGET setting. 1000 (-8) 1001 (-7) … 1111 (-1) 0000 (0) 0001 (1) … 0111 (7) Absolute carrier sense threshold disabled 7 dB below MAGN_TARGET setting … 1 dB below MAGN_TARGET setting At MAGN_TARGET setting 1 dB above MAGN_TARGET setting … 7 dB above MAGN_TARGET setting SWRS033E Page 219 of 239 CC1110Fx / CC1111Fx 0xDF19: AGCCTRL0 – AGC Control Bit 7:6 Field Name HYST_LEVEL[1:0] Reset 10 R/W R/W Description Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determines gain changes). 00 01 10 11 5:4 WAIT_TIME[1:0] 01 R/W No hysteresis, small symmetric dead zone, high gain Low hysteresis, small asymmetric dead zone, medium gain Medium hysteresis, medium asymmetric dead zone, medium gain Large hysteresis, large asymmetric dead zone, low gain Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples. 00 01 10 11 8 16 24 32 3:2 AGC_FREEZE[1:0] 00 R/W Controls when the AGC gain should be frozen. 00 01 10 11 Normal operation. Always adjust gain when required. The gain setting is frozen when a sync word has been found. Manually freeze the analog gain setting and continue to adjust the digital gain. Manually freezes both the analog and the digital gain settings. Used for manually overriding the gain. 1:0 FILTER_LENGTH[1:0] 01 R/W Sets the averaging length for the amplitude from the channel filter. Please use the SmartRF® Studio software [9] for recommended settings. 00 01 10 11 8 16 32 64 0xDF1A: FREND1 – Front End RX Configuration Bit 7:6 5:4 3:2 1:0 Field Name LNA_CURRENT[1:0] LNA2MIX_CURRENT[1:0] LODIV_BUF_CURRENT_RX[1:0] MIX_CURRENT[1:0] Reset 01 01 01 10 R/W R/W R/W R/W R/W Description Adjusts front-end LNA PTAT current output Adjusts front-end PTAT outputs Adjusts current in RX LO buffer (LO input to mixer) Adjusts current in mixer SWRS033E Page 220 of 239 CC1110Fx / CC1111Fx 0xDF1B: FREND0 – Front End TX Configuration Bit 7:6 5:4 LODIV_BUF_CURRENT_TX[1:0] Field Name Reset 01 R/W R0 R/W Description Not used Adjusts current TX LO buffer (input to PA). The value to use in this field is given by the SmartRF® Studio software [9]. Not used Selects PA power setting. This value is an index to the PATABLE (PA_TABLE7-PA_TABLE0 registers), which can be programmed with up to 8 different PA settings. In ASK mode, this selects the PATABLE index to use when transmitting a ‘1’. PATABLE index zero is used in ASK when transmitting a ‘0’. The PATABLE settings from index ‘0’ to the PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats. 3 2:0 PA_POWER[2:0] 000 R0 R/W 0xDF1C: FSCAL3 – Frequency Synthesizer Calibration Bit 7:6 Field Name FSCAL3[7:6] Reset 10 R/W R/W Description Frequency synthesizer calibration configuration. The value to write in this register before calibration is given by the SmartRF® Studio software [9]. Disable charge pump calibration stage when 0 Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an FSCAL3[3:0]/4 exponential scale: IOUT=I0·2 Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. 5:4 3:0 CHP_CURR_CAL_EN[1:0] FSCAL3[3:0] 10 1001 R/W R/W Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 0xDF1D: FSCAL2 – Frequency Synthesizer Calibration Bit 7:6 5 VCO_CORE_H_EN Field Name Reset 0 R/W R0 R/W Description Not used Select VCO 0 1 4:0 FSCAL2[4:0] 01010 R/W Low High Frequency synthesizer calibration result register. VCO current calibration result and override value Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. SWRS033E Page 221 of 239 CC1110Fx / CC1111Fx 0xDF1E: FSCAL1 – Frequency Synthesizer Calibration Bit 7:6 5:0 FSCAL1[5:0] Field Name Reset 100000 R/W R0 R/W Description Not used Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. Note: This register will be in its reset state when returning to active mode from PM2 and PM3. 0xDF1F: FSCAL0 – Frequency Synthesizer Calibration Bit 7 6:0 FSCAL0[6:0] Field Name Reset 0001101 R/W R0 R/W Description Not used Frequency synthesizer calibration control. The value to use in this register is given by the SmartRF® Studio software [9]. 0xDF23: TEST2 – Various Test Settings Bit 7:0 Field Name TEST2[7:0] Reset 0x88 R/W R/W Description At low data rates, the sensitivity can be improved by changing it to 0x35 (MDMCFG2.DEM_DCFILT_OFF should be 0). 0xDF24: TEST1 – Various Test Settings Bit 7:0 Field Name TEST1[7:0] Reset 0x11 R/W R/W Description Always set this register to 0x31 when being in TX. At low data rates, the sensitivity can be improved by changing it to 0x35 in RX. (MDMCFG2.DEM_DCFILT_OFF should be 0). 0xDF25: TEST0 – Various Test Settings Bit 7:2 1 0 Field Name TEST0[7:2] VCO_SEL_CAL_EN TEST0[0] Reset 000010 1 1 R/W R/W R/W R/W Description The value to use in this register is given by the SmartRF® Studio software [9]. Enable VCO selection calibration stage when 1 The value to use in this register is given by the SmartRF® Studio software [9]. 0xDF27: PA_TABLE7 – PA Power Setting 7 Bit 7:0 Field Name PA_TABLE7[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 7 0xDF28: PA_TABLE6 – PA Power Setting 6 Bit 7:0 Field Name PA_TABLE6[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 6 0xDF29: PA_TABLE5 – PA Power Setting 5 Bit 7:0 Field Name PA_TABLE5[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 5 0xDF2A: PA_TABLE4 – PA Power Setting 4 Bit 7:0 Field Name PA_TABLE4[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 4 SWRS033E Page 222 of 239 CC1110Fx / CC1111Fx 0xDF2B: PA_TABLE3 – PA Power Setting 3 Bit 7:0 Field Name PA_TABLE3[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 3 0xDF2C: PA_TABLE2 – PA Power Setting 2 Bit 7:0 Field Name PA_TABLE2[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 2 0xDF2D: PA_TABLE1 – PA Power Setting 1 Bit 7:0 Field Name PA_TABLE1[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 1 0xDF2E: PA_TABLE0 – PA Power Setting 0 Bit 7:0 Field Name PA_TABLE0[7:0] Reset 0x00 R/W R/W Description Power amplifier output power setting 0 0xDF36: PARTNUM – Chip ID[15:8] Bit 7:0 Field Name PARTNUM[7:0] Reset 0x01 CC1110Fx 0x11 CC1111Fx R/W R Description Chip part number 0xDF37: VERSION – Chip ID[7:0] Bit 7:0 Field Name VERSION[7:0] Reset 0x03 R/W R Description Chip version number. 0xDF38: FREQEST – Frequency Offset Estimate from Demodulator Bit 7:0 Field Name FREQOFF_EST Reset 0x00 R/W R Description The estimated frequency offset (2’s complement) of the carrier. 14 Resolution is fRef/2 Range is ±186 kHz to ±209 kHz for CC1110Fx and ±186 kHz for CC1111Fx 0xDF39: LQI – Demodulator Estimate for Link Quality Bit 7 Field Name CRC_OK Reset 0 R/W R Description The last CRC comparison matched. Cleared when entering/restarting RX mode. Only valid if PKTCTRL0.CC2400_EN=1. This bit will be 1 if CRC check is disabled (PKTCTRL0.CRC_EN=0) The Link Quality Indicator estimates how easily a received signal can be demodulated. Calculated over the 64 symbols following the sync word. 6:0 LQI_EST[6:0] 0000000 R 0xDF3A: RSSI – Received Signal Strength Indication Bit 7:0 Field Name RSSI Reset 0x80 R/W R Description Received signal strength indicator SWRS033E Page 223 of 239 CC1110Fx / CC1111Fx 0xDF3B: MARCSTATE – Main Radio Control State Machine State Bit 7:5 4:0 MARC_STATE[4:0] Field Name Reset 0001 R/W R0 R Description Not used Main Radio Control FSM State Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 State Name SLEEP IDLE Not used VCOON_MC REGON_MC MANCAL VCOON REGON STARTCAL BWBOOST FS_LOCK IFADCON ENDCAL RX RX_END RX_RST TXRX_SWITCH RX_OVERFLOW FSTXON TX TX_END RXTX_SWITCH TX_UNDERFLOW MANCAL MANCAL MANCAL FS_WAKEUP FS_WAKEUP CALIBRATE SETTLING SETTLING SETTLING CALIBRATE RX RX RX TXRX_SETTLING RX_OVERFLOW FSTXON TX TX RXTX_SETTLING TX_UNDERFLOW State (Figure 54, page201) SLEEP IDLE SWRS033E Page 224 of 239 CC1110Fx / CC1111Fx 0xDF3C: PKTSTATUS –Packet Status Bit 7 6 5 4 3 2:0 Field Name CRC_OK CS PQT_REACHED CCA SFD Reset 0 0 0 0 0 R/ W R R R R R R0 Description The last CRC comparison matched. Cleared when entering/restarting RX mode. Carrier sense Preamble Quality reached Channel is clear Sync word found Not used 0xDF3D: VCO_VC_DAC – Current Setting from PLL Calibration Module Bit 7:0 Field Name VCO_VC_DAC[7:0] Reset 0x94 R/W R Description Status register for test only. SWRS033E Page 225 of 239 CC1110Fx / CC1111Fx 15 Voltage Regulators The CC1110Fx/CC1111Fx includes a low drop-out voltage regulator. This is used to provide a 1.8 V power supply to the CC1110Fx/CC1111Fx digital power supply. The voltage regulator should not be used to provide power to external circuits because of limited power sourcing capability and also due to noise considerations. The voltage regulator input pin AVDD_DREG is to be connected to the unregulated 2.0 V to 3.6 V power supply. The output of the digital regulator is connected internally in the CC1110Fx/CC1111Fx to the digital power supply. The voltage regulator requires an external decoupling capacitor connected to the DCOUPL pin as described in section 10 on page 36. 15.1 Voltage Regulator Power-on The voltage regulator is disabled when the CC1110Fx/CC1111Fx is placed in power modes PM2 or PM3 (see section 13.1). When the voltage regulator is disabled, register and RAM contents will be retained while the unregulated 2.0 V - 3.6 V power supply is present. 16 Radio Test Output Signals For debug and test purposes, a number of internal status signals in the radio may be output on the port pins P1_7 – P1_5. This debug option is controlled through the RF registers IOCFG2-IOCFG0. Table 74 shows the value written to IOCFGx.GDOx_CFG[5:0] with the corresponding internal signals that will be output in each case. GDO0_CFG[5:0] GDO1_CFG[5:0] GDO2_CFG[5:0] 000000 000001 – 000111 001000 001001 001010 – 001101 001110 001111 010000 - 010101 010110 010111 011000 – 011010 011011 011100 011101 011110 - 101110 101111 110000 - 111111 Setting IOCFGx.GDOx_CFG to a value other than 0 will override the P1SEL_SELP1_7, P1SEL_SELP1_6, and P1SEL_SELP1_5 settings, and the pins will automatically become outputs. Description The pin is configured according to the I/O registers. See 13.4.11 Reserved Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value. Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting) Reserved Carrier sense. High if RSSI level is above threshold. CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. Reserved RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. Reserved PA_PD. Can be used to control an external PA or RX/TX switch. Signal is asserted when the radio enters TX state. LNA_PD. Can be used to control an external LNA or RX/TX switch. Signal is asserted when the radio enters RX state. RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output. Reserved HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch. Reserved Table 74: Radio Test Output Signals SWRS033E Page 226 of 239 CC1110Fx / CC1111Fx 17 Register Overview MPAGE (0x93) – Memory Page Select .................................................................................. 53 MEMCTR (0xC7) – Memory Arbiter Control........................................................................ 54 DPH0 (0x83) – Data Pointer 0 High Byte............................................................................... 54 DPL0 (0x82) – Data Pointer 0 Low Byte................................................................................ 54 DPH1 (0x85) – Data Pointer 1 High Byte............................................................................... 54 DPL1 (0x84) – Data Pointer 1 Low Byte................................................................................ 54 DPS (0x92) – Data Pointer Select ........................................................................................... 54 PSW (0xD0) – Program Status Word...................................................................................... 55 ACC (0xE0) – Accumulator.................................................................................................... 55 B (0xF0) – B Register ............................................................................................................. 55 SP (0x81) – Stack Pointer ....................................................................................................... 56 IEN1 (0xB8) – Interrupt Enable 1 Register............................................................................. 64 IEN2 (0x9A) – Interrupt Enable 2 Register ............................................................................ 65 TCON (0x88) – CPU Interrupt Flag 1..................................................................................... 66 S0CON (0x98) – CPU Interrupt Flag 2................................................................................... 67 S1CON (0x9B) – CPU Interrupt Flag 3 .................................................................................. 67 IRCON (0xC0) – CPU Interrupt Flag 4 .................................................................................. 68 IRCON2 (0xE8) – CPU Interrupt Flag 5................................................................................. 69 IP1 (0xB9) – Interrupt Priority 1............................................................................................. 69 IP0 (0xA9) – Interrupt Priority 0............................................................................................. 70 PCON (0x87) – Power Mode Control..................................................................................... 79 SLEEP (0xBE) – Sleep Mode Control ................................................................................... 80 CLKCON (0xC6) – Clock Control ........................................................................................ 83 FCTL (0xAE) – Flash Control ................................................................................................ 90 FWDATA (0xAF) – Flash Write Data.................................................................................... 90 FADDRH (0xAD) – Flash Address High Byte....................................................................... 90 FADDRL (0xAC) – Flash Address Low Byte ........................................................................ 90 FWT (0xAB) – Flash Write Timing........................................................................................ 90 P0 (0x80) – Port 0 ................................................................................................................... 96 P1 (0x90) – Port 1 ................................................................................................................... 96 P2 (0xA0) – Port 2 .................................................................................................................. 96 PERCFG (0xF1) – Peripheral Control .................................................................................... 96 ADCCFG (0xF2) – ADC Input Configuration........................................................................ 97 P0SEL (0xF3) – Port 0 Function Select .................................................................................. 97 P1SEL (0xF4) – Port 1 Function Select .................................................................................. 97 P2SEL (0xF5) – Port 2 Function Select .................................................................................. 98 P0DIR (0xFD) – Port 0 Direction ........................................................................................... 98 P1DIR (0xFE) – Port 1 Direction............................................................................................ 98 P2DIR (0xFF) – Port 2 Direction ............................................................................................ 99 P0INP (0x8F) – Port 0 Input Mode ......................................................................................... 99 P1INP (0xF6) – Port 1 Input Mode ......................................................................................... 99 P2INP (0xF7) – Port 2 Input Mode ......................................................................................... 99 P0IFG (0x89) – Port 0 Interrupt Status Flag ......................................................................... 100 P1IFG (0x8A) – Port 1 Interrupt Status Flag ........................................................................ 100 P2IFG (0x8B) – Port 2 Interrupt Status Flag......................................................................... 100 PICTL (0x8C) – Port Interrupt Control................................................................................. 101 P1IEN (0x8D) – Port 1 Interrupt Mask ................................................................................. 101 DMAARM (0xD6) – DMA Channel Arm ............................................................................ 111 DMAREQ (0xD7) – DMA Channel Start Request and Status.............................................. 112 DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte ....................... 112 DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte ........................ 112 DMA1CFGH (0xD3) – DMA Channel 1-4 Configuration Address High Byte.................... 112 DMA1CFGL (0xD2) – DMA Channel 1-4 Configuration Address Low Byte..................... 112 SWRS033E Page 227 of 239 CC1110Fx / CC1111Fx DMAIRQ (0xD1) – DMA Interrupt Flag.............................................................................. 113 ENDIAN (0x95) – USB Endianess Control (CC1111Fx) ........................................................ 113 T1CNTH (0xE3) – Timer 1 Counter High ............................................................................ 121 T1CNTL (0xE2) – Timer 1 Counter Low ............................................................................. 121 T1CTL (0xE4) – Timer 1 Control and Status ....................................................................... 122 T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control...................................... 123 T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value High ................................ 123 T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value Low ................................. 123 T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control...................................... 124 T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High ................................ 124 T1CC1L (0xDC) – Timer 1 Channel 1 Capture/Compare Value Low ................................. 124 T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control...................................... 125 T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High................................. 125 T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low.................................. 125 T2CTL (0x9E) – Timer 2 Control......................................................................................... 127 T2CT (0x9C) – Timer 2 Count.............................................................................................. 127 T2PR (0x9D) – Timer 2 Prescaler......................................................................................... 127 WORTIME0 (0xA5) – Sleep Timer Low Byte..................................................................... 129 WORTIME1 (0xA6) – Sleep Timer High Byte .................................................................... 129 WOREVT1 (0xA4) – Sleep Timer Event0 Timeout High .................................................... 129 WOREVT0 (0xA3) – Sleep Timer Event0 Timeout Low..................................................... 129 WORCTRL (0xA2) – Sleep Timer Control .......................................................................... 130 WORIRQ (0xA1) – Sleep Timer Interrupt Control .............................................................. 130 T3CNT (0xCA) – Timer 3 Counter....................................................................................... 134 T3CTL (0xCB) – Timer 3 Control ........................................................................................ 134 T3CCTL0 (0xCC) – Timer 3 Channel 0 Capture/Compare Control..................................... 135 T3CC0 (0xCD) – Timer 3 Channel 0 Compare Value.......................................................... 135 T3CCTL1 (0xCE) – Timer 3 Channel 1 Compare Control................................................... 136 T3CC1 (0xCF) – Timer 3 Channel 1 Compare Value .......................................................... 136 T4CNT (0xEA) – Timer 4 Counter ....................................................................................... 136 T4CTL (0xEB) – Timer 4 Control ........................................................................................ 137 T4CCTL0 (0xEC) – Timer 4 Channel 0 Capture/Compare Control ..................................... 138 T4CC0 (0xED) – Timer 4 Channel 0 Compare Value .......................................................... 138 T4CCTL1 (0xEE) – Timer 4 Channel 1 Compare Control ................................................... 139 T4CC1 (0xEF) – Timer 4 Channel 1 Compare Value........................................................... 139 TIMIF (0xD8) – Timers 1/3/4 Interrupt Mask/Flag .............................................................. 140 ADCL (0xBA) – ADC Data Low.......................................................................................... 144 ADCH (0xBB) – ADC Data High......................................................................................... 144 ADCCON1 (0xB4) – ADC Control 1 ................................................................................... 144 ADCCON2 (0xB5) – ADC Control 2 ................................................................................... 145 ADCCON2 (0xB5) – ADC Control 2 ................................................................................... 145 ADCCON3 (0xB6) – ADC Control 3 ................................................................................... 146 RNDL (0xBC) – Random Number Generator Data Low Byte ............................................. 148 RNDH (0xBD) – Random Number Generator Data High Byte............................................ 148 ENCCS (0xB3) – Encryption Control and Status ................................................................. 150 ENCDI (0xB1) – Encryption Input Data.............................................................................. 150 ENCDO (0xB2) – Encryption Output Data.......................................................................... 150 WDCTL (0xC9) – Watchdog Timer Control ........................................................................ 152 U0CSR (0x86) – USART 0 Control and Status .................................................................... 157 U0UCR (0xC4) – USART 0 UART Control ........................................................................ 158 U0GCR (0xC5) – USART 0 Generic Control....................................................................... 158 U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer.............................................. 159 U0BAUD (0xC2) – USART 0 Baud Rate Control ............................................................... 159 U1CSR (0xF8) – USART 1 Control and Status.................................................................... 159 SWRS033E Page 228 of 239 CC1110Fx / CC1111Fx U1UCR (0xFB) – USART 1 UART Control ........................................................................ 160 U1GCR (0xFC) – USART 1 Generic Control ...................................................................... 161 U1DBUF (0xF9) – USART 1 Receive/Transmit Data Buffer .............................................. 161 U1BAUD (0xFA) – USART 1 Baud Rate Control ............................................................... 161 0xDF40: I2SCFG0 – I2S Configuration Register 0 ............................................................... 166 0xDF41: I2SCFG1 – I2S Configuration Register 1 ............................................................... 167 0xDF42: I2SDATL – I2S Data Low Byte ............................................................................. 167 0xDF43: I2SDATH – I2S Data High Byte ............................................................................ 167 0xDF44: I2SWCNT – I2S Word Count Register................................................................... 167 0xDF45: I2SSTAT – I2S Status Register .............................................................................. 168 0xDF46: I2SCLKF0 – I2S Clock Configuration Register 0 .................................................. 168 0xDF47: I2SCLKF1 – I2S Clock Configuration Register 1 .................................................. 168 0xDF48: I2SCLKF2 – I2S Clock Configuration Register 2 .................................................. 168 0xDE00: USBADDR – Function Address ............................................................................ 178 0xDE01: USBPOW – Power/Control Register ..................................................................... 178 0xDE02: USBIIF – IN Endpoints and EP0 Interrupt Flags .................................................. 178 0xDE04: USBOIF – Out Endpoints Interrupt Flags.............................................................. 178 0xDE06: USBCIF – Common USB Interrupt Flags ............................................................. 179 0xDE07: USBIIE – IN Endpoints and EP0 Interrupt Enable Mask ...................................... 179 0xDE09: USBOIE – Out Endpoints Interrupt Enable Mask ................................................. 180 0xDE0B: USBCIE – Common USB Interrupt Enable Mask ................................................ 180 0xDE0C: USBFRML – Current Frame Number (Low byte) ................................................ 180 0xDE0D: USBFRMH – Current Frame Number (High byte)............................................... 181 0xDE0E: USBINDEX – Current Endpoint Index Register................................................... 181 0xDE10: USBMAXI – Max. Packet Size for IN Endpoint{1-5}.......................................... 181 0xDE11: USBCS0 – EP0 Control and Status (USBINDEX=0) ............................................ 181 0xDE11: USBCSIL – IN EP{1-5} Control and Status Low ................................................. 182 0xDE12: USBCSIH – IN EP{1-5} Control and Status High ................................................ 182 0xDE13: USBMAXO – Max. Packet Size for OUT{1-5} Endpoint .................................... 182 0xDE14: USBCSOL – OUT EP{1-5} Control and Status Low............................................ 183 0xDE15: USBCSOH – OUT EP{1-5} Control and Status High .......................................... 183 0xDE16: USBCNT0 – Number of Received Bytes in EP0 FIFO (USBINDEX=0).............. 183 0xDE16: USBCNTL – Number of Bytes in EP{1 – 5} OUT FIFO Low ............................. 183 0xDE17: USBCNTH – Number of Bytes in EP{1 – 5} OUT FIFO High ............................ 184 0xDE20: USBF0 – Endpoint 0 FIFO .................................................................................... 184 0xDE22: USBF1 – Endpoint 1 FIFO .................................................................................... 184 0xDE24: USBF2 – Endpoint 2 FIFO .................................................................................... 184 0xDE26: USBF3 – Endpoint 3 FIFO .................................................................................... 184 0xDE28: USBF4 – Endpoint 4 FIFO .................................................................................... 184 0xDE2A: USBF5 – Endpoint 5 FIFO ................................................................................... 184 RFIF (0xE9) – RF Interrupt Flags......................................................................................... 188 RFIM (0x91) – RF Interrupt Mask........................................................................................ 189 0xDF2F: IOCFG2 – Radio Test Signal Configuration (P1_7).............................................. 209 0xDF30: IOCFG1 – Radio Test Signal Configuration (P1_6) .............................................. 209 0xDF31: IOCFG0 – Radio Test Signal Configuration (P1_5) .............................................. 209 0xDF00: SYNC1 – Sync Word, High Byte........................................................................... 209 0xDF01: SYNC0 – Sync Word, Low Byte ........................................................................... 209 0xDF02: PKTLEN – Packet Length ..................................................................................... 209 0xDF03: PKTCTRL1 – Packet Automation Control ............................................................ 210 0xDF04: PKTCTRL0 – Packet Automation Control ............................................................ 210 0xDF05: ADDR – Device Address ....................................................................................... 211 0xDF06: CHANNR – Channel Number................................................................................ 211 0xDF07: FSCTRL1 – Frequency Synthesizer Control ......................................................... 211 0xDF08: FSCTRL0 – Frequency Synthesizer Control ......................................................... 211 SWRS033E Page 229 of 239 CC1110Fx / CC1111Fx 0xDF09: FREQ2 – Frequency Control Word, High Byte..................................................... 211 0xDF0A: FREQ1 – Frequency Control Word, Middle Byte................................................. 211 0xDF0B: FREQ0 – Frequency Control Word, Low Byte..................................................... 211 0xDF0C: MDMCFG4 – Modem configuration .................................................................... 212 0xDF0D: MDMCFG3 – Modem Configuration ................................................................... 212 0xDF0E: MDMCFG2 – Modem Configuration.................................................................... 213 0xDF0F: MDMCFG1 – Modem Configuration .................................................................... 214 0xDF10: MDMCFG0 – Modem Configuration .................................................................... 214 0xDF11: DEVIATN – Modem Deviation Setting................................................................. 214 0xDF12: MCSM2 – Main Radio Control State Machine Configuration .............................. 215 0xDF13: MCSM1 – Main Radio Control State Machine Configuration .............................. 215 0xDF14: MCSM0 – Main Radio Control State Machine Configuration .............................. 216 0xDF15: FOCCFG – Frequency Offset Compensation Configuration ................................. 216 0xDF16: BSCFG – Bit Synchronization Configuration........................................................ 217 0xDF17: AGCCTRL2 – AGC Control ................................................................................. 218 0xDF18: AGCCTRL1 – AGC Control ................................................................................. 219 0xDF19: AGCCTRL0 – AGC Control ................................................................................. 220 0xDF1A: FREND1 – Front End RX Configuration.............................................................. 220 0xDF1B: FREND0 – Front End TX Configuration .............................................................. 221 0xDF1C: FSCAL3 – Frequency Synthesizer Calibration ..................................................... 221 0xDF1D: FSCAL2 – Frequency Synthesizer Calibration ..................................................... 221 0xDF1E: FSCAL1 – Frequency Synthesizer Calibration ..................................................... 222 0xDF1F: FSCAL0 – Frequency Synthesizer Calibration...................................................... 222 0xDF23: TEST2 – Various Test Settings.............................................................................. 222 0xDF24: TEST1 – Various Test Settings.............................................................................. 222 0xDF25: TEST0 – Various Test Settings.............................................................................. 222 0xDF27: PA_TABLE7 – PA Power Setting 7 ...................................................................... 222 0xDF28: PA_TABLE6 – PA Power Setting 6 ...................................................................... 222 0xDF29: PA_TABLE5 – PA Power Setting 5 ...................................................................... 222 0xDF2A: PA_TABLE4 – PA Power Setting 4 ..................................................................... 222 0xDF2B: PA_TABLE3 – PA Power Setting 3...................................................................... 223 0xDF2C: PA_TABLE2 – PA Power Setting 2...................................................................... 223 0xDF2D: PA_TABLE1 – PA Power Setting 1 ..................................................................... 223 0xDF2E: PA_TABLE0 – PA Power Setting 0...................................................................... 223 0xDF36: PARTNUM – Chip ID[15:8] ................................................................................. 223 0xDF37: VERSION – Chip ID[7:0]...................................................................................... 223 0xDF38: FREQEST – Frequency Offset Estimate from Demodulator................................. 223 0xDF39: LQI – Demodulator Estimate for Link Quality ...................................................... 223 0xDF3A: RSSI – Received Signal Strength Indication......................................................... 223 0xDF3B: MARCSTATE – Main Radio Control State Machine State .................................. 224 0xDF3C: PKTSTATUS –Packet Status ................................................................................ 225 0xDF3D: VCO_VC_DAC – Current Setting from PLL Calibration Module....................... 225 SWRS033E Page 230 of 239 CC1110Fx / CC1111Fx 18 Package Description (QLP 36) All dimensions are in millimeters, angles in degrees. Note: The CC1110Fx/CC1111Fx is available in RoHS lead-free package only. Compliant with JEDEC: MO-220. Figure 61: Package Dimensions Drawing Quad Leadless Package (QLP) A QLP36 Min 0.80 0.85 Max 0.90 A1 0.005 0.025 0.045 A2 0.60 0.65 0.70 D 5.90 6.00 6.10 D1 5.65 5.75 5.85 E 5.90 6.00 6.10 E1 5.65 5.75 5.85 0.50 e b 0.18 0.23 0.30 L 0.45 0.55 0.65 4.40 4.40 D2 E2 Table 75: Package Dimensions SWRS033E Page 231 of 239 CC1110Fx / CC1111Fx 18.1 Recommended PCB Layout for Package (QLP 36) Figure 62: Recommended PCB Layout for QLP 36 Package Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC1110EM reference design [1] and theCC1111 USB-Dongle reference design [4]. Thermal Resistance Air velocity [m/s] Rth,j-a [C/W] 0 32 Table 76: Thermal Properties of QLP 36 Package 18.2 Soldering information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020D should be followed. The lead finish is annealed (150 °C for 1 hr) pure matte tin. 18.3 Tray Specification Tray Specification Package QLP 36 Tray Length 322.6 mm Tray Width 135.9 mm Tray Height 7.62 mm Units per Tray 490 Table 77: Tray Specification SWRS033E Page 232 of 239 CC1110Fx / CC1111Fx 18.4 Carrier Tape and Reel Specification Carrier tape and reel is in accordance with EIA Specification 481. Tape and Reel Specification Package QLP 36 Carrier Tape Width 16 mm Component Pitch 12 mm Hole Pitch 4 mm Reel Diameter 13 inches Reel Hub Diameter 100 mm Units per Reel 2500 Table 78: Carrier Tape and Reel Specification SWRS033E Page 233 of 239 CC1110Fx / CC1111Fx 19 Ordering Information Ordering Part Number CC1110F8RSP Description 8 kB flash, 1 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. CC1110F8RSPR 8 kB flash, 1 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. CC1110F16RSP 16 kB flash, 2 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. CC1110F16RSPR 16 kB flash, 2 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. CC1110F32RSP 32 kB flash, 4 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. CC1110F32RSPR 32 kB flash, 4 kB RAM, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. CC1111F8RSP 8 kB flash, 1 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. CC1111F8RSPR 8 kB flash, 1 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. CC1111F16RSP 16 kB flash, 2 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. CC1111F16RSPR 16 kB flash, 2 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. CC1111F32RSP 32 kB flash, 4 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, Tray with 490 pcs per tray. CC1111F32RSPR 32 kB flash, 4 kB RAM, full-speed USB, System-on-Chip RF Transceiver. QLP36 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel. CC1110DK-433 CC1110DK-868 CC1110EMK433 CC1110EMK868-915 CC1111EMK868-915 CC1110Fx Development Kit, for 433 MHz operation CC1110Fx Development Kit, for 868/915 MHz operation CC1110 Evaluation Module Kit, for 433 MHz operation CC1110 Evaluation Module Kit, for 868/915 MHz operation CC1111 Evaluation Module Kit, for 868/915 MHz operation 1 1 1 1 1 2500 490 2500 490 2500 490 2500 490 2500 490 2500 Minimum Order Quantity 490 Table 79: Ordering Information SWRS033E Page 234 of 239 CC1110Fx / CC1111Fx 20 References [1] [2] [3] [4] [5] CC1110EM315 Reference Design (swrr050.zip) CC1110EM433 Reference Design (swrr047.zip) CC1110EM868-915 Reference Design (swrr049.zip) CC1111 USB-Dongle Reference Design (swrr049.zip) NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf Universal Serial Bus Revision 2.0 Specification. Available from the USB Implementors Forum website. http://www.usb.org/developers/docs/ I2S bus specification, Philips Semiconductors, Available from the Philips Semiconductors website. http://www.semiconductors.philips.com/acrobat_download/various/I2SBUS.pdf IEEE Std 1241-2000, IEEE standard for terminology and test methods for analog-to-digital converters. SmartRF® Studio (swrc046.zip) AN001 SRD regulations for license free transceiver operation(swra090.pdf) ISM-Band and Short Range Device Regulatory Compliance Overview (swra048.pdf) DN006 CC11xx settings for FCC15.247 Solutions (swra123.pdf) AN050 Using the CC1101 in the European 868 MHz SRD band (swra146.pdf) DN016 Compact antenna solutions for 868/915MHz (swra160.pdf) [6] [7] [8] [9] [10] [11] [12] [13] [14] SWRS033E Page 235 of 239 CC1110Fx / CC1111Fx 21 General Information 21.1 Document History Revision SWRS033 SWRS033A SWRS033B Date 2006.01.04 2006.05.11 2007.09.14 Description/Changes First release Preliminary status updated First data sheet for released product. Preliminary data sheets exist for engineering samples and pre-production prototype devices, but these data sheets are not complete and may be incorrect in some aspects compared with the released product. SWRS033C 2007.09.20 Data sheet update before release of product. - Operating frequency range changed to 391-464 MHz and 782-928 MHz - Changed restrivted range for PA power in section 14.15 (now 0x68 to 0x6F) - Added information about register TEST1 when TX-if-CCA is to be used - Changed register FREQEST and FSCTRL0 max range from ±20910 to ±209 - Added reference to SmartRF studio for register MCSM0. - Changed bit description for bit FSCAL2.VCO_CORE_H_EN - Added section 13.1.5.2, describing data rate limitations caused by system clock speed - Added power numbers for RX (Table 6) when using other system clock speeds SWRS033D 2007.10.19 Data sheet update before release of CC1111Fx. -Electrical Specification section 7 updated with CC1111Fx performance -Minimum powerdown time of CC1110Fx high speed crystal oscillator stated in section 7.4.1, section 7.4.2, section 13.1.1 and section 13.1.5.1. rd - Removed 3 overtone crystal option for CC1111Fx - Replaced Figure 14, Figure 15, and Figure 16 to apply for these devices and correct address ranges. - Fixed Table 32 - Fixed bit range for register FADDRH and stated that register WORTIME0 and WORTIME1 defines a combined 16 bit word (WORTIME) - Replaced all occurrences of WORCTL with WORCTRL - Made consistent use of VDD for power with reference to power pin if so needed - Corrected part number for these devices, register PARTNUM - Stated that P1_0 and P1_1 does not have PULL capability in register P2INP - Corrected code example in Figure 48 - Corrected unimplemented RAM range in section 11.2.3.1 - Uppdated sections 13.1.3, 13.1.5.1, and 13.1.5.3 with information about clock source change - Rewrote RAM range in section 13.3.2 for executing CODE from RAM - Updated section 13.8.2 with information about power modes and code examples - Changed heading text for section 13.8.5 - Corrected receiver symbol write and read location in section 14.11.2 SWRS033E 2007.10.26 -Corrected Table of contents -Updated guard time and stated for which crystal this applies in Table 11 Table 80: Document History SWRS033E Page 236 of 239 CC1110Fx / CC1111Fx 21.2 Product Status Definitions Data Sheet Identification Advance Information Product Status Planned or Under Development Experimental and Prototype Devices Definition This data sheet contains the design specifications for product development. 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