CD74HCT670M

CD54HC670, CD74HC670, CD74HCT670 Data sheet acquired from Harris Semiconductor SCHS195C January 1998 - Revised October 2003 High-Speed CMOS Logic 4x4 Register File Description The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE) is low. The output is in the high impedance state when the (RE) is high. Outputs can be tied together to increase the word capacity to 512 x 4 bits. Features [ /Title (CD74H C670, CD74H CT670) /Subject (HighSpeed CMOS Logic 4x4 Register • Simultaneous and Independent Read and Write Operations • Expandable to 512 Words of n-Bits • Three-State Outputs • Organized as 4 Words x 4 Bits Wide • Buffered Inputs • Typical Read Time = 16ns for ’HC670 VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information PART NUMBER CD54HC670F3A CD74HC670E CD74HC670M CD74HC670MT CD74HC670M96 CD74HCT670E CD74HCT670M CD74HCT670MT CD74HCT670M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC670 (CERDIP) CD74HC670, CD74HCT670 (PDIP, SOIC) TOP VIEW D1 1 D2 2 D3 3 RA1 4 RA0 5 Q3 6 Q2 7 GND 8 16 VCC 15 D0 14 WA0 13 WA1 12 WE 11 RE 10 Q0 9 Q1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC670, CD74HC670, CD74HCT670 Functional Diagram 15 D0 D1 D2 D3 WE RE RA1 RA0 WA0 WA1 4 5 14 13 1 2 3 12 11 10 9 7 6 Q0 Q1 Q2 Q3 WRITE MODE SELECT TABLE INPUTS OPERATING MODE Write Data WE L L Data Latched NOTE: 1. The Write Address (WA0 and WA1) to the “internal latches” must be stable while WE is LOW for conventional operation. H DN L H X INTERNAL LATCHES (NOTE 1) L H No Change Disabled NOTE: READ MODE SELECT TABLE INPUTS OPERATING MODE Read INTERNAL LATCHES (NOTE 2) L H X OUTPUT QN L H (Z) RE L L H 2. The selection of the “internal latches” by Read Address (RA0 and RA1) are not constrained by WE or RE operation. H = High Voltage Level L = Low Voltage Level X= Don’t Care Z = High Impedance “Off” State 2 CD54HC670, CD74HC670, CD74HCT670 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . ±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . ±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . ±50mA Thermal Information Thermal Resistance (Typical, Note 3) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 V V V V V V V V V V V V V V V V V V µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 3 CD54HC670, CD74HC670, CD74HCT670 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three- State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Three- State Leakage Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. ∆ICC (Note 4) II ICC VCC and GND VCC or GND VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND VIL or VIH IO (mA) 0 VO = VCC or GND 25oC MIN TYP MAX 8 ±0.5 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 ±5.0 MIN MAX 160 ±10 UNITS µA µA VCC (V) 6 6 -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 VO = VCC or GND - 5.5 5.5 5.5 - ±0.1 8 ±0.5 - ±1 80 ±5.0 - ±1 160 ±10 µA µA µA VCC -2.1 4.5 to 5.5 - 100 360 - 450 - 490 µA HCT Input Loading Table INPUT WE WA0 WA1 RE DATA RA0 RA1 UNIT LOADS 0.3 0.2 0.4 1.5 0.15 0.4 0.7 NOTE: Unit Load is ∆ICC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25oC. 4 CD54HC670, CD74HC670, CD74HCT670 Prerequisite for Switching Specifications 25oC PARAMETER HC TYPES Setup Time Data to WE Write to WE tSU, th 2 4.5 6 Hold Time Data to WE Write to WE tH, tW 2 4.5 6 Pulse Width WE tW 2 4.5 6 Latch Time WE to RA0, RA1 tLATCH 2 4.5 6 HCT TYPES Setup Time Data to WE Hold Time Data to WE Write to WE Setup Time Write to WE Pulse Width WE Latch Time WE to RA0, RA1 tSU, th tH, tW 4.5 12 15 18 ns 60 12 10 5 5 5 80 16 14 100 20 17 75 15 13 5 5 5 100 20 17 125 25 21 90 18 15 5 5 5 120 24 20 150 30 26 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN TYP MAX -55oC TO 125oC MIN TYP MAX UNITS 4.5 5 - - 5 - - 5 - - ns tSU tW tLATCH 4.5 18 - - 23 - - 27 - - ns 4.5 4.5 20 25 - - 25 31 - - 30 38 - - ns ns Switching Specifications CL = 50pF, Input tr, tf = 6ns 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS PARAMETER HC TYPES Propagation Delay Reading Any Word SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 16 21 195 39 33 250 50 43 245 49 42 315 63 54 295 59 50 375 75 64 ns ns ns ns ns ns ns ns Write Enable to Output tPLH, tPHL CL = 50pF 5 CD54HC670, CD74HC670, CD74HCT670 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) 25oC VCC (V) 2 4.5 CL = 15pF CL = 50pF Output Disable Time tPLZ, tPHZ CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Output Enable Time tPZL, tPZH CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF Output Transition Time tTHL, tTLH CL = 50pF 5 6 2 4.5 6 Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay Reading Any Word tPHL, tPLH CL = 50pF CL = 15pF Write Enable to Output tPHL, tPLH CL = 50pF CL = 15pF Data to Output tPHL, tPLH CL = 50pF CL = 15pF Output Disable Time tPLZ, tPHZ CL = 50pF CL = 15pF Output Enable Time tPZL, tPZH CL = 50pF CL = 15pF Output Transition Time Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per output. 6. PD = CPD VCC2 fi + ∑ CL VCC2 fO where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. tTLH, tTHL CI CO CPD CL = 50pF CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 10 20 17 21 21 14 16 66 40 50 50 35 38 15 10 20 50 63 63 44 48 19 10 20 53 75 75 53 57 22 10 20 ns ns ns ns ns ns ns ns ns ns ns pF pF pF CI CO CPD CL = 50pF CL = 15pF 5 MIN 10 20 TYP 21 12 12 59 MAX 256 50 43 150 30 26 150 30 26 75 15 13 10 20 -40oC TO 85oC MIN MAX 315 63 54 190 38 33 190 38 33 95 19 10 10 20 -55oC TO 125oC MIN MAX 375 75 64 225 45 38 225 45 38 110 22 19 10 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF PARAMETER Data to Output SYMBOL tPLH, tPHL TEST CONDITIONS CL = 50pF 6 CD54HC670, CD74HC670, CD74HCT670 Test Circuits and Waveforms trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK trCL = 6ns tWL + tWH = tfCL = 6ns 2.7V 0.3V I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns INPUT 90% 50% 10% tf = 6ns VCC tr = 6ns INPUT GND 2.7V 1.3V 0.3V tf = 6ns 3V GND tTLH 90% tTHL tTLH 90% 50% 10% tPHL tPLH tTHL INVERTING OUTPUT INVERTING OUTPUT tPHL tPLH 1.3V 10% FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL CLOCK INPUT 90% 10% tH(H) tfCL VCC 50% GND tH(L) VCC DATA INPUT tSU(H) CLOCK INPUT trCL 2.7V 0.3V tH(H) tfCL 3V 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V tSU(L) tTLH tTHL 90% 1.3V 10% tPHL GND DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL 50% GND OUTPUT 90% 1.3V tPLH 50% GND tREM 3V SET, RESET OR PRESET 1.3V GND IC CL 50pF IC CL 50pF FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7 CD54HC670, CD74HC670, CD74HCT670 Test Circuits and Waveforms 6ns OUTPUT DISABLE 90% 50% 10% tPZL 50% 10% tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED tPZH OUTPUT HIGH TO OFF OUTPUTS ENABLED OUTPUT LOW TO OFF tPHZ 90% (Continued) tr VCC GND tPLZ OUTPUT DISABLE 6ns tf 2.7 1.3 6ns 3V 0.3 tPZL GND 6ns tPLZ OUTPUT LOW TO OFF 10% tPZH 1.3V 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device CD54HC670F3A CD74HC670E CD74HC670EE4 CD74HC670M CD74HC670M96 CD74HC670M96E4 CD74HC670M96G4 CD74HC670ME4 CD74HC670MG4 CD74HC670MT CD74HC670MTE4 CD74HC670MTG4 CD74HCT670E CD74HCT670EE4 CD74HCT670M CD74HCT670M96 CD74HCT670M96E4 CD74HCT670M96G4 CD74HCT670ME4 CD74HCT670MG4 CD74HCT670MT CD74HCT670MTE4 CD74HCT670MTG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing J N N D D D D D D D D D N N D D D D D D D D D Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1 25 25 40 TBD Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Lead/Ball Finish A42 SNPB CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 40 40 250 250 250 25 25 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 40 40 250 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOIC SOIC D D 16 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 16.4 16.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 8.0 W Pin1 (mm) Quadrant 16.0 16.0 Q1 Q1 CD74HC670M96 CD74HCT670M96 2500 2500 6.5 6.5 10.3 10.3 2.1 2.1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device CD74HC670M96 CD74HCT670M96 Package Type SOIC SOIC Package Drawing D D Pins 16 16 SPQ 2500 2500 Length (mm) 333.2 333.2 Width (mm) 345.9 345.9 Height (mm) 28.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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