PCA9517

www.ti.com PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 1 FEATURES Two-Channel Bidirectional Buffer I2C Bus and SMBus Compatible Operating Supply Voltage Range of 0.9 V to 5.5 V on A Side Operating Supply Voltage Range of 2.7 V to 5.5 V on B Side Voltage-Level Translation From 0.9 V to 5.5 V and 2.7 V to 5.5 V Footprint and Function Replacement for PCA9515A Active-High Repeater-Enable Input Open-Drain I2C I/O 5.5-V Tolerant I2C and Enable Input Support Mixed-Mode Signal Operation D PACKAGE (TOP VIEW) • • • • • • • • • • • • • • • • Lockup-Free Operation Accommodates Standard Mode and Fast Mode I2C Devices and Multiple Masters Supports Arbitration and Clock Stretching Across Repeater Powered-Off High-Impedance I2C Pins 400-kHz Fast I2C Bus Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) VCCA SCLA SDAA GND 1 2 3 4 8 7 6 5 VCCB SCLB SDAB EN VCCA SCLA SDAA GND DGK PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 VCCB SCLB SDAB EN DESCRIPTION/ORDERING INFORMATION This dual bidirectional I2C buffer is operational at 2.7 V to 5.5 V. The PCA9517 is a BiCMOS integrated circuit intended for I2C bus and SMBus systems. It can also provide bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and similar bus systems to be extended, without degradation of performance even during level shifting. The PCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing two buses of 400-pF bus capacitance to be connected in an I2C application. This device can also be used to isolate two halves of a bus for voltage and capacitance. The PCA9517 has two types of drivers—A-side drivers and B-side drivers. All inputs and I/Os are overvoltage tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V). ORDERING INFORMATION TA –40°C to 85°C (1) (2) SOIC – D MSOP – DGK PACKAGES (1) (2) Tape and reel Tape and reel ORDERABLE PART NUMBER PCA9517DR PCA9517DGKR TOP-SIDE MARKING PD517 7EA Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The B-side drivers operate from 2.7 V to 5.5 V and behave like the drivers in the PCA9515A. This side also supports the standard low-level contention arbitration of the I2C bus and clock stretching. The output low level for this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low condition is released. This type of design on the B side prevents it from being used in series with the PCA9515A and another PCA9517 (B side). This is because these devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again. The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low feature (or the static offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on the A side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A side drives a hard low, and the input level is set at 0.3 VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.9 V. The A side of two or more PCA9517s can be connected together to allow a star topography, with the A side on the common bus. Also, the A side can be connected directly to any other buffer with static- or dynamic-offset voltage. Multiple PCA9517s can be connected in series, A side to B side, with no buildup in offset voltage and with only time-of-flight delays to consider. The PCA9517 drivers are enabled when VCCA is above 0.8 V and VCCB is above 2.5 V. The PCA9517 has an active-high enable (EN) input with an internal pullup to VCCB, which allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It should never change state during an I2C operation, because disabling during a bus operation hangs the bus, and enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input should change state only when the global bus and repeater port are in an idle state, to prevent system failures. The PCA9517 includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. VCCB and VCCA can be applied in any sequence at power up. After power up and with the EN high, a low level on the A side (below 0.3 VCCA) turns the corresponding B-side driver (either SDA or SCL) on and drives the B side down to approximately 0.5 V. When the A side rises above 0.3 VCCA, the B-side pulldown driver is turned off and the external pullup resistor pulls the pin high. When the B side falls first and goes below 0.3 VCCB, the A-side driver is turned on and the A side pulls down to 0 V. The B-side pulldown is not enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the A-side driver turns off when the B-side voltage is above 0.7 VCCB. If the B-side low voltage goes below 0.4 V, the B-side pulldown driver is enabled, and the B side is able to rise to only 0.5 V until the A side rises above 0.3 VCCA. Then the B side continues to rise, being pulled up by the external pullup resistor. VCCA is only used to provide the 0.3 VCCA reference to the A-side input comparators and for the power-good-detect circuit. The PCA9517 logic and all I/Os are powered by the VCCB pin. As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The PCA9517 has standard open-collector configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used. 2 Submit Documentation Feedback Product Folder Link(s): PCA9517 Copyright © 2007–2008, Texas Instruments Incorporated www.ti.com PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 TERMINAL FUNCTIONS NO. 1 2 3 4 5 6 7 8 NAME VCCA SCLA SDAA GND EN SDAB SCLB VCCB A-side supply voltage (0.9 V to 5.5 V) Serial clock bus, A side. Connect to VCCA through a pullup resistor. Serial data bus, A side. Connect to VCCA through a pullup resistor. Supply ground Active-high repeater enable input Serial data bus, B side. Connect to VCCB through a pullup resistor. Serial clock bus, B side. Connect to VCCB through a pullup resistor. B-side and device supply voltage (2.7 V to 5.5 V) DESCRIPTION FUNCTION TABLE INPUT EN L H FUNCTION Outputs disabled SDAA = SDAB SCLA = SCLB FUNCTIONAL BLOCK DIAGRAM VCCA 1 VCCB 8 3 SDAA 6 SDAB 2 SCLA 7 SCLB VCCB Pullup Resistor 5 EN 4 GND Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9517 3 PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCCB VCCA VI VI/O IIK IOK IO θJA Tstg (1) (2) (3) Supply voltage range Supply voltage range Enable input voltage range I2C bus voltage range (2) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Package thermal impedance (3) Storage temperature range D package DGK package –65 VI < 0 VO < 0 (2) MAX 7 7 7 7 –50 –50 ±50 ±100 97 172 150 UNIT V V V V mA mA mA °C/W °C –0.5 –0.5 –0.5 –0.5 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions MIN VCCA VCCB VIH Supply voltage, A-side bus Supply voltage, B-side bus SDAA, SCLA High-level input voltage SDAB, SCLB EN SDAA, SCLA VIL Low-level input voltage SDAB, SCLB EN IOL TA (1) (2) Low-level output current Operating free-air temperature VCCB = 2.7 V VCCB = 3 V –40 0.9 (1) 2.7 0.7 × VCCA 0.7 × VCCB 0.7 × VCCB –0.5 (2) –0.5 MAX 5.5 5.5 5.5 5.5 5.5 0.3 × VCCB 0.3 × VCCB 6 6 85 mA °C V V UNIT V V –0.5 0.28 × VCCA Low-level supply voltage VIL specification is for the first low level seen by the SDAB and SCLB lines. VILc is for the second and subsequent low levels seen by the SDAB and SCLB lines. 4 Submit Documentation Feedback Product Folder Link(s): PCA9517 Copyright © 2007–2008, Texas Instruments Incorporated www.ti.com PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 Electrical Characteristics VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER VIK VOL Input clamp voltage Low-level output voltage Low-level input voltage below low-level output voltage SDAB, SCLB SDAA, SCLA SDAB, SCLB TEST CONDITIONS II = –18 mA IOL = 100 µA or 6 mA, VILA = VILB = 0 V IOL = 6 mA 2.7 V to 5.5 V 2.7 V to 5.5 V Both channels low, SDAA = SCLA = GND and SDAB = SCLB = open, or SDAA = SCLA = open and SDAB = SCLB = GND Both channels high, SDAA = SCLA = VCCA and SDAB = SCLB = VCCB and EN = VCCB ICC Quiescent supply current Both channels low, SDAA = SCLA = GND and SDAB = SCLB = open, or SDAA = SCLA = open and SDAB = SCLB = GND In contention, SDAA = SCLA = GND and SDAB = SCLB = GND SDAB, SCLB II Input leakage current SDAA, SCLA EN IOH High-level output leakage current SDAB, SCLB SDAA, SCLA EN CI Input capacitance SCLA, SCLB VI = VCCB VI = 0.2 V VI = VCCB VI = 0.2 V VI = VCCB VI = 0.2 V VO = 3.6 V VI = 3 V or 0 V VI = 3 V or 0 V 2.7 V to 5.5 V 3.3 V 3.3 V 0V 3.3 V 0V 6 6 6 6 6 –10 2.7 V to 5.5 V 5.5 V 1.5 –0.5 0.4 VCCB 2.7 V to 5.5 V 2.7 V to 5.5 V 0.45 0.52 0.1 MIN TYP MAX –1.2 0.7 0.2 70 mV V UNIT V V VOL – VILc VILC SDA and SCL low-level SDAB, SCLB input voltage contention ICC Quiescent supply current for VCCA 1 mA 4 1.5 5 mA 1.5 5 ±1 10 ±1 10 ±1 –30 10 10 7 9 8 9 8 pF pF µA µA CIO Input/output capacitance SDAA, SDAB VI = 3 V or 0 V Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) MIN tsu th (1) Setup time, EN high before Start condition (1) Hold time, EN high after Stop condition (1) EN should change state only when the global bus and the repeater port are in an idle state. 100 100 MAX UNIT ns ns Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9517 5 PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 www.ti.com I2C Interface Timing Requirements VCCB = 2.7 V to 5.5 V, GND = 0 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER FROM (INPUT) SDAB, SCLB (2) (see Figure 4) SDAA, SCLA (3) (see Figure 3) TO (OUTPUT) SDAA, SCLA (2) (see Figure 4) SDAB, SCLB (3) (see Figure 3) VCCA ≤ 2.7 V (see Figure 2) SDAB, SCLB tPZL Propagation delay SDAA, SCLA (3) (see Figure 3) B side to A side (see Figure 3) A side to B side (see Figure 2) SDAB, SCLB (3) (see Figure 3) SDAA, SCLA 2.7 V ≤ VCCA ≤ 3 V (see Figure 2) VCCA ≥ 3 V (see Figure 2) TEST CONDITIONS MIN 100 25 15 20 10 45 1 20% 80% 20 VCCA ≤ 2.7 V (see Figure 3) B side to A side tTHL Transition time 80% 20% 2.7 V ≤ VCCA ≤ 3 V (see Figure 2) VCCA ≥ 3 V (see Figure 3) 1 1 1 1 31 3 (4) 6 25 (5) 12 170 105 120 ns 175 90 TYP (1) MAX UNIT 169 67 68 (4) 79 103 (5) 118 6 255 ns 110 110 130 ns 300 230 30 ns tPLZ Propagation delay tTLH Transition time A side to B side (see Figure 2) (1) (2) (3) (4) (5) Typical values were measured with VCCA = VCCB = 2.7 V at TA = 25°C, unless otherwise noted. The tPLH delay data from B to A side is measured at 0.5 V on the B side to 0.5 VCCA on the A side when VCCA is less than 2 V, and 1.5 V on the A side if VCCA is greater than 2 V. The proportional delay data from A to B side is measured at 0.3 VCCA on the A side to 1.5 V on the B side. Typical value measured with VCCA = 0.9 V at TA = 25°C Typical value measured with VCCA = 5.5 V at TA = 25°C 6 Submit Documentation Feedback Product Folder Link(s): PCA9517 Copyright © 2007–2008, Texas Instruments Incorporated www.ti.com PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 PARAMETER MEASUREMENT INFORMATION VCC RL (see Note A) VCC S1 GND CL = 57 pF (see Note C) VIN PULSE GENERATOR RT (see Note B) DUT VOUT TEST tPLZ/tPZL S1 VCC TEST CIRCUIT FOR OPEN-DRAIN OUTPUT A. B. C. D. E. F. G. H. RL = 167 Ω on the A side and 1.35 kΩ on the B side RT termination resistance should be equal to ZOUT of pulse generators. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. Figure 1. Test Circuit 3V INPUT 1.5 V 1.5 V 0.1 V tPZL 80% OUTPUT 0.6 V 20% tTHL 0.6 V 20% tTLH tPLZ 1.2 V 80% VOL Figure 2. Waveform 1 – Propagation Delay and Transition Times for B Side to A Side VCCA INPUT 0.3 VCCA tPZL 80% OUTPUT 20% 1.5 V 0.3 VCCA tPLZ 3V 80% 1.5 V 20% VCCA Figure 3. Waveform 2 – Propagation Delay and Transition Times for A Side to B Side Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9517 7 PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) INPUT SDAB, SCLB 0.5 V OUTPUT SCLA, SDAA tPLH 50% is VCCA is less than 2 V 1.5 V if VCCA is greater than 2 V Figure 4. Waveform 3 8 Submit Documentation Feedback Product Folder Link(s): PCA9517 Copyright © 2007–2008, Texas Instruments Incorporated www.ti.com PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 APPLICATION INFORMATION A typical application is shown in Figure 5. In this example, the system master is running on a 3.3-V I2C bus, and the slave is connected to a 1.2-V bus. Both buses run at 400 kHz. Master devices can be placed on either bus. The PCA9517 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9-V to 5.5-V bus voltages and 2.7-V to 5.5-V bus voltages. When the A side of the PCA9517 is pulled low by a driver on the I2C bus, a comparator detects the falling edge when it goes below 0.3 VCCA and causes the internal driver on the B side to turn on, causing the B side to pull down to about 0.5 V. When the B side of the PCA9517 falls, first a CMOS hysteresis-type input detects the falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 7 and Figure 8. If the bus master in Figure 5 were to write to the slave through the PCA9517, waveforms shown in Figure 7 would be observed on the A bus. This looks like a normal I2C transmission, except that the high level may be as low as 0.9 V, and the turn on and turn off of the acknowledge signals are slightly delayed. On the B-side bus of the PCA9517, the clock and data lines would have a positive offset from ground equal to the VOL of the PCA9517. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by the driver in the PCA9517 for a short delay, while the A-bus side rises above 0.3 VCCA and then continues high. It is important to note that any arbitration or clock stretching events require that the low level on the B-bus side at the input of the PCA9517 (VIL) be at or below 0.4 V to be recognized by the PCA9517 and then transmitted to the A-bus side. 3.3 V 1.2 V 10 kΩ SDA BUS MASTER 400 kHz SCL 10 kΩ VCCB SDAB 10 kΩ VCCA SDAA 10 kΩ SDA SCL SLAVE 400 kHz BUS A SCLB SCLA PCA9517 EN BUS B Figure 5. Typical Application Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9517 9 PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 VCCA VCCB www.ti.com 10 kΩ SDA SCL BUS MASTER 10 kΩ 10 kΩ SDAA SDAB SCLA SCLB PCA9517 EN 10 kΩ SDA SCL SLAVE 400 kHz 10 kΩ SDAA SDAB SCLA SCLB PCA9517 EN 10 kΩ SDA SCL SLAVE 400 kHz 10 kΩ SDAA SDAB SCLA SCLB PCA9517 EN 10 kΩ SDA SCL SLAVE 400 kHz Figure 6. Typical Star Application Multiple PCA9517 A sides can be connected in a star configuration, allowing all nodes to communicate with each other. VCCB 10 kΩ SDA SCL BUS MASTER 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ SDA SCL SLAVE 400 kHz SDAA SDAB SCLA SCLB PCA9517 EN SDAA SDAB SCLA SCLB PCA9517 EN SDAA SDAB SCLA SCLB PCA9517 EN Figure 7. Typical Series Application Multiple PCA9517s can be connected in series as long as the A side is connected to the B side. I2C bus slave devices can be connected to any of the bus segments. The number of devices that can be connected in series is limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements. 10 Submit Documentation Feedback Product Folder Link(s): PCA9517 Copyright © 2007–2008, Texas Instruments Incorporated www.ti.com PCA9517 LEVEL-TRANSLATING I2C BUS REPEATER SCPS157A – DECEMBER 2007 – REVISED FEBRUARY 2008 9th CLOCK PULSE — ACKNOWLEDGE SCL 0.5 V/DIV SDA Figure 8. Bus A (0.9-V to 5.5-V Bus) Waveform 9th CLOCK PULSE — ACKNOWLEDGE SCL 2 V/DIV SDA VOL OF PCA9517 VOL OF SLAVE Figure 9. Bus B (2.7-V to 5.5-V Bus) Waveform Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9517 11 PACKAGE OPTION ADDENDUM www.ti.com 13-Feb-2008 PACKAGING INFORMATION Orderable Device PCA9517D PCA9517DG4 PCA9517DGKR PCA9517DGKRG4 PCA9517DR PCA9517DRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC MSOP MSOP SOIC SOIC Package Drawing D D DGK DGK D D Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jan-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 12.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PCA9517DR 2500 6.4 5.2 2.1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jan-2009 *All dimensions are nominal Device PCA9517DR Package Type SOIC Package Drawing D Pins 8 SPQ 2500 Length (mm) 346.0 Width (mm) 346.0 Height (mm) 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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