SN54AHCT16541

SN54AHCT16541, SN74AHCT16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS339H – MARCH 1996 – REVISED JANUARY 2000 D D D D D D D Members of the Texas Instruments Widebus ™ Family EPIC ™ (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54AHCT16541 . . . WD PACKAGE SN74AHCT16541 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) description The ’AHCT16541 devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state. 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 GND 1Y7 1Y8 2Y1 2Y2 GND 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2Y8 2OE1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE2 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54AHCT16541 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHCT16541 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit buffer/driver) INPUTS OE1 L L H X OE2 L L X H A L H X X OUTPUT Y L H Z Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Copyright © 2000, Texas Instruments Incorporated • DALLAS, TEXAS 75265 1 SN54AHCT16541, SN74AHCT16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS339H – MARCH 1996 – REVISED JANUARY 2000 logic symbol† 1OE1 1OE2 2OE1 2OE2 24 25 & EN2 1 48 & EN1 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 1 2 3 5 6 8 9 11 12 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 1 2 13 14 16 17 19 20 22 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE1 1OE2 1 48 2OE1 2OE2 2 24 25 1A1 47 1Y1 2A1 36 13 2Y1 To Seven Other Channels To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT16541, SN74AHCT16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS339H – MARCH 1996 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54AHCT16541 MIN VCC VIH VIL VI VO IOH IOL ∆t/∆v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 5.5 VCC –8 8 20 0 0 MAX 5.5 SN74AHCT16541 MIN 4.5 2 0.8 5.5 VCC –8 8 20 MAX 5.5 UNIT V V V V V mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHCT16541, SN74AHCT16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS339H – MARCH 1996 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC† Ci TEST CONDITIONS CONDITIONS IOH = –50 mA IOH = –8 mA IOL = 50 mA IOL = 8 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND VCC 4.5 V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V 5.5 V 5V 2 MIN 4.4 3.94 0.1 0.36 ±0.1 ±0.25 4 1.35 10 TA = 25°C TYP MAX 4.5 SN54AHCT16541 MIN 4.4 3.8 0.1 0.44 ±1* ±2.5 40 1.5 MAX SN74AHCT16541 MIN 4.4 3.8 0.1 0.44 ±1 ±2.5 40 1.5 10 MAX UNIT V V mA mA mA mA pF pF Co 5V 3 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) FROM (INPUT) A TO (OUTPUT) Y Y Y Y Y Y LOAD CAPACITANCE CL = 15 pF 15 CL = 15 pF 15 CL = 15 pF 15 CL = 50 pF 50 CL = 50 pF 50 CL = 50 pF 50 CL = 50 pF TA = 25°C MIN TYP MAX 5.4** 5.4** 7.7** 7.7** 4.5** 4.5** 6.2 6 7.5 7.5 7 7 8.5** 8.5** 10.4** 10.4** 10.4** 10.4** 9.5 9.5 11.4 11.4 11.4 11.4 1*** SN54AHCT16541 MIN 1** 1** 1** 1** 1** 1** 1 1 1 1 1 1 MAX 10** 10** 12** 12** 12** 12** 11 11 13 13 13 13 SN74AHCT16541 MIN 1 1 1 1 1 1 1 1 1 1 1 1 MAX 9.5 9.5 12 12 12 12 10.5 10.5 13 13 13 13 1 UNIT ns ns ns ns ns ns ns OE OE A OE OE ** On products compliant to MIL-PRF-38535, this parameter is not production tested. *** On products compliant to MIL-PRF-38535, this parameter does not apply. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2 0.8 SN74AHCT16541 MIN TYP 0.6 –0.3 4.6 MAX UNIT V V V V V VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT16541, SN74AHCT16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS339H – MARCH 1996 – REVISED JANUARY 2000 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 12 UNIT pF PARAMETER MEASUREMENT INFORMATION RL = 1 k Ω S1 VCC Open GND From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain S1 Open VCC GND VCC LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS 3V Timing Input tw 3V tsu Data Input 0V 1.5 V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V tPZL 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 1.5 V 0V tPLZ ≈VCC VOL + 0.3 V VOL tPHZ VOH – 0.3 V VOH ≈0 V Input 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output 1.5 V 1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL Output Control Output Waveform 1 S1 at VCC (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device 74AHCT16541DGGRE4 74AHCT16541DGGRG4 74AHCT16541DGVRE4 74AHCT16541DGVRG4 74AHCT16541DLRG4 SN74AHCT16541DGGR SN74AHCT16541DGVR SN74AHCT16541DL SN74AHCT16541DLG4 SN74AHCT16541DLR (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type TSSOP TSSOP TVSOP TVSOP SSOP TSSOP TVSOP SSOP SSOP SSOP Package Drawing DGG DGG DGV DGV DL DGG DGV DL DL DL Pins Package Eco Plan (2) Qty 48 48 48 48 48 48 48 48 48 48 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 1000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TSSOP TVSOP SSOP DGG DGV DL 48 48 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 330.0 24.4 24.4 32.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 12.0 12.0 16.0 W Pin1 (mm) Quadrant 24.0 24.0 32.0 Q1 Q1 Q1 SN74AHCT16541DGGR SN74AHCT16541DGVR SN74AHCT16541DLR 2000 2000 1000 8.6 6.8 11.35 15.8 10.1 16.2 1.8 1.6 3.1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device SN74AHCT16541DGGR SN74AHCT16541DGVR SN74AHCT16541DLR Package Type TSSOP TVSOP SSOP Package Drawing DGG DGV DL Pins 48 48 48 SPQ 2000 2000 1000 Length (mm) 346.0 346.0 346.0 Width (mm) 346.0 346.0 346.0 Height (mm) 41.0 41.0 49.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) 48 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,50 48 0,27 0,17 25 0,08 M 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 0,25 0°– 8° A 0,75 0,50 1 24 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 48 56 64 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) 48 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 25 0.005 (0,13) M 48 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 A 24 0°– 8° 0.040 (1,02) 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10) PINS ** DIM A MAX 28 0.380 (9,65) 0.370 (9,40) 48 0.630 (16,00) 0.620 (15,75) 56 0.730 (18,54) 0.720 (18,29) 4040048 / E 12/01 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN 0,23 0,13 13 PLASTIC SMALL-OUTLINE 0,40 24 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 A 12 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,08 PINS ** DIM A MAX A MIN 14 3,70 3,50 16 3,70 3,50 20 5,10 4,90 24 5,10 4,90 38 7,90 7,70 48 9,80 9,60 56 11,40 11,20 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. 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