TPA4411 TPA4411M
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80-mW DIRECTPATH™ STEREO HEADPHONE DRIVER
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FEATURES
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20 19 17 16 20 19 18 17
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• Space Saving Packages – 20-Pin, 4 mm × 4 mm Thin QFN – TPA4411 – Thermally Optimized PowerPAD™ Package – TPA4411M – Thermally Enhanced PowerPAD™ Package – 16-Ball, 2.18 mm × 2.18 mm WCSP • Ground-Referenced Outputs Eliminate DC-Bias Voltages on Headphone Ground Pin – No Output DC-Blocking Capacitors – Reduced Board Area – Reduced Component Cost – Improved THD+N Performance – No Degradation of Low-Frequency Response Due to Output Capacitors • Wide Power Supply Range: 1.8 V to 4.5 V • 80-mW/Ch Output Power into 16-Ω at 4.5 V • Independent Right and Left Channel Shutdown Control • Short-Circuit and Thermal Protection • Pop Reduction Circuitry
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TPA4411RTJ
A2 A1 B1 C1 D1
INR SGND
TPA4411MRTJ
A3
PVDD
A4
C1P
SDR
SDL
NC
PGND
INL
OUTR
NC
C1N
SVDD
OUTL
SVSS
PVSS
TPA4411YZH
DESCRIPTION
The TPA4411 and TPA4411M are stereo headphone drivers designed to allow the removal of the output DC-blocking capacitors for reduced component count and cost. The TPA4411 and TPA4411M are ideal for small portable electronics where size and cost are critical design parameters. The TPA4411 and TPA4411M are capable of driving 80 mW into a 16-Ω load at 4.5 V. Both TPA4411 and TPA4411M have a fixed gain of –1.5 V/V and headphone outputs that have ±8-kV IEC ESD protection. The TPA4411 and TPA4411M have independent shutdown control for the right and left audio channels. The TPA4411 is available in a 2.18 mm × 2.18 mm WCSP and 4 mm × 4 mm Thin QFN packages. The TPA4411M is available in a 4 mm × 4 mm Thin QFN package. The TPA4411RTJ package is a thermally optimized PowerPAD™ package allowing the maximum amount of thermal dissipation and the TPA4411MRTJ is a thermally enhanced PowerPAD package designed to match competitive package footprints.
APPLICATIONS
• • • • • Notebook Computers CD / MP3 Players Smart Phones Cellular Phones PDAs
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, DirectPath are trademarks of Texas Instruments.
Copyright © 2004–2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TPA4411 TPA4411M
SLOS430E – AUGUST 2004 – REVISED MARCH 2008
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
RTJ (QFN) PACKAGE (TOP VIEW)
SGND
SGND
17
PVDD
PVDD
SDL
NC
NC
NC
SDL
20
19
18
17
16
20
19
18
C1P PGND C1N NC PVSS
1 2 3 4 5
15 14 13 12 11
INR SDR INL NC OUTR
C1P PGND C1N NC PVSS
16
NC
1 2 3 4 5
15 14 13 12 11
INR SDR INL NC OUTR
10
SVDD
NC
NC
TPA4411RTJ
NC − No internal connection
TPA4411MRTJ
NC − No internal connection
YZH (WCSP) PACKAGE (TOP VIEW)
A2 A1
A3
A4
INR
SGND
PVDD
C1P
B1
SDR
SDL
NC
PGND
C1
INL
OUTR
NC
C1N
D1
SVDD
OUTL
SVSS
PVSS
TPA4411YZH
NC - No internal connection
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SVDD
NC
SVSS
OUTL
SVSS
NC
OUTL
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TPA4411 TPA4411M
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SLOS430E – AUGUST 2004 – REVISED MARCH 2008
TERMINAL FUNCTIONS
TERMINAL NAME C1P PGND C1N NC PVSS SVSS OUTL SVDD OUTR INL SDR INR SGND SDL PVDD Exposed Pad QFN 1 2 3 4, 6, 8, 12, 16, 20 5 7 9 10 11 13 14 15 17 18 19 WCSP A4 B4 C4 B3, C3 D4 D3 D2 D1 C2 C1 B1 A1 A2 B2 A3 O I O I O I I I I I I I/O DESCRIPTION I/O Charge pump flying capacitor positive terminal I Power ground, connect to ground. I/O Charge pump flying capacitor negative terminal No connection Output from charge pump. Amplifier negative supply, connect to PVSS via star connection. Left audio channel output signal Amplifier positive supply, connect to PVDD via star connection. Right audio channel output signal Left audio channel input signal Right channel shutdown, active low logic. Right audio channel input signal Signal ground, connect to ground. Left channel shutdown, active low logic. Supply voltage, connect to positive supply. Exposed pad must be soldered to a floating plane. Do NOT connect to power or ground.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range, TA = 25°C (unless otherwise noted)
VALUE / UNIT Supply voltage, AVDD, PVDD VI TA TJ Tstg Input voltage Output Continuous total power dissipation Operating free-air temperature range Operating junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) –0.3 V to 5.5 V –0.3 V to VDD + 0.3 V See Dissipation Rating Table –40°C to 85°C –40°C to 150°C –65°C to 150°C 260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2004–2008, Texas Instruments Incorporated
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DISSIPATION RATINGS TABLE
PACKAGE RTJ (TPA4411) RTJ (TPA4411M) YZH (1) TA ≤ 25°C POWER RATING 5200 mW 3450 mW 1200 mW DERATING FACTOR (1) 41.6 mW/°C 34.5 mW/°C 9.21 mW/°C TA = 70°C POWER RATING 3120 mW 1898 mW 690 mW TA = 85°C POWER RATING 2700 mW 1380 mW 600 mW
Derating factor measured with High K board.
AVAILABLE OPTIONS
TA –40°C to 85°C PACKAGED DEVICES (1) 20-pin, 4 mm × 4 mm QFN 20-pin, 4 mm × 4 mm QFN 16-ball, 2.18 mm × 2.18 mm WSCP (1) (2) PART NUMBER TPA4411RTJ (2) TPA4411MRTJ (2) TPA4411YZH SYMBOL AKQ BPB AKT
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The RTJ package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g., TPA4411RTJR).
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, AVDD, PVDD VIH VIL TA (1) High-level input voltage Low-level input voltage SDL, SDR SDL, SDR –40 1.8 1.5 0.5 85 MAX 4.5 (1) UNIT V V V °C
Operating free-air temperature Device can shut down for VDD > 4.5 V to prevent damage to the device.
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER |VOS| PSRR VOH VOL |IIH| |IIL| Output offset voltage Power Supply Rejection Ratio High-level output voltage Low-level output voltage High-level input current (SDL, SDR) Low-level input current (SDL, SDR) TEST CONDITIONS VDD = 1.8 V to 4.5 V, Inputs grounded VDD = 1.8 V to 4.5 V VDD = 3 V, RL = 16 Ω VDD = 3 V, RL = 16 Ω VDD = 4.5 V, VI = VDD VDD = 4.5 V, VI = 0 V VDD = 1.8 V, No load, SDL= SDR = VDD IDD Supply Current VDD = 3 V, No load, SDL = SDR = VDD VDD = 4.5 V, No load, SDL = SDR = VDD Shutdown mode, VDD = 1.8 V to 4.5 V 5.3 6.5 8.0 –69 2.2 –1.1 1 1 6.5 8.0 10.0 1 µA mA –80 MIN TYP MAX 8 UNIT mV dB V V µA µA
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SLOS430E – AUGUST 2004 – REVISED MARCH 2008
OPERATING CHARACTERISTICS
VDD = 3 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS THD = 1%, VDD = 3 V, f = 1 kHz PO Output power (Outputs In Phase) THD = 1%, VDD = 4.5 V, f = 1 kHz THD = 1%, VDD = 3 V, f = 1 kHz, RL = 32 Ω THD+N Total harmonic distortion plus noise Crosstallk kSVR Av ΔAv Supply ripple rejection ratio Closed-loop voltage gain Gain matching Slew rate Maximum capacitive load Vn fosc Noise output voltage Electrostatic discharge, IEC Charge pump switching frequency Start-up time from shutdown Input impedance SNR Signal-to-noise ratio Thermal shutdown Po = 40 mW (THD+N = 0.1%) Threshold Hysteresis 150 15 12 OUTR, OUTL 280 PO = 25 mW, f = 1 kHz PO = 25 mW, f = 20 kHz PO = 20 mW, f = 1 kHz 200-mVpp ripple, f = 217 Hz 200-mVpp ripple, f = 1 kHz 200-mVpp ripple, f = 20 kHz –1.45 MIN TYP 50 100 50 0.054% 0.010% –83 –82.5 –70.4 –45.1 –1.5 1% 2.2 400 10 ±8 320 450 15 98 170 18 420 V/µs pF µVRMS kV kHz µs kΩ dB °C °C –1.55 V/V dB dB mW MAX UNIT
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Functional Block Diagram
TPA4411 SVDD Audio In − R _ + SGND SVSS SVDD + _ SVSS Short Circuit Protection Audio Out − L Audio Out − R
Audio In − L
Av = −1.5 V/V Bias Circuitry Charge Pump
C1P
SDx
C1N PVSS
APPLICATION CIRCUIT
HPL or SPK1 HPR or SPK2
TLV320AIC26 or TLV320AIC28
TPA2012D2
Shutdown Control
SDL SDR INR TPA4411
PGND SGND OUTL OUTR
INL 1.8 − 4.5 V PVDD SVDD C1P C1N
PVSS SVSS
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SLOS430E – AUGUST 2004 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS
C(PUMP) = C(PVSS) = 2.2 µF , CIN = 1 µF (unless otherwise noted)
Table of Graphs
FIGURE Total harmonic distortion + noise Total harmonic distortion + noise Supply voltage rejection ratio Power dissipation Crosstalk Output power Quiescent supply current Output power Output spectrum Gain and phase TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
vs Output power vs Frequency vs Frequency vs Output power vs Frequency vs Supply voltage vs Supply voltage vs Load resistance vs Frequency TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
VDD = 1.8 V, RL = 16 Ω, fIN = 1 kHz 10 180° Out of Phase
THD+N − Total Harmonic Distortion + Noise − %
1–24 25–32 33, 34 35–42 43–46 47–50 51 5–60 61 62, 63 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 1.8 V, RL = 16 Ω, fIN = 10 kHz 10 180° Out of Phase In Phase
100 VDD = 1.8 V, RL = 16 Ω, fIN = 20 Hz In Phase
100
10
1 Single Channel
1
In Phase
1
0.1
0.01 180° Out of Phase 0.001 1 10 PO − Output Power − mW 30
0.1 Single Channel 0.01 1 10 PO − Output Power − mW 30
0.1
Single Channel 0.01 1 10 PO − Output Power − mW 30
Figure 1. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
Figure 2. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
Figure 3. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 1.8 V, RL = 32 Ω, fIN = 10 kHz 10 180° Out of Phase 1
THD+N − Total Harmonic Distortion + Noise − %
100 VDD = 1.8 V, RL = 32 Ω, fIN = 20 Hz In Phase
100 VDD = 1.8 V, RL = 32 Ω, fIN = 1 kHz 10 In Phase
10
In Phase
180° Out of Phase 1 Single Channel
180° Out of Phase Single Channel
1
Single Channel
0.1
0.1
0.1
0.01
0.001 1 10 PO − Output Power − mW 30
0.01
0.01 1 10 PO − Output Power − mW 30
1
10 PO − Output Power − mW
30
Figure 4.
Figure 5.
Figure 6.
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TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 3 V, RL = 16 Ω, fIN = 10 kHz In Phase
100 VDD = 3 V, RL = 16 Ω, fIN = 20 Hz In Phase
100 VDD = 3 V, RL = 16 Ω, fIN = 1 kHz 10 In Phase
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10
1
1 180° Out of Phase
1
180° Out of Phase
0.1
180° Out of Phase
0.01 Single Channel 0.001 1 10 100 PO − Output Power − mW 300
0.1 Single Channel 0.01 1 10 100 PO − Output Power − mW 300
0.1 Single Channel 0.01 1 10 100 300 PO − Output Power − mW
Figure 7. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − %
Figure 8. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
Figure 9. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 3 V, RL = 32 Ω, fIN = 10 kHz In Phase
100 VDD = 3 V, RL = 32 Ω, fIN = 20 Hz In Phase
100 VDD = 3 V, RL = 32 Ω, fIN = 1 kHz 10 Single Channel 1 180° Out of Phase 0.1 In Phase
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10
180° Out of Phase 1
1
0.1 Single Channel 0.01
0.1 Single Channel 0.01 180° Out of Phase 0.001 1 10 100 300 PO − Output Power − mW
0.001 1 10 100 PO − Output Power − mW 300
0.01 1 10 100 300 PO − Output Power − mW
Figure 10. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
100 VDD = 3.6 V, RL = 16 Ω, fIN = 20 Hz In Phase
Figure 11. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
Figure 12. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 3.6 V, RL = 16 Ω, fIN = 10 kHz 10 In Phase
100 VDD = 3.6 V, RL = 16 Ω, fIN = 1 kHz 10 In Phase
10
180° Out of Phase
180° Out of Phase
180° Out of Phase
1 Single Channel 0.1
1 Single Channel 0.1
1 Single Channel 0.1
0.01
0.001 1 10 100 300 PO − Output Power − mW
0.01 1 10 100 300 PO − Output Power − mW
0.01 1 10 100 300 PO − Output Power − mW
Figure 13.
Figure 14.
Figure 15.
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SLOS430E – AUGUST 2004 – REVISED MARCH 2008
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 3.6 V, RL = 32 Ω, fIN = 1 kHz 10 180° Out of Phase 1 In Phase
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − % 100 VDD = 3.6 V, RL = 32 Ω, fIN = 10 kHz In Phase
100 VDD = 3.6 V, RL = 32 Ω, fIN = 20 Hz In Phase
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10
180° Out of Phase 1
180° Out of Phase 1
0.1 Single Channel 0.01
0.1
0.1
Single Channel
0.01 Single Channel 0.001 1 10 100 300 PO − Output Power − mW
0.001 1 10 100 300 PO − Output Power − mW
0.01 1 10 100 300 PO − Output Power − mW
Figure 16. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − % 100 VDD = 4.5 V, RL = 16 Ω, fIN = 20 Hz In Phase 100 VDD = 4.5 V, RL = 16 Ω, fIN = 1 k Hz 10
Figure 17. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
100
Figure 18. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
VDD = 4.5 V, RL = 16 Ω, fIN = 10 k Hz 10 180° Out of Phase 1
In Phase
10
180° Out of Phase
In Phase
1 Single Channel 0.1
180° Out of Phase 1 Single Channel 0.1
0.1 Single Channel 0.01 1 10 100 300 PO − Output Power − mW
0.01
0.001 1 10 100 300 PO − Output Power − mW
0.01 1 10 100 300 PO − Output Power − mW
Figure 19. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 100 VDD = 4.5 V, RL = 32 Ω, fIN = 20 Hz
Figure 20. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
100 100 VDD = 4.5 V, RL = 32 Ω, fIN = 10 kHz 10 VDD = 4.5 V, RL = 32 Ω, fIN = 1 kHz
Figure 21. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
In Phase
10
In Phase
10
In Phase
1 Single Channel 0.1 180° Out of Phase 0.01
1 180° Out of Phase 0.1 Single Channel
1
180° Out of Phase 0.1
0.001 1 10 100 300 PO − Output Power − mW
0.01 1 10 100 300 PO − Output Power − mW
0.01 1
Single Channel 10 100 300
PO − Output Power − mW
Figure 22.
Figure 23.
Figure 24.
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TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
1
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − %
1 VDD = 1.8 V RL = 32 Ω PO = 2 mW 1
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
VDD = 3 V RL = 16 Ω P O = 5 mW 0.1
VDD = 1.8 V RL = 16 Ω PO = 1 mW
0.1 P O = 3 mW 0.01 PO = 2 mW
0.1 PO = 6 mW
PO = 40 mW 0.01 PO = 25 mW
0.01 PO = 5 mW
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
0.001
10
100
1k
10 k
100 k
f − Frequency − Hz
Figure 25. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − %
Figure 26. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
Figure 27. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
1 VDD = 3.6 V RL = 32 Ω P O = 5 mW PO = 35 mW 0.1
1 VDD = 3 V RL = 32 Ω PO = 5 mW 0.1 PO = 25 mW
1 VDD = 3.6 V RL = 16 Ω PO = 5 mW 0.1 PO = 40 mW
PO = 70 mW 0.01
0.01 PO = 45 mW
0.01
PO = 20 mW
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
Figure 28. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
Figure 29. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
k SVR − Supply Voltage Rejection Ratio − V
1 VDD = 4.5 V RL = 32 Ω PO = 5 mW 0.1 PO = 80 mW
Figure 30. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 10 100 1k 10 k 100 k 3.6 V 1.8 V 4.5 V 3V RL = 16 Ω
1 VDD = 4.5 V RL = 16 Ω PO = 50 mW
0.1
PO = 35 mW
PO = 25 mW 0.01
0.01 PO = 25 mW PO = 5 mW
PO = 50 mW 0.001 10 100 1k 10 k 100 k f − Frequency − Hz
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
f − Frequency − Hz
Figure 31.
Figure 32.
Figure 33.
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SLOS430E – AUGUST 2004 – REVISED MARCH 2008
SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
k SVR − Supply Voltage Rejection Ratio − V
POWER DISSIPATION vs OUTPUT POWER
80
P D − Power Dissipation − mW
POWER DISSIPATION vs OUTPUT POWER
60
P D − Power Dissipation − mW
0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 10
RL = 32 Ω
70 60 50 40 30 20 10 0 0
In Phase 180° Out of Phase
50 40
In Phase
180° Out of Phase
30
3V 1.8 V 4.5 V
20 10 VDD = 1.8 V, RL = 32 Ω 0 5 10 15 20 25 30 35 40
VDD = 1.8 V, RL = 16 Ω 5 10 15 20 25 30
3.6 V 100 1k 10 k 100 k f − Frequency − Hz
0
PO − Output Power − mW
PO − Output Power − mW
Figure 34. POWER DISSIPATION vs OUTPUT POWER
300
P D − Power Dissipation − mW
160
Figure 35. POWER DISSIPATION vs OUTPUT POWER
400
In Phase
Figure 36. POWER DISSIPATION vs OUTPUT POWER
In Phase 350 300 180° Out of Phase 250 200 150 100 50 0 VDD = 3.6 V, RL = 16 Ω 0 50 100 150 200 250 PO − Output Power − mW 300
120 100 80 60 40 20 0
200
180° Out of Phase
180° Out of Phase
150 100 50 0 VDD = 3 V, RL = 16 Ω 0 50 100 150 200
VDD = 3 V, RL = 32 Ω 0 50 100 150 200
PO − Output Power − mW
PO − Output Power − mW
Figure 37. POWER DISSIPATION vs OUTPUT POWER
250
PD − Power Dissipation − mW
PD − Power Dissipation − mW
Figure 38. POWER DISSIPATION vs OUTPUT POWER
600
P D − Power Dissipation − mW 350
P D − Power Dissipation − mW
250
P D − Power Dissipation − mW
In Phase
140
Figure 39. POWER DISSIPATION vs OUTPUT POWER
300 250 200 VDD = 4.5 V, RL = 32 Ω In Phase
In Phase 200
VDD = 4.5 V, RL = 16 Ω 500 In Phase
400 300 200
150
180° Out of Phase
180° Out of Phase
180° Out of Phase
100
150 100 50 0
50 VDD = 3.6 V, RL = 32 Ω 0 0 50 100 150 200 250 300 350 PO − Output Power − mW
100 0 0
50
100
150
200
250
0
50
PO − Output Power − mW
100 150 200 250 PO − Output Power − mW
300
Figure 40.
Figure 41.
Figure 42.
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CROSSTALK vs FREQUENCY
0 VDD = 3 V, PO = 1.6 mW RL = 16 Ω
0 −20 −40
CROSSTALK vs FREQUENCY
0 VDD = 3 V, PO = 20 mW RL = 16 Ω
Crosstalk − dB
CROSSTALK vs FREQUENCY
VDD = 3.6 V, PO = 1.6 mW RL = 16 Ω
−20
Crosstalk − dB
−20 −40
−40
Crosstalk − dB
−60 −80
−60 Left to Right −80
Left to Right
−60 Left to Right −80 −100 −120 10
−100 −120 10
Right to Left
−100 −120
Right to Left
Right to Left 100 1k 10 k
100
1k
10 k
100 k
10
100
1k
10 k
100 k
100 k
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 43. CROSSTALK vs FREQUENCY
0 −20
Crosstalk − dB
Figure 44. OUTPUT POWER vs SUPPLY VOLTAGE
120
Figure 45. OUTPUT POWER vs SUPPLY VOLTAGE
250 THD = 10 % RL = 16 Ω
PO − Output Power − mW
VDD = 3.6 V, PO = 20 mW RL = 16 Ω
PO − Output Power − mW
THD = 1 % RL = 16 Ω 100 180° Out of Phase
200 180° Out of Phase 150
−40
80
−60 Left to Right −80
60 40 In Phase
100 In Phase 50
−100 −120 10
Right to Left
20 0 1.8 2.3 2.8 3.3 3.8 VDD − Supply Voltage − V 4.3
100
1k
10 k
100 k
0 1.8 2.3 2.8 3.3 3.8 VDD − Supply Voltage − V 4.3
f − Frequency − Hz
Figure 46. OUTPUT POWER vs SUPPLY VOLTAGE
160 140
PO − Output Power − mW
Figure 47. OUTPUT POWER vs SUPPLY VOLTAGE
250 I DD − Quiescent Supply Current − mA
10
Figure 48. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
9 8 7 6 5 4 3 2 1 0 0 1 1.5 2 2.5 3 3.5 4 4.5 5
THD = 1 % RL = 32 Ω
PO − Output Power − mW
THD = 10 % RL = 32 Ω 200 180° Out of Phase 150
120 100 80 60 40 20 0
180° Out of Phase
100 In Phase 50
In Phase
0 1.8 2.3 2.8 3.3 3.8 4.3 1.8 VDD − Supply Voltage − V 2.3 2.8 3.3 3.8 VDD − Supply Voltage − V 4.3
VDD − Supply Voltage − V
Figure 49.
Figure 50.
Figure 51.
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OUTPUT POWER vs LOAD RESISTANCE
120 110 1 µF 0.68 µF
PO − Output Power − mW
OUTPUT POWER vs LOAD RESISTANCE
30 VDD = 1.8 V, THD = 1%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase
OUTPUT POWER vs LOAD RESISTANCE
40 35
PO − Output Power − mW
2.2 µF
PO − Output Power − mW
100 90 80 70 60 50 40 30 0 10 20 30 40 RL − Load Resistance − Ω 50 In Phase, VDD = 3 V, THD = 1%, Vary C(PUMP) 0.47 µF
25 20
VDD = 1.8 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase
30 25 20 15 In Phase 10 5 0 10
15
10 In Phase 5 0 10
100
1000
10000
100
1000
10000
RL − Load Resistance − Ω
RL − Load Resistance − Ω
Figure 52. OUTPUT POWER vs LOAD RESISTANCE
160 140 VDD = 3 V, THD = 1%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase 250
Figure 53. OUTPUT POWER vs LOAD RESISTANCE
VDD = 3 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase 150 250
Figure 54. OUTPUT POWER vs LOAD RESISTANCE
VDD = 3.6 V, THD = 1%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase 150
PO − Output Power − mW
PO − Output Power − mW
PO − Output Power − mW
200
200
120 100 80 60 40 20 0 10 In Phase
100 In Phase 50
100 In Phase 50
0 100 1000 RL − Load Resistance − Ω 10000 10 100 1000 10000 RL − Load Resistance − Ω
0 10
100
1000
10000
RL − Load Resistance − Ω
Figure 55. OUTPUT POWER vs LOAD RESISTANCE
350 300
PO − Output Power − mW
Figure 56. OUTPUT POWER vs LOAD RESISTANCE
350 500 VDD = 4.5 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase 450
PO − Output Power − mW
Figure 57. OUTPUT POWER vs LOAD RESISTANCE
VDD = 4.5 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR Out of Phase
250 Out of Phase 200 150 In Phase 100 50 0 10 100 1000 10000 RL − Load Resistance − Ω
PO − Output Power − mW
VDD = 3.6 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR
300 250 200 150 In Phase 100 50
400 350 300 250 200 150 100 50 In Phase
0 10 100 1000 10000 RL − Load Resistance − Ω
0 10 100 1000 10000 RL − Load Resistance − Ω
Figure 58.
Figure 59.
Figure 60.
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OUTPUT SPECTRUM
20 0
Output Spectrum − dBv
GAIN AND PHASE vs FREQUENCY
3.5 3 2.5
GAIN AND PHASE vs FREQUENCY
100 3.5 3 2.5 Gain 100 80
Phase − Degrees
−20 −40
VO = 1 VRMS VDD = 3 V fIN = 1 kHz RL = 32 Ω
Gain
80 60
60 40 20 Phase 0 VCC = 3 V, RL = 16 Ω 100 1k 10 k 100 k -20 -40 1G
Phase − Degrees
Gain − dB
−60 −80 −100 −120 −140 −160 10 100 1k 10 k 100 k f − Frequency − Hz
2
40 20 Phase 0 VCC = 3.6 V, RL = 16 Ω 100 1k 10 k 100 k -20 -40 1G
Gain − dB
2 1.5 1 0.5 0 10
1.5 1 0.5 0 10
f − Frequency − Hz
f − Frequency − Hz
Figure 61.
Figure 62.
Figure 63.
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APPLICATION INFORMATION Headphone Amplifiers
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, the output signal is severely clipped, and large amounts of dc current rush through the headphones, potentially damaging them. The top drawing in Figure 64 illustrates the conventional headphone amplifier connection to the headphone jack and output signal. DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32 Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between the load impedance L), the capacitor O), and the cutoff frequency (fC). 1 fc = 2pRLCO (1) CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known. 1 CO = 2pRLfc
(2)
If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal. Two different headphone amplifier applications are available that allow for the removal of the output dc blocking capacitors. The Capless amplifier architecture is implemented in the same manner as the conventional amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do not connect the shield to any GND reference or large currents will result. The scenario can happen if, for example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the second block diagram and waveform in Figure 64.
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Conventional CO VOUT CO GND Capless VDD VOUT GND VBIAS DirectPathTM VDD VBIAS VDD VDD/2
GND
VSS
Figure 64. Amplifier Applications The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and waveform of Figure 64 illustrate the ground-referenced headphone architecture. This is the architecture of the TPA4411.
Input-Blocking Capacitors
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the TPA4411 and TPA4411M. These capacitors block the DC portion of the audio source and allow the TPA4411 and TPA4411M inputs to be properly biased to provide maximum performance. These capacitors form a high-pass filter with the input impedance of the TPA4411 and TPA4411M. The cutoff frequency is calculated using Equation 3. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the input impedance of the TPA4411 or TPA4411M. Because the gains of both the TPA4411 and TPA4411M are fixed, the input impedance remains a constant value. Using the input impedance value from the operating characteristics table, the frequency and/or capacitance can be determined when one of the two values are given. 1 1 fc IN + or C IN + 2p fc R 2p RIN C IN IN IN (3)
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Charge Pump Flying Capacitor and PVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 2.2 µF is typical. Capacitor values that are smaller than 2.2 µF can be used, but the maximum output power is reduced and the device may not operate to specifications. Figure 65 through Figure 75 compare the performance of the TPA4411 and TPA4411M with the recommended 2.2-µF capacitors and 1-µF capacitors.
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − % 1 VDD = 3.6 V, RL = 32 Ω, PO = 35 mW,
0.1
C = 1 µF
0.01 C = 2.2 µF
0.001 10 100 1k 10 k 100 k f − Frequency − Hz
Figure 65. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − % VDD = 3.6 V, RL = 16 Ω, fIN = 20 HZ C = 1 µF 180° Out of Phase 10
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 3.6 V, RL = 16 Ω, fIN = 20 Hz C = 2.2 µF In Phase
100
10
180° Out of Phase 1 Single Channel 0.1
In Phase 1 Single Channel
0.01
0.1 0.0001
0.001
0.01
0.1
1
0.001 0.001
0.01
0.1
PO − Output Power − mW
PO − Output Power − mW
Figure 66.
Figure 67.
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TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100 VDD = 3.6 V, RL = 16 Ω, fIN = 1 kHz C = 2.2 µF 10 In Phase
100
VDD = 3.6 V, RL = 16 Ω, fIN = 1 kHZ C = 1 µF
Single Channel In Phase
10
180° Out of Phase
1
180° Out of Phase 0.1
1 Single Channel 0.1
0.01 0.0001
0.001
0.1 PO − Output Power − mW
0.01
1
0.01 0.001
0.01
0.1
PO − Output Power − mW
Figure 68. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − %
Figure 69. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
100
VDD = 3.6 V, RL = 16 Ω, fIN = 10 kHz C = 2.2 µF In Phase
100 VDD = 3.6 V, RL = 16 Ω, fIN = 10 kHZ C = 1 µF In Phase 1 180° Out of Phase 0.1
10
10
180° Out of Phase
1
Single Channel 0.1
0.01 Single Channel 0.001 0.0001 0.001 0.01 0.1 1
0.01 0.001
0.01
0.1
PO − Output Power − mW
PO − Output Power − mW
Figure 70. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
Figure 71. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
100
VDD = 3.6 V, RL = 32 Ω, fIN = 20 HZ C = 1 µF In Phase
100
10
VDD = 3.6 V, RL = 32 Ω, fIN = 20 Hz C = 2.2 µF
In Phase
10
180° Out of Phase 1
Single Channel 1 180° Out of Phase
0.1 Single Channel 0.01
0.1 0.0001
0.001 0.01 0.1 PO − Output Power − mW
1
0.001 0.001
0.01
0.1
PO − Output Power − mW
Figure 72.
Figure 73.
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SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
k SVR − Supply Voltage Rejection Ratio − V
k SVR − Supply Voltage Rejection Ratio − V
SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 10 3.6 V 100 1k 10 k 100 k f − Frequency − Hz 1.8 V 3V 4.5 V RL = 32 Ω C = 2.2 µF
0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 10 100 1k 10 k 100 k f − Frequency − Hz VDD = 3.6 V, RL = 32 Ω, C = 1 µF
Figure 74.
Figure 75.
Decoupling Capacitors
The TPA4411 and TPA4411M are DirectPath™ headphone amplifiers that require adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 2.2 µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the TPA4411 or TPA4411M is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device.
Supply Voltage Limiting At 4.5 V
The TPA4411 and TPA4411M have a built-in charge pump which serves to generate a negative rail for the headphone amplifier. Because the headphone amplifier operates from a positive voltage and negative voltage supply, circuitry has been implemented to protect the devices in the amplifier from an overvoltage condition. Once the supply is above 4.5 V, the TPA4411 and TPA4411M can shut down in an overvoltage protection mode to prevent damage to the device. The TPA4411 and TPA4411M resume normal operation once the supply is reduced to 4.5 V or lower.
Layout Recommendations
Exposed Pad On TPA4411RTJ and TPA4411MRTJ Package Option The exposed metal pad on the TPA4411RTJ and TPA4411MRTJ packages must be soldered down to a pad on the PCB in order to maintain reliability. The pad on the PCB should be allowed to float and not be connected to ground or power. Connecting this pad to power or ground prevents the device from working properly because it is connected internally to PVSS. TPA4411RTJ and TPA441MRTJ PowerPAD Sizes Both the TPA4411 and TPA4411M are available in a 4 mm × 4mm QFN. The exposed pad on the bottom of the package is sized differently between the two devices. The TPA4411RTJ PowerPAD is larger than the TPA4411MRTJ PowerPAD. Please see the layout and mechanical drawings at the end of the datasheet for proper sizing. SGND and PGND Connections The SGND and PGND pins of the TPA4411 and TPA4411M must be routed separately back to the decoupling capacitor in order to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and THD performance do not meet the specifications.
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CODEC HPL or SPK1 HPR or SPK2
PVDD INL− INL+
AVDD
TLV320AIC26 or TLV320AIC28
PGND TPA2012D2 INR− INR+ AGND SDR SDL Gain0 Gain1
Control SDL SDR 1 mF INR VCC 1 mF OUTR INL PVDD SVDD 2.2 mF C1P C1N 2.2 mF PVSS SVSS TPA4411 OUTL PGND SGND
2.2 mF
Figure 76. Application Circuit
1.8 − 4.5 V
20 19 18 17
Shutdown Control
16
C1 2.2 mF C2 2.2 mF
1 15 2 14
C5 Right Audio Input 1 mF Shutdown Control 1 mF
13
3
− C3 2.2 mF
4
+
+
−
12
Left Audio Input C4
5
11
10
6
7
8
9
No Output DC-Blocking Capacitors Note: PowerPAD must be soldered down and plane must be floating.
Figure 77. Typical Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Apr-2009
PACKAGING INFORMATION
Orderable Device TPA4411MRTJR TPA4411MRTJRG4 TPA4411MRTJT TPA4411MRTJTG4 TPA4411RTJR TPA4411RTJRG4 TPA4411RTJT TPA4411RTJTG4 TPA4411YZHR TPA4411YZHT
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type QFN QFN QFN QFN QFN QFN QFN QFN DSBGA DSBGA
Package Drawing RTJ RTJ RTJ RTJ RTJ RTJ RTJ RTJ YZH YZH
Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 16 16 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI
MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM
3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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16-Mar-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing QFN QFN QFN QFN DSBGA DSBGA DSBGA DSBGA RTJ RTJ RTJ RTJ YZH YZH YZH YZH 20 20 20 20 16 16 16 16
SPQ
Reel Reel Diameter Width (mm) W1 (mm) 330.0 180.0 330.0 180.0 180.0 180.0 180.0 180.0 12.4 12.4 12.4 12.4 8.4 8.4 8.4 8.4
A0 (mm)
B0 (mm)
K0 (mm)
P1 (mm) 8.0 8.0 8.0 8.0 4.0 4.0 4.0 4.0
W Pin1 (mm) Quadrant 12.0 12.0 12.0 12.0 8.0 8.0 8.0 8.0 Q1 Q1 Q2 Q2 Q1 Q1 Q1 Q1
TPA4411MRTJR TPA4411MRTJT TPA4411RTJR TPA4411RTJT TPA4411YZHR TPA4411YZHR TPA4411YZHT TPA4411YZHT
3000 250 3000 250 3000 3000 250 250
4.3 4.3 4.3 4.3 2.38 2.35 2.35 2.38
4.3 4.3 4.3 4.3 2.4 2.35 2.35 2.4
1.5 1.5 1.5 1.5 0.8 0.81 0.81 0.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Mar-2009
*All dimensions are nominal
Device TPA4411MRTJR TPA4411MRTJT TPA4411RTJR TPA4411RTJT TPA4411YZHR TPA4411YZHR TPA4411YZHT TPA4411YZHT
Package Type QFN QFN QFN QFN DSBGA DSBGA DSBGA DSBGA
Package Drawing RTJ RTJ RTJ RTJ YZH YZH YZH YZH
Pins 20 20 20 20 16 16 16 16
SPQ 3000 250 3000 250 3000 3000 250 250
Length (mm) 346.0 190.5 346.0 190.5 190.5 220.0 220.0 190.5
Width (mm) 346.0 212.7 346.0 212.7 212.7 220.0 220.0 212.7
Height (mm) 29.0 31.8 29.0 31.8 31.8 34.0 34.0 31.8
Pack Materials-Page 2
D: Max = 2196 µm, Min = 2136 µm E: Max = 2196 µm, Min = 2136 µm
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