TPA6132A2

TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 25-mW DIRECTPATH™ STEREO HEADPHONE AMPLIFIER WITH POP SUPPRESSION 1 FEATURES DESCRIPTION The TPA6132A2 (sometimes referred to as TPA6132) is a DirectPath™ stereo headphone amplifier that eliminates the need for external dc-blocking output capacitors. Differential stereo inputs and built-in resistors set the device gain, further reducing external component count. Gain is selectable at –6 dB, 0 dB, 3 dB or 6 dB. The amplifier drives 25 mW into 16 Ω speakers from a single 2.3 V supply. The TPA6132A2 (TPA6132) provides a constant maximum output power independent of the supply voltage, thus facilitating the design for prevention of acoustic shock. The TPA6132A2 (TPA6132) features fully differential inputs to reduce system noise pickup between the audio source and the headphone amplifier. The high power supply noise rejection performance and differential architecture provides increased RF noise immunity. For single-ended input signals, connect INL+ and INR+ to ground. The device has built-in pop suppression circuitry to completely eliminate disturbing pop noise during turn-on and turn-off. The amplifier outputs have short-circuit and thermal-overload protection along with ±8 kV HBM ESD protection, simplifying end equipment compliance to the IEC 61000-4-2 ESD standard. The TPA6132A2 (TPA6132) operates from a single 2.3 V to 5.5 V supply with 2.1 mA of typical supply current. Shutdown mode reduces supply current to less than 1 µA. OUTR+ OUTRCODEC OUTL+ OUTLENABLE GAIN0 GAIN1 VBAT INL+ INLSGND EN G0 G1 VDD HPVDD CPP CPN PGND INR+ INRTPA6132A2 OUTL OUTR • Patented DirectPath™ Technology Eliminates Need for DC-Blocking Capacitors – Outputs Biased at 0 V – Excellent Low Frequency Fidelity • Active Click and Pop Suppression • 2.1 mA Typical Supply Current • Fully Differential or Single-Ended Inputs – Built-In Resistors Reduces Component Count – Improves System Noise Performance • Constant Maximum Output Power from 2.3 V to 5.5 V Supply – Simplifies Design to Prevent Acoustic Shock • Improved RF Noise Immunity • MicrosoftTM Windows VistaTM Compliant • High Power Supply Noise Rejection – 100 dB PSRR at 217 Hz – 90 dB PSRR at 10 kHz • Wide Power Supply Range: 2.3 V to 5.5 V • Gain Settings: –6 dB, 0 dB, 3 dB, and 6 dB • Short-Circuit and Thermal-Overload Protection • ±8 kV HBM ESD Protected Outputs • Small Package Available – 16-Pin, 3 mm × 3 mm Thin QFN 23 APPLICATIONS • • • • Smart Phones / Cellular Phones Notebook Computers CD / MP3 Players Portable Gaming HPVSS 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath is a trademark of Texas Instruments. Windows Vista is a trademark of Microsoft Corporation. Copyright © 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM VDD HPVDD Supply Control HPVDD + Resistor Array – INLINL+ 2.2 mF PGND OUTL Short-Circuit Protection Thermal Protection OUTR HPVDD CPP HPVSS HPVDD INRINR+ + HPVSS Click-and-Pop Suppression Resistor Array – G0 G1 Gain Select Charge Pump CPN HPVSS 1 mF 1 mF SGND EN 2 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 DEVICE PINOUT RTE (QFN) PACKAGE (TOP VIEW) OUTL SGND VDD 14 16 15 INL- 1 INL+ 2 INR+ 3 INR- 4 6 7 5 8 13 12 11 10 9 EN HPVDD CPP PGND CPN G0 OUTR G1 PIN FUNCTIONS PIN NAME INLINL+ INR+ INROUTR G0 G1 HPVSS CPN PGND CPP HPVDD EN VDD SGND OUTL Thermal Pad QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 – I/O/P I I I I O I I P P P P P I P I O P PIN DESCRIPTION Inverting left input for differential signals; left input for single-ended signals Non-inverting left input for differential signals. Connect to ground for single-ended input applications Non-inverting right input for differential signals. Connect to ground for single-ended input applications Inverting right input for differential signals; right input for single-ended signals Right headphone amplifier output. Connect to right terminal of headphone jack Gain select Gain select Charge pump output and negative power supply for output amplifiers; connect 1µF capacitor to GND Charge pump negative flying cap. Connect to negative side of 1µF capacitor between CPP and CPN Ground Charge pump positive flying cap. Connect to positive side of 1µF capacitor between CPP and CPN Positive power supply for headphone amplifiers. Connect to a 2.2µF capacitor. Do not connect to VDD Amplifier enable. Connect to logic low to shutdown; connect to logic high to activate Positive power supply for TPA6132A2 Amplifier reference voltage. Connect to ground terminal of headphone jack Left headphone amplifier output. Connect to left terminal of headphone jack Solder the exposed metal pad on the TPA6132A2RTE QFN package to the landing pad on the PCB. Connect the landing pad to ground or leave it electrically unconnected (floating). HPVSS Copyright © 2008, Texas Instruments Incorporated 3 Product Folder Link(s) :TPA6132A2 TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com BOARD LAYOUT CONCEPT Enable Control To Battery 16 15 14 13 2.2 mF 12 2.2 mF 1 2 3 4 Paddle Soldered / Electrical Float Matched Board Layout for Differential Input Signals 11 10 9 1 mF 5 6 7 8 Gain Control 1 mF ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range, TA = 25°C (unless otherwise noted) VALUE / UNIT Supply voltage, VDD Headphone amplifier supply voltage, HPVDD (do not connect to external supply) VI TA TJ Input voltage (INR+, INR-, INL+, INL-) Output continuous total power dissipation Operating free-air temperature range Operating junction temperature range OUTL, OUTR All Other Pins –0.3 V to 6.0 V –0.3 V to 1.9 V HPVSS –0.3 V to HPVDD + 0.3 V See Dissipation Rating Table –40°C to 85°C –40°C to 150°C –65°C to 85°C 8 kV 2 kV Tstg Storage temperature range ESD Protection – HBM ORDERING GUIDE TA –40°C to 85°C (1) (2) PACKAGED DEVICES (1) 16-pin, 3 mm × 3 mm Thin QFN PART NUMBER (2) TPA6132A2RTER TPA6132A2RTET SYMBOL AIWI For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. The RTE packages is only available taped and reeled. The suffix “R” indicates a reel of 3000, the suffix “T” indicates a reel of 250 4 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 DISSIPATION RATINGS TABLE PACKAGE RTE (QFN) (1) TA ≤ 25°C POWER RATING 2050 mW DERATING FACTOR 48.7 °C/W (1) TA = 70°C POWER RATING 1130 mW TA = 85°C POWER RATING 821 mW See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for using package thermal information. See JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD VIH VIL TA High-level input voltage; EN, G0, G1 Low-level input voltage; EN, G0, G1 Voltage applied to Output; OUTR, OUTL (when EN = 0 V) Operating free-air temperature –0.3 –40 2.3 1.3 0.6 3.6 85 MAX 5.5 UNIT V V V V °C ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER Output offset voltage Power supply rejection ratio High-level output current (EN, G0, G1) Low-level output current (EN, G0, G1) VDD = 2.3 V, No load, EN = VDD Supply Current VDD = 3.6 V, No load, EN = VDD VDD = 5.5 V, No load, EN = VDD EN = 0 V, VDD = 2.3 V to 5.5 V 2.1 2.1 2.2 0.7 VDD = 2.3 V to 5.5 V TEST CONDITIONS MIN –0.5 100 1 1 3.1 3.1 3.2 1.2 µA mA TYP MAX 0.5 UNIT mV dB µA µA Copyright © 2008, Texas Instruments Incorporated 5 Product Folder Link(s) :TPA6132A2 TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com OPERATING CHARACTERISTICS VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted) PARAMETER PO VO Output power (1) (Outputs in phase) Output voltage(1) (Outputs in phase) TEST CONDITIONS THD = 1%, f = 1 kHz THD = 1%, f = 1 kHz, RL = 32 Ω THD = 1%, VDD = 3.6 V, f = 1 kHz, RL = 100 Ω G0 = 0 V, G1 = 0 V, (–6 dB) AV Closed-loop voltage gain (OUT / IN–) G0 ≥ 1.3 V, G1 = 0 V, (0 dB) G0 = 0 V, G1 ≥ 1.3 V, (3 dB) G0 ≥ 1.3 V, G1 ≥ 1.3 V, (6 dB) ΔAv Gain matching Between Left and Right channels G0 = 0 V, G1 = 0 V, (–6 dB) Input impedance (per input pin) RIN Input impedance in shutdown (per input pin) VCM Input common-mode voltage range Output impedance in shutdown Input-to-output attenuation in shutdown kSVR THD+N SNR En fosc tON AC-power supply rejection ratio Total harmonic distortion plus noise (2) Signal-to-noise ratio Noise output voltage Charge pump switching frequency Start-up time from shutdown Crosstallk Thermal shutdown (1) (2) Per output channel A-weighted PO = 20 mW, f = 1 kHz Threshold Hysteresis EN = 0 V EN = 0 V 200 mVpp ripple, f = 217 Hz 200 mVpp ripple, f = 10 kHz PO = 20 mW, f = 1 kHz PO = 25 mW into 32 Ω, VDD = 5.5 V, f = 1 kHz PO = 20 mW; G0 ≥ 1.3 V, G1 = 0 V, (AV = 0 dB) A-weighted 1200 G0 ≥ 1.3 V, G1 = 0 V, (0 dB) G0 = 0 V, G1 ≥ 1.3 V, (3 dB) G0 ≥ 1.3 V, G1 ≥ 1.3 V, (6 dB) EN = 0 V –0.5 50 80 -100 -90 0.02% 0.01% 100 5.5 1275 5 –80 150 20 1350 dB µVRMS kHz ms dB °C °C –0.45 –0.95 –1.36 –1.95 MIN TYP 25 22 1.1 –0.5 –1.0 –1.41 –2.0 1% 26.4 19.8 16.5 13.2 10 1.5 V Ω dB dB kΩ –0.55 –1.05 –1.46 –2.05 V/V MAX UNIT mW VRMS 6 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 TYPICAL CHARACTERISTICS TA = 25°C, VDD = 3.6 V, Gain = 0 dB, EN = 3.6 V, CHPVDD = CHPVSS = 2.2 µF, CINPUT = CFLYING = 1 µF, Outputs in Phase TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % RL = 16 W, f = 1kHz VDD = 2.5 V, In Phase VDD = 3.6 V, In Phase RL = 32 W, f = 1kHz VDD = 2.5 V, In Phase VDD = 3.6 V, In Phase 1 1 VDD = 2.5 V, Out of Phase VDD = 2.5 V, Out of Phase VDD = 3.6 V, Out of Phase 0.1 0.1 VDD = 3.6 V, Out of Phase 0.01 0.1 1 10 PO - Output Power per Channel - mW 50 0.01 0.1 1 10 PO - Output Power per Channel - mW 50 Figure 1. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 Figure 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 THD+N - Total Harmonic Distortion + Noise - % RL = 16 W, VDD = 2.5 V PO = 1 mW per Channel 0.1 THD+N - Total Harmonic Distortion + Noise - % RL = 16 W, VDD = 3.6 V PO = 1 mW per Channel 0.1 PO = 20 mW per Channel 0.01 PO = 4 mW per Channel PO = 10 mW per Channel 0.01 PO = 10 mW per Channel 0.001 20 100 1k f - Frequency - Hz 10k 20k 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 3. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 Figure 4. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % RL = 16 W, VDD = 5 V PO = 1 mW per Channel 0.1 PO = 20 mW per Channel RL = 32 W, VDD = 2.5 V PO = 1 mW per Channel 0.1 PO = 4 mW per Channel 0.01 PO = 10 mW per Channel 0.01 PO = 10 mW per Channel 0.001 20 100 1k f - Frequency - Hz 10k 20k 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 5. Figure 6. Copyright © 2008, Texas Instruments Incorporated 7 Product Folder Link(s) :TPA6132A2 TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % RL = 32 W, VDD = 3.6 V PO = 1 mW per Channel 0.1 PO = 10 mW per Channel RL = 32 W, VDD = 5 V PO = 1 mW per Channel 0.1 PO = 20 mW per Channel 0.01 0.01 PO = 20 mW per Channel PO = 10 mW per Channel 0.001 20 100 1k f - Frequency - Hz 10k 20k 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 7. OUTPUT POWER vs SUPPLY VOLTAGE 50 RL = 16 W 45 45 50 RL = 32 W Figure 8. OUTPUT POWER vs SUPPLY VOLTAGE PO - Output Power per Channel - mW 40 THD+N = 10% 35 30 THD+N = 1% 25 20 15 10 5 0 2.5 PO - Output Power per Channel - mW 40 35 THD+N = 10% 30 25 20 15 10 5 THD+N = 1% 3 3.5 4 4.5 VDD - Supply Voltage - V 5 5.5 0 2.5 3 3.5 4 4.5 VDD - Supply Voltage - V 5 5.5 Figure 9. OUTPUT POWER vs LOAD RESISTANCE 40 30 Figure 10. OUTPUT POWER vs LOAD RESISTANCE HPVSS and Flying Cap = 1 mF PO - Output Power per Channel - mW PO - Output Power per Channel - mW 25 HPVSS and Flying Cap = 2.2 mF 20 VDD = 3.6 V, 10% THD+N 10 VDD = 2.5 V, 10% THD+N VDD = 2.5 V, 1% THD+N VDD = 3.6 V, 1% THD+N 15 10 HPVSS and Flying Cap = 0.47 mF 5 THD+N = 1%, VDD = 3.6 V 100 RL - Load Resistance - W 200 f = 1 kHz 1 10 100 RL - Load Resistance - W 1000 0 10 Figure 11. Figure 12. 8 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs SUPPLY VOLTAGE 2 1.8 1.6 Ksvr - Supply Voltage Rejection Ratio - dB SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY -10 RL = 16 W -30 f = 1 kHz, THD+N = 1% VO - Output Voltage - Vrms 1.4 Load = 600 W 1.2 1 Load = 32 W 0.8 0.6 Load = 16 W 0.4 0.2 0 2.5 -50 -70 VDD = 2.5 V -90 VDD = 3.6 V VDD = 5 V 3 3.5 4 4.5 5 5.5 -110 20 100 VDD - Supply Voltage - V 1k f - Frequency - Hz 10k 20k Figure 13. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY Ksvr - Supply Voltage Rejection Ratio - dB -10 RL = 32 W -30 Figure 14. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 10 9 EN = 1.3 V, No Load Quiescent Supply Current - mA 10k 20k 8 7 6 5 4 3 2 1 -50 -70 VDD = 3.6 V -90 VDD = 2.5 V VDD = 5 V -110 20 100 1k f - Frequency - Hz 0 2.5 3 3.5 4 4.5 VDD - Supply Voltage - V 5 5.5 Figure 15. SUPPLY CURRENT vs TOTAL OUTPUT POWER 100 RL = 16 W, f = 1kHz VDD = 3 V Figure 16. SUPPLY CURRENT vs TOTAL OUTPUT POWER 100 RL = 32 W, f = 1kHz IDD - Supply Current - mA VDD = 5 V 10 VDD = 2.5 V IDD - Supply Current - mA VDD = 5 V 10 VDD = 3.6 V VDD = 3 V VDD = 3.6 V 1 0.001 VDD = 2.5 V 1 0.001 0.01 0.1 1 PO - Total Output Power - mW 10 50 0.01 0.1 1 PO - Total Output Power - mW 10 50 Figure 17. Figure 18. Copyright © 2008, Texas Instruments Incorporated 9 Product Folder Link(s) :TPA6132A2 TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) CROSSTALK vs FREQUENCY 0 -20 RL = 16 W, Power = 15 mW, VDD = 3.6 V OUTPUT SPECTRUM vs FREQUENCY -10 -30 Single Channel, Load = 16 W, VDD = 3.6 V -40 VO - Output Amplitude - dBV -50 -70 -90 -110 Crosstalk - dB -60 -80 -100 -120 -140 20 -130 -150 0 100 1k f - Frequency - Hz 10k 20k 5000 10000 f - Frequency - Hz 15000 20000 Figure 19. STARTUP WAVEFORMS vs TIME 5 4 3 V - Voltage - V 5 4 EN 3 2 1 VOUT 0 -1 Figure 20. SHUTDOWN WAVEFORMS vs TIME Load = 16 W, VDD = 3.6 V, VI = 0.5 VRMS at 20 kHz EN V - Voltage - V 2 1 VOUT 0 -1 -2 -3 0 2 4 6 t - Time - ms 8 10 Load = 16 W, VDD = 3.6 V, VI = 0.5 VRMS at 1 kHz -2 -3 0 50 100 t - Time - ms 150 200 Figure 21. Figure 22. 10 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 APPLICATION INFORMATION APPLICATION CIRCUIT 0.22 µF x 4 INR+ INRTPA2012D2 INL+ INLOUTL OUTR 0.22 µF x 4 ABB or TLV320AIC33 TLV320AIC3104 TLV320DAC32 PCM1774 OUTR+ OUTR– OUTL+ OUTL– ENABLE GAIN0 GAIN1 VBAT 2.2 µF INR+ INRINL+ INLEN G0 G1 PVDD HPVDD 2.2 µF 1 µF CPP OUTR OUTL TPA6132A2 SGND PGND HPVSS CPN 1 µF Figure 23. Typical Application Configuration with Differential Input Signals 1 µF RIGHT IN INRINR+ OUTR LEFT IN 1 µF INLINL+ SGND ENABLE GAIN0 GAIN1 VBAT 2.2 µF EN G0 G1 PVDD HPVDD CPP HPVSS CPN 1 µF PGND TPA6132A2 OUTL 2.2 µF 1 µF Figure 24. Typical Application Configuration with Single-Ended Input Signals Copyright © 2008, Texas Instruments Incorporated 11 Product Folder Link(s) :TPA6132A2 TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com GAIN CONTROL The TPA6132A2 has four gain settings which are controlled with pins G0 and G1. The following table gives an overview of the gain function. G0 VOLTAGE ≤ 0.5 V ≥ 1.3 V ≤ 0.5 V ≥ 1.3 V G1 VOLTAGE ≤ 0.5 V ≤ 0.5 V ≥ 1.3 V ≥ 1.3 V AMPLIFIER GAIN –6 dB 0 dB 3 dB 6 dB Table 1. Windows Vista™ Premium Mobile Mode Specifications Device Type Analog Speaker Line Jack (RL = 10 kΩ, FS = 0.707 Vrms) Requirement THD+N Dynamic Range with Signal Present Line Output Crosstalk THD+N Analog Headphone Out Jack (RL = 32Ω, FS = 0.300 Vrms) Dynamic Range with Signal Present Headphone Output Crosstalk Windows Premium Mobile Vista Specifications ≤ –65 dB FS [20 Hz, 20 kHz] ≤ –80 dB FS A-Weight ≤ –60 dB [20 Hz, 20 kHz] ≤ –45 dB FS [20 Hz, 20 kHz] ≤ –80 dB FS A-Weight ≤ –60 dB [20 Hz, 20 kHz] TPA6132A2 Typical Performance –75 dB FS[20 Hz, 20 kHz] –100 dB FS A-Weight –90 dB [20 Hz, 20 kHz] –65 dB FS [20 Hz, 20 kHz] –94 dB FS A-Weight –90 dB [20 Hz, 20 kHz] HEADPHONE AMPLIFIERS Single-supply headphone amplifiers typically require dc-blocking capacitors to remove dc bias from their output voltage. The top drawing in Figure 25 illustrates this connection. If dc bias is not removed, large dc current will flow through the headphones which wastes power, clip the output signal, and potentially damage the headphones. These dc-blocking capacitors are often large in value and size. Headphone speakers have a typical resistance between 16 Ω and 32 Ω. This combination creates a high-pass filter with a cutoff frequency as shown in Equation 1, where RL is the load impedance, CO is the dc-block capacitor, and fC is the cutoff frequency. 1 fc = 2pRLCO (1) For a given high-pass cutoff frequency and load impedance, the required dc-blocking capacitor is found as: CO = 1 2p ¦C RL (2) Reducing fC improves low frequency fidelity and requires a larger dc-blocking capacitor. To achieve a 20 Hz cutoff with 16 Ω headphones, CO must be at least 500 µF. Large capacitor values require large packages, consuming PCB area, increasing height, and increasing cost of assembly. During start-up or shutdown the dc-blocking capacitor has to be charged or discharged. This causes an audible pop on start-up and power-down. Large dc-blocking capacitors also reduce audio output signal fidelity. Two different headphone amplifier architectures are available to eliminate the need for dc-blocking capacitors. The Capless amplifier architecture is similar provides a reference voltage to the headphone connector shield pin as shown in the middle drawing of Figure 25. The audio output signals are centered around this reference voltage, which is typically half of the supply voltage to allow symmetrical output voltage swing. When using a Capless amplifier do not connect the headphone jack shield to any ground reference or large currents will result. This makes Capless amplifiers ineffective for plugging non-headphone accessories into the headphone connector. Capless amplifiers are useful only with floating GND headphones. 12 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 Conventional CO VOUT CO GND Capless VOUT GND VBIAS DirectPath™ VDD GND VSS Figure 25. Amplifier Applications The DirectPath™ amplifier architecture operates from a single supply voltage and uses an internal charge pump to generate a negative supply rail for the headphone amplifier. The output voltages are centered around 0 V and are capable of positive and negative voltage swings as shown in the bottom drawing of Figure 25. DirectPath amplifiers require no output dc-blocking capacitors. The headphone connector shield pin connects to ground and will interface will headphones and non-headphone accessories. The TPA6132A2 is a DirectPath amplifier. ELIMINATING TURN-ON POP AND POWER SUPPLY SEQUENCING The TPA6132A2 has excellent noise and turn-on / turn-off pop performance. It uses an integrated click-and-pop suppression circuit to allow fast start-up and shutdown without generating any voltage transients at the output pins. Typical start-up time from shutdown is 5 ms. DirectPath technology keeps the output dc voltage at 0 V even when the amplifier is powered up. The DirectPath technology together with the active pop-and-click suppression circuit eliminates audible transients during start up and shutdown. Use input coupling capacitors to ensure inaudible turn-on pop. Activate the TPA6132A2 after all audio sources have been activated and their output voltages have settled. On power-down, deactivate the TPA6132A2 before deactivating the audio input source. The EN pin controls device shutdown: Set to 0.6 V or lower to deactivate the TPA6132A2; set to 1.3 V or higher to activate. Copyright © 2008, Texas Instruments Incorporated 13 Product Folder Link(s) :TPA6132A2 TPA6132A2 SLOS597 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com RF AND POWER SUPPLY NOISE IMMUNITY The TPA6132A2 employs a new differential amplifier architecture to achieve high power supply noise rejection and RF noise rejection. RF and power supply noise are common in modern electronics. Although RF frequencies are much higher than the 20 kHz audio band, signal modulation often falls in-band. This, in turn, modulates the supply voltage, allowing a coupling path into the audio amplifier. A common example is the 217 Hz GSM frame-rate buzz often heard from an active speaker when a cell phone is placed nearby during a phone call. The TPA6132A2 has excellent rejection of power supply and RF noise, preventing audio signal degradation. CONSTANT MAXIMUM OUTPUT POWER AND ACOUSTIC SHOCK PREVENTION Typically the output power increases with increasing supply voltage on an unregulated headphone amplifier. The TPA6132A2 maintains a constant output power independent of the supply voltage. Thus the design for prevention of acoustic shock (hearing damage due to exposure to a loud sound) is simplified since the output power will remain constant, independent of the supply voltage. This feature allows maximizing the audio signal at the lowest supply voltage. INPUT COUPLING CAPACITORS Input coupling capacitors block any dc bias from the audio source and ensure maximum dynamic range. Input coupling capacitors also minimize TPA6132A2 turn-on pop to an inaudible level. The input capacitors are in series with TPA6132A2 internal input resistors, creating a high-pass filter. Equation 3 calculates the high-pass filter corner frequency. The input impedance, RIN, is dependent on device gain. Larger input capacitors decrease the corner frequency. See the Operating Characteristics table for input impedance values. 1 fC = 2 p RIN CIN (3) For a given high-pass cutoff frequency, the minimum input coupling capacitor is found as: 1 CIN = 2 p ¦ C RIN (4) Example: Design for a 20 Hz corner frequency with a TPA6132A2 gain of +6 dB. The Operating Characteristics table gives RIN as 13.2 kΩ. Equation 4 shows the input coupling capacitors must be at least 0.6 µF to achieve a 20 Hz high-pass corner frequency. Choose a 0.68 µF standard value capacitor for each TPA6132A2 input (X5R material or better is required for best performance). Input capacitors can be removed provided the TPA6132A2 inputs are driven differentially with less than ±1 V and the common-mode voltage is within the input common-mode range of the amplifier. Without input capacitors turn-on pop performance may be degraded and should be evaluated in the system. CHARGE PUMP FLYING CAPACITOR AND HPVSS CAPACITOR The TPA6132A2 uses a built-in charge pump to generate a negative voltage supply for the headphone amplifiers. The charge pump flying capacitor connects between CPP and CPN. It transfers charge to generate the negative supply voltage. The HPVSS capacitor must be at least equal in value to the flying capacitor to allow maximum charge transfer. Use low equivalent-series-resistance (ESR) ceramic capacitors (X5R material or better is required for best performance) to maximize charge pump efficiency. Typical values are 1 µF to 2.2 µF for the HPVSS and flying capacitors. Although values down to 0.47 µF can be used, total harmonic distortion (THD) will increase. 14 Product Folder Link(s) :TPA6132A2 Copyright © 2008, Texas Instruments Incorporated TPA6132A2 www.ti.com ........................................................................................................................................................................................... SLOS597 – DECEMBER 2008 POWER SUPPLY AND HPVDD DECOUPLING CAPACITORS The TPA6132A2 DirectPath headphone amplifier requires adequate power supply decoupling to ensure that output noise and total harmonic distortion (THD) remain low. Use good low equivalent-series-resistance (ESR) ceramic capacitors (X5R material or better is required for best performance). Place a 2.2 µF capacitor within 5 mm of the VDD pin. Reducing the distance between the decoupling capacitor and VDD minimizes parasitic inductance and resistance, improving TPA6132A2 supply rejection performance. Use 0402 or smaller size capacitors if possible. For additional supply rejection, connect an additional 10 µF or higher value capacitor between VDD and ground. This will help filter lower frequency power supply noise. The high power supply rejection ratio (PSRR) of the TPA6132A2 makes the 10 µF capacitor unnecessary in most applications. Connect a 2.2 µF capacitor between HPVDD and ground. This ensures the amplifier internal bias supply remains stable and maximizes headphone amplifier performance. WARNING: DO NOT connect HPVDD directly to VDD or an external supply voltage. The voltage at HPVDD is generated internally. Connecting HPVDD to an external voltage can damage the device. LAYOUT RECOMMENDATIONS EXPOSED PAD ON TPA6132A2RTE Solder the exposed metal pad on the TPA6132A2RTE QFN package to the landing pad on the PCB. Connect the landing pad to ground or leave it electrically unconnected (floating). Do not connect the landing pad to VDD or to any other power supply voltage. If the pad is grounded, it must be connected to the same ground as the PGND pin (10). See the layout and mechanical drawings at the end of the data sheet for proper sizing. Soldering the thermal pad is required for mechanical reliability and enhances thermal conductivity of the package. WARNING: DO NOT connect the TPA6132A2RTE exposed metal pad to VDD or any other power supply voltage. GND CONNECTIONS The SGND pin is an input reference and must be connected to the headphone ground connector pin. This ensures no turn-on pop and minimizes output offset voltage. Do not connect more than ±0.3 V to SGND. PGND is a power ground. Connect supply decoupling capacitors for VDD, HPVDD, and HPVSS to PGND. POWER SUPPLY CONNECTIONS Connect the supply voltage to the VDD pin and decouple it with an X5R or better capacitor. Connect the HPVDD pin only to a 2.2 µF, X5R or better, capacitor. Do not connect HPVDD to an external voltage supply. Place both capacitors within 5 mm of their associated pins on the TPA6132A2. Ensure that the ground connection of each of the capacitors has a minimum length return path to the device. Failure to properly decouple the TPA6132A2 may degrade audio or EMC performance. Copyright © 2008, Texas Instruments Incorporated 15 Product Folder Link(s) :TPA6132A2 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 PACKAGING INFORMATION Orderable Device TPA6132A2RTER TPA6132A2RTET (1) Status (1) ACTIVE ACTIVE Package Type QFN QFN Package Drawing RTE RTE Pins Package Eco Plan (2) Qty 16 16 3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing QFN QFN RTE RTE 16 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 180.0 12.4 12.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 8.0 W Pin1 (mm) Quadrant 12.0 12.0 Q2 Q2 TPA6132A2RTER TPA6132A2RTET 3000 250 3.3 3.3 3.3 3.3 1.1 1.1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2008 *All dimensions are nominal Device TPA6132A2RTER TPA6132A2RTET Package Type QFN QFN Package Drawing RTE RTE Pins 16 16 SPQ 3000 250 Length (mm) 346.0 190.5 Width (mm) 346.0 212.7 Height (mm) 29.0 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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