TSL1401CS-LF

r r TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 D D D D D D D D D D D D 128 × 1 Sensor-Element Organization 400 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required Available in a Solder-Bump Linear Array Package Lead (Pb) Free and RoHS Compliant (TOP VIEW) 1 SI HOLD 2 3 CLK GND 4 5 GND AO 6 7 SO VDD 8 Description The TSL1401CS−LF linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 μm (H) by 55.5 μm (W) with 63.5-μm center-to-center spacing and 8-μm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. Functional Block Diagram Pixel 1 S1 1 Integrator Reset 2 2 Pixel 2 Pixel 3 Pixel 128 8 Analog Bus Output Buffer 6 VDD _ 1 3 AO + S2 Sample/Hold/ Output 4, 5 GND Switch Control Logic Hold 2 Gain Trim 7 SO Q1 Q2 Q3 Q128 CLK SI 3 1 128-Bit Shift Register The LUMENOLOGY r Company Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759 r www.taosinc.com 1 r Copyright E 2007, TAOS Inc. TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 Terminal Functions TERMINAL NAME AO CLK GND HOLD SI SO VDD NO. 6 3 4, 5 2 1 7 8 Analog output Clock. The clock controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to the substrate. Hold signal. HOLD freezes the result of a 128 pixel scan. Serial input. SI defines the start of the data-out sequence. Serial output. SO provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. Supply voltage. Supply voltage for both analog and digital circuits. DESCRIPTION Detailed Description The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. The signal called Hold is normally connected to SI. Then, the rising edge of SI causes a HOLD condition. This causes all 128 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to a known state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of tqt (pixel charge transfer time) after the 129th clock pulse. AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout Vdrk Re Ee tint is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(μJ/cm2) is the incident irradiance in μW/cm2 is integration time in seconds A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device. The TSL1401CS−LF is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 2 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 Available Options DEVICE TSL1401CS−LF TA − 40°C to 100°C PACKAGE − LEADS Solder Bump − Lead Free − 8 PACKAGE DESIGNATOR ORDERING NUMBER TSL1401CS−LF Absolute Maximum Ratings† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . − 0.3 V to VDD + 0.3 V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25 mA to 25 mA Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 100°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 100°C Solder reflow temperature, case exposed for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, λ Clock frequency, fclock Sensor integration time, tint (see Note 1) Setup time, serial input, tsu(SI) Hold time, serial input, th(SI) (see Note 2) Operating free-air temperature, TA 3 0 2 0 400 5 0.03375 20 0 −40 85 NOM 5 MAX 5.5 VDD VDD 0.8 1000 8000 100 UNIT V V V V nm kHz ms ns ns °C NOTES: 1. Integration time is calculated as follows: tint (min) = (128 − 18) y clock period + 20 ms where 128 is the number of pixels in series, 18 is the required logic setup clocks, and 20 ms is the pixel charge transfer time (tqt) 2. SI must go low before the rising edge of the next clock pulse. The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 3 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, RL = 330 Ω, Ee = 11 μW/cm2 (unless otherwise noted) (see Note 3 and Note 4) PARAMETER Vout Vdrk PRNU Analog output voltage (white, average over 128 pixels) Analog output voltage (dark, average over 128 pixels) Pixel response nonuniformity Nonlinearity of analog output voltage Output noise voltage Re Vsat SE DSNU IL IDD IIH IIL Ci Responsivity Analog output saturation voltage Saturation exposure Dark signal nonuniformity Image lag Supply current High-level input current Low-level input current Input capacitance TEST CONDITIONS See Note 4 Ee = 0 See Note 5 See Note 6 See Note 7 See Note 8 VDD = 5 V, RL = 330 Ω VDD = 3 V, RL = 330 Ω VDD = 5 V, See Note 9 VDD = 3 V, See Note 9 All pixels, Ee = 0 See Note 11 VDD = 5 V, Ee = 0 VDD = 3 V, Ee = 0 VI = VDD VI = 0 5 See Note 10 25 4.5 2.5 MIN 1.6 0 TYP 2 0.1 ± 4% ± 0.4% 1 35 4.8 2.8 136 78 0.02 0.5% 2.8 2.6 4.5 4.5 1 1 mA μA μA pF 0.05 44 MAX 2.4 0.2 ± 10% FS mVrms V/ (μJ/cm 2) V nJ/cm 2 V UNIT V V NOTES: 3. All measurements made with a 0.1 μF capacitor connected between VDD and ground. 4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. Re(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint) 9. SE(min) = [Vsat(min) − Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) − Vdrk(min)] 10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: V out (IL) * V drk IL + 100 V out (white) * V drk Timing Requirements (see Figure 1 and Figure 2) MIN tsu(SI) th(SI) tw tr, tf tqt Setup time, serial input (see Note 12) Hold time, serial input (see Note 11 and Note 13) Pulse duration, clock high or low Input transition (rise and fall) time Pixel charge transfer time 20 0 50 0 20 500 NOM MAX UNIT ns ns ns ns μs NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 13. SI must go low before the rising edge of the next clock pulse. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 4 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 7 and 8) PARAMETER ts tpd(SO) Analog output settling time to ± 1% Propagation delay time, SO1, SO2 TEST CONDITIONS RL = 330 Ω, CL = 10 pF MIN TYP 120 50 MAX UNIT ns ns TYPICAL CHARACTERISTICS CLK SI tqt Internal Reset 18 Clock Cycles Integration Not Integrating 129 Clock Cycles AO tint Integrating Hi-Z tw CLK tsu(SI) SI SO ts AO Pixel 1 Pixel 128 The LUMENOLOGY r Company ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hi-Z Figure 1. Timing Waveforms 1 2 128 129 2.5 V 5V 0V 5V 0V 50% th(SI) tpd(SO) tpd(SO) Figure 2. Operational Waveforms Copyright E 2007, TAOS Inc. r r www.taosinc.com 5 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 TYPICAL CHARACTERISTICS IDLE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 4.0 VDD = 5 V 3.5 IDD — Idle Supply Current — mA 3.0 2.5 2.0 1.5 1.0 0.5 0 −40 PHOTODIODE SPECTRAL RESPONSIVITY 1 TA = 25°C 0.8 Relative Responsivity 0.6 0.4 0.2 0 300 400 500 600 700 800 900 λ − Wavelength − nm 1000 1100 −15 10 35 60 85 TA − Free-Air Temperature − °C Figure 3 AVERAGE ANALOG OUTPUT VOLTAGE, WHITE vs FREE-AIR TEMPERATURE 3.50 Average Analog Output Voltage, White — V 3.00 2.50 2.00 tint = 5 ms 1.50 1.00 0.50 tint = 0.5 ms tint = 2.5 ms tint = 1 ms tint = 10 ms Average Analog Output Voltage, Dark — V 0.12 Figure 4 AVERAGE ANALOG OUTPUT VOLTAGE, DARK vs FREE-AIR TEMPERATURE 0.10 tint = 5 ms 0.08 0.06 0.04 0.02 0 −40 −15 10 35 60 TA − Free-Air Temperature − °C 85 0 −40 −15 Figure 5 10 35 60 TA − Free-Air Temperature − °C 85 Figure 6 Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 6 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 TYPICAL CHARACTERISTICS SETTLING TIME vs. LOAD 600 VDD = 3 V Vout = 1 V Settling Time to 1% — ns 470 pF 400 220 pF 300 600 VDD = 5 V Vout = 1 V 470 pF 400 220 pF 300 SETTLING TIME vs. LOAD 500 Settling Time to 1% — ns 500 200 100 pF 100 10 pF 200 100 pF 100 10 pF 0 0 200 400 600 800 RL — Load Resistance − W 1000 0 0 200 400 600 800 RL — Load Resistance − W 1000 Figure 7 Figure 8 The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 7 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 APPLICATION INFORMATION Power Supply Considerations A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device. Connection Diagrams The HOLD pin on the device is normally connected to the SI pin in single-die operation. In multi-die operation of n die, the HOLD pin is used to provide a continuous scan across the n die. See Figure 9 for an example of this wiring configuration. Note that there is a single AO signal when used in this mode. Alternately, the individual die may be scanned all at once by connecting the individual SI and HOLD lines and reading the AO signals in parallel. See Figure 10 for an example of this wiring configuration. VDD C1 0.1 mF 8 1 2 3 SI HOLD CLK 5 SO 4 7 VDD AO 6 1 2 3 SI HOLD CLK 5 8 VDD C2 0.1 mF C3 0.1 mF AO 8 VDD AO 6 1 2 SI HOLD CLK 5 AO 6 TSL1401CS−LF TSL1401CS−LF TSL1401CS−LF GND GND 4 SO 7 3 GND 4 SO 7 GND CLK SI Figure 9. Multi-Die Continuous Scan VDD C1 0.1 mF C2 0.1 mF C3 0.1 mF AO1 AO2 8 1 2 3 SI HOLD CLK 5 GND CLK SI SO 4 7 VDD TSL1401CS−LF AO 6 1 2 3 SI HOLD CLK 5 8 VDD AO 6 1 2 7 3 SI HOLD CLK 5 8 VDD AO 6 AO3 TSL1401CS−LF TSL1401CS−LF GND GND 4 SO GND 4 SO 7 Figure 10. Multi-Die Individual Scan Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 8 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 APPLICATION INFORMATION Integration Time The integration time of the linear array is the period during which light is sampled and charge accumulates on each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature of the TAOS TSL14xx linear array family. By changing the integration time, a desired output voltage can be obtained on the output pin while avoiding saturation for a wide range of light levels. The integration time is the time between the SI (Start Integration) positive pulse and the HOLD positive pulse minus the 18 setup clocks. The TSL14xx linear array is normally configured with the SI and HOLD pins tied together. This configuration will be assumed unless otherwise noted. Sending a high pulse to SI (observing timing rules for setup and hold to clock edge) starts a new cycle of pixel output and integration setup. However, a minimum of (n+1) clocks, where n is the number of pixels, must occur before the next high pulse is applied to SI. It is not necessary to send SI immediately on/after the (n+1) clocks. A wait time adding up to a maximum total of 100 ms between SI pulses can be added to increase the integration time creating a higher output voltage in low light applications. Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the Functional Block Diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing switch S1 (position 2). At SI input, all of the pixel voltages are simultaneously scanned and held by moving S2 to position 2 for all pixels. During this event, S2 for pixel 1 is in position 3. This makes the voltage of pixel 1 available on the analog output. On the next clock, S2 for pixel 1 is put into position 2 and S2 for pixel 2 is put into position 3 so that the voltage of pixel 2 is available on the output. Following the SI pulse and the next 17 clocks after the SI pulse is applied, the S1 switch for all pixels remains in position 2 to reset (zero out) the integrating capacitor so that it is ready to begin the next integration cycle. On the rising edge of the 19th clock, the S1 switch for all the pixels is put into position 1 and all of the pixels begin a new integration cycle. The first 18 pixel voltages are output during the time the integrating capacitor is being reset. On the 19th clock following an SI pulse, pixels 1 through 18 have switch S2 in position 1 so that the sampling capacitor can begin storing charge. For the period from the 19th clock through the nth clock, S2 is put into position 3 to read the output voltage during the nth clock. On the next clock the previous pixel S2 switch is put into position 1 to start sampling the integrating capacitor voltage. For example, S2 for pixel 19 moves to position 1 on the 20th clock. On the n+1 clock, the S2 switch for the last (nth) pixel is put into position 1 and the output goes to a high-impedance state. If a SI was initiated on the n+1 clock, there would be no time for the sampling capacitor of pixel n to charge to the voltage level of the integrating capacitor. The minimum time needed to guarantee the sampling capacitor for pixel n will charge to the voltage level of the integrating capacitor is the charge transfer time of 20 μs. Therefore, after n+1 clocks, an extra 20 μs wait must occur before the next SI pulse to start a new integration and output cycle. The minimum integration time for any given array is determined by time required to clock out all the pixels in the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels in the array. A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency of 8 MHz. The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 9 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 APPLICATION INFORMATION The minimum integration time can be calculated from the equation: T int(min) + where: n is the number of pixels 1 maximum clock frequency (n * 18) pixels ) 20ms In the case of the TSL1401CS−LF with the maximum clock frequency of 8 MHz, the minimum integration time would be: T int(min) + 0.125 ms (128 * 18) ) 20 ms + 33.75 ms It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when inactive because the SI pulse required to start a new cycle is a low-to-high transition. The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits for integration time. If the amount of light incident on the array during a given integration period produces a saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing the period of time the light sampling window is active is to lower the output voltage level to prevent saturation. However, the integration time must still be greater than or equal to the minimum integration period. If the light intensity produces an output below desired signal levels, the output voltage level can be increased by increasing the integration period provided that the maximum integration time is not exceeded. The maximum integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated charge. The maximum integration time should not exceed 100 ms for accurate measurements. It should be noted that the data from the light sampled during one integration period is made available on the analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock period. In other words, at any given time, two groups of data are being handled by the linear array: the previous measured light data is clocked out as the next light sample is being integrated. Although the linear array is capable of running over a wide range of operating frequencies up to a maximum of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required for the analog-to-digital conversion must be less than the clock period. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 10 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 APPLICATION INFORMATION PCB Pad Layout Suggested PCB pad layout guidelines for the TSL1401CS−LF solder bump linear array package is shown in Figure 11. 8 y 380 Diameter Mask 8 y 360 Diameter Metal Pad 1 2 3 4 5 6 7 8 170 8 y 110 Trace Width 7 y 1000 NOTES: A. All linear dimensions are in micrometers. B. This drawing is subject to change without notice. Figure 11. Suggested PCB Layout The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 11 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 MECHANICAL INFORMATION The TSL1401CS-LF is available in a solder bump linear array package, ready for surface mount manufacturing processes. SOLDER BUMP LINEAR ARRAY 8870 + 25 8120 TOP VIEW 1000 + 25 A SIDE VIEW 645 + 55 8 y 145 + 30 935 + 30 300 + 30 BOTTOM VIEW 4 y 170 4 y 415 + 30 Pin Pin Pin Pin Pin Pin Pin Pin 1 2 3 4 5 6 7 8 SI HOLD CLK GND GND AO SO VDD 430.4 + 25 NOTES: A. All linear dimensions are in micrometers. Dimension tolerance is ± 10 μm unless otherwise noted. B. Solder bumps are formed of Sn (96.5%), Ag (3%), and Cu (0.5%). C. The top of the photodiode active area is 415 μm below the glass that forms the top surface of the package. The index of refraction of the glass is 1.52. D. This drawing is subject to change without notice. Figure 12. TSL1401CS−LF Solder Bump Linear Array Package Copyright E 2007, TAOS Inc. 12 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Pixel 1 Pixel 128 Alignment Marker (Pin 8) B 7 y 1000 DETAIL B DETAIL A 128 y 63.5 Glass Cover Thickness 400 + 50 375 + 25 128 y 55.5 127 y 63.5 505 Typ Pb Lead Free r r The LUMENOLOGY r Company www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 MECHANICAL INFORMATION 0.300 + 0.200 1.24 + 0.100 SIDE VIEW 1.75 + 0.100 Pin 1 j 1.5 + 0.100 Typ 2 + 0.100 4 + 0.100 Typ 4 + 0.100 TOP VIEW A 7.50 + 0.100 C L 16 + 0.300 − 0.100 A R 0.58 B B DETAIL A DETAIL B Ko 0.82 85 Max Bo 7.60 9.17 1.29 Ao 1.17 55 Max NOTES: A. B. C. D. E. F. G. All linear dimensions are in millimeters. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. Each reel is 178 millimeters in diameter and contains 2800 parts. TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. This drawing is subject to change without notice. Figure 13. TSL1401CS−LF Solder Bump Linear Array Package Carrier Tape The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 13 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 MANUFACTURING INFORMATION This product, in the solder bump linear array package, has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The process, equipment, and materials used in these tests are detailed below. Tooling Required D Solder stencil (round aperture size 0.36 mm, stencil thickness of 152.4 μm) D 20 × 20 frame for solder stencil Process 1. Apply solder paste using stencil 2. Dispense adhesive dots 3. Place component 4. Reflow solder/cure 5. X-Ray verify Placement of the TSL1401CS−LF device onto the gold immersion substrate is accomplished using a standard surface mount manufacturing process. First, using the stencil with 0.36 mm square aperture, print solder paste onto the substrate. Next, dispense two 0.25 mm to 0.4 mm diameter dots of adhesive in opposing corners of the TSL1401CS−LF mounting area. Machine place the TSL1401CS−LF from the JEDEC waffle carrier onto the substrate. A suggested pick-up tool is the Siemens Vacuum Pickup tool nozzle number 912. This nozzle has a rubber tip with a diameter of approximately 0.75 mm. The part is picked up from the center of the body. Reflow the solder and cure the adhesive using the solder profile shown in Figure 14. The reflow profiles specified here describe expected maximum heat exposure of components during the solder reflow process of product on a PWB. Temperature is measured at the top of component. The components should be limited to one pass through the solder reflow profile used. Table 1. TSL1401CS−LF Solder Reflow Profile PARAMETER Average temperature gradient in preheating Soak time Time above T1, 217°C Time above T2, 230°C Time above T3, (Tpeak −10°C) Peak temperature in reflow Temperature gradient in cooling tsoak t1 t2 t3 Tpeak REFERENCE TSL1401CS−LF 2.5°C/sec 2 to 3 minutes Max 60 sec Max 50 sec Max 10 sec 260°C (−0°C/+5°C) Max −5°C/sec Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 14 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 MANUFACTURING INFORMATION Not to scale — for reference only Tpeak T3 T2 T1 Temperature (5C) Time (sec) tsoak t3 t2 t1 Figure 14. TSL1401CS−LF Solder Bump Linear Array Package Solder Profile It is important to use a substrate that has an immersion plating surface. This may be immersion gold, silver, or white tin. Hot air solder leveled substrates (HASL) are not coplanar and should not be used. Qualified Equipment D EKRA E5 — Stencil Printer D ASYMTEC Century — Dispensing system D SIEMENS F5 — Placement system D VITRONICS 820 — Oven D PHOENIX — Inspector X-Ray system Qualified Materials − SIEMENS 912 — Vacuum Pickup Tool Nozzle D OMG — Microbond solder paste D Loctite 3621 — Adhesive The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 15 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 MANUFACTURING INFORMATION Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package molding compound. To ensure the package molding compound contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. This package has been assigned a moisture sensitivity level of MSL 2 and the devices should be stored under the following conditions: Temperature Range Relative Humidity Floor Life 5°C to 50°C 60% maximum 1 year out of bag at ambient < 30°C / 60% RH Rebaking will be required if the aluminized envelope has been open for more than 1 year. If rebaking is required, it should be done at 90°C for 3 hours. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 16 www.taosinc.com TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. LEAD-FREE (Pb-FREE) and GREEN STATEMENT Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TAOS has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced Optoelectronic Solutions Incorporated. The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 17 TSL1401CS−LF 128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS072E − APRIL 2007 Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 18 www.taosinc.com