TSL1406R

r r TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 D D D D D D D D D D D 768 × 1 Sensor-Element Organization 400 Dot-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required Replacement for TSL1406 TSL1406R (TOP VIEW) Description The TSL1406R is a 400 dots-per-inch (DPI) linear sensor array consisting of two 384-pixel sections, each with its own output. The sections are aligned to form a contiguous 768 × 1 pixel array. The device incorporates a pixel data-hold function that provides simultaneous integration-start and integration-stop times for all pixels. 1 2 3 4 5 6 7 8 9 10 11 12 13 VPP SI1 HOLD1 CLK1 GND AO1 SO1 SI2 HOLD2 CLK2 SO2 AO2 VDD Pixels measure 63.5 μm by 55.5 μm, with 63.5-μm center-to-center spacing and 8-μm spacing between pixels. Operation is simplified by internal logic that requires only a serial-input (SI) pulse and a clock. The device operates from a single 5-V power source. The two sections of 384 pixels each can be read out separately or can be cascaded to provide a single output for all 768 pixels (see Figure 9). The TSL1406RS is the same device mounted in a shorter package. These devices are intended for use in a wide variety of applications including mark and code reading, OCR and contact imaging, edge detection and positioning, and optical encoding. Functional Block Diagram (each section) Pixel 1 (385) 1 Integrator Reset 2 2 Pixel 2 (386) Pixel 3 (387) Pixel 384 (768) Analog Bus 13 VDD S1 _ + 1 3 S2 Sample/Hold/ Output Output Buffer 6, 12 AO 5 GND Switch Control Logic Hold 3, 9 Hold Q1 Q2 Q3 Q384 (Q768) Gain Trim 7, 11 SO CLK SI 4, 10 2, 8 384-Bit Shift Register (2 each) The LUMENOLOGY r Company Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759 r www.taosinc.com 1 r Copyright E 2007, TAOS Inc. TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 Terminal Functions TERMINAL NAME AO1 AO2 CLK1 CLK2 GND HOLD1 HOLD2 SI1 SI2 SO1 SO2 VDD VPP NO. 6 12 4 10 5 3 9 2 8 7 11 13 1 I I I I O O I/O O O I I Analog output, section 1. Analog output, section 2. Clock, section 1. CLK1 controls charge transfer, pixel output, and reset. Clock, section 2. CLK2 controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to GND. Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in serial mode, SI1 in parallel mode. Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode. Serial input (section 1). SI1 defines the start of the data-out sequence. Serial input (section 2). SI2 defines the start of the data-out sequence. Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode. Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. Supply voltage for both analog and digital circuitry. Normally grounded. DESCRIPTION Detailed Description The sensor consists of 768 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The output and reset of the integrators are controlled by a 384-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1 are connected together. This causes all 384 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins. On the 384th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (when SO1 is connected to SI2). The rising edge of the 385th clock cycle terminates the SO1 pulse, and returns the analog output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 768th clock pulse. Note that a 769th clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of tqt (pixel charge transfer time) after the 769th clock pulse. Sections 1 and 2 may be operated in parallel or in serial fashion. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 2 www.taosinc.com TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout Vdrk Re Ee tint is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(μJ/cm2) is the incident irradiance in μW/cm2 is integration time in seconds A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device. The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 3 TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 Absolute Maximum Ratings† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . − 0.3 V to VDD + 0.3 V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25 mA to 25 mA Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 25°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, λ Clock frequency, fclock Sensor integration time, Serial, tint (see Note 1) Sensor integration time, Parallel, tint (see Note 1) Setup time, serial input, tsu(SI) Hold time, serial input, th(SI) (see Note 2) Operating free-air temperature, TA 3 0 2 0 400 5 0.11375 0.06575 20 0 0 70 NOM 5 MAX 5.5 VDD VDD 0.8 1000 8000 100 100 UNIT V V V V nm kHz ms ms ns ns °C NOTES: 1. Integration time is calculated as follows: tint (min) = (768 − 18) y clock period + 20 ms where 768 is the number of pixels in series, 18 is the required logic setup clocks, and 20 ms is the pixel charge transfer time (tqt) 2. SI must go low before the rising edge of the next clock pulse. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 4 www.taosinc.com TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, RL = 330 Ω, Ee = 12.5 μW/cm2 (unless otherwise noted) (see Note 3) PARAMETER Vout Vdrk PRNU Analog output voltage (white, average over 768 pixels) Analog output voltage (dark, average over 256 pixels) Pixel response nonuniformity Nonlinearity of analog output voltage Output noise voltage Re Vsat SE DSNU IL IDD IIH IIL Ci Ci Responsivity Analog output saturation voltage Saturation exposure Dark signal nonuniformity Image lag Supply current High-level input current Low-level input current Input capacitance, SI Input capacitance, CLK Ee = 0 See Note 5 See Note 6 See Note 7 See Note 8 VDD = 5 V, RL = 330 Ω VDD = 3 V, RL = 330 Ω VDD = 5 V, See Note 9 VDD = 3 V, See Note 9 All pixels, Ee = 0, See Note 10 See Note 11 VDD = 5 V, Ee = 0, RL = 330 Ω VDD = 3 V, Ee = 0, RL = 330 Ω VI = VDD VI = 0 15 30 20 4.5 2.5 0.4% 1 30 4.8 2.8 155 90 0.05 0.5% 18 16 27 25 10 10 mA μA μA pF pF 0.15 38 TEST CONDITIONS See Note 4 MIN 1.6 0 TYP 2 0.1 MAX 2.4 0.3 ±15% FS mVrms V/ (μJ/cm 2) V nJ/cm 2 V UNIT V V NOTES: 3. All measurements made with a 0.1 μF capacitor connected between VDD and ground. 4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated. 6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. Re(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint) 9. SE(min) = [Vsat(min) − Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) − Vdrk(min)] 10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN tsu(SI) th(SI) tpd(SO) tw tr, tf tqt Setup time, serial input (see Note 12) Hold time, serial input (see Note 12 and Note 13) Propagation delay time, SO Pulse duration, clock high or low Input transition (rise and fall) time Pixel charge transfer time 50 0 20 500 20 0 50 NOM MAX UNIT ns ns ns ns ns μs NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 13. SI must go low before the rising edge of the next clock pulse. The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 5 TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 7 and 8) PARAMETER ts tpd(SO) Analog output settling time to ± 1% Propagation delay time, SO1, SO2 TEST CONDITIONS RL = 330 Ω, CL = 50 pF MIN TYP 120 50 MAX UNIT ns ns TYPICAL CHARACTERISTICS CLK SI1 Internal Reset 18 Clock Cycles Integration Not Integrating 769 Clock Cycles AO tqt tint Integrating Hi-Z tw CLK tsu(SI) SI SO AO Copyright E 2007, TAOS Inc. 6 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hi-Z Figure 1. Timing Waveforms (serial connection) 1 2 384 385 2.5 V 5V 0V 5V 0V 50% th(SI) tpd(SO) tpd(SO) ts Pixel 1 Pixel 384 Figure 2. Operational Waveforms (each section) r r The LUMENOLOGY r Company www.taosinc.com TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 TYPICAL CHARACTERISTICS NORMALIZED IDLE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 2 IDD — Normalized Idle Supply Current 400 500 600 700 800 900 1000 1100 PHOTODIODE SPECTRAL RESPONSIVITY 1 TA = 25°C 0.8 Relative Responsivity 1.5 0.6 1 0.4 0.2 0.5 0 300 0 0 10 20 30 40 50 60 70 λ − Wavelength − nm TA − Free-Air Temperature − °C Figure 3 WHITE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2 VDD = 5 V tint = 0.5 ms to 15 ms Vout — Output Voltage — V 1.5 Vout — Output Voltage 0.09 0.10 VDD = 5 V Figure 4 DARK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE tint = 0.5 ms tint = 1 ms 1 0.08 tint = 15 ms tint = 5 ms tint = 2.5 ms 0.5 0.07 0 0 10 20 30 40 60 50 TA − Free-Air Temperature − °C 70 0.06 0 10 20 30 40 60 50 TA − Free-Air Temperature − °C 70 Figure 5 Figure 6 The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 7 TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 TYPICAL CHARACTERISTICS SETTLING TIME vs. LOAD 600 VDD = 3 V Vout = 1 V Settling Time to 1% — ns 470 pF 400 220 pF 300 600 VDD = 5 V Vout = 1 V 470 pF 400 220 pF 300 SETTLING TIME vs. LOAD 500 Settling Time to 1% — ns 500 200 100 pF 100 10 pF 200 100 pF 100 10 pF 0 0 200 400 600 800 RL — Load Resistance − W 1000 0 0 200 400 600 800 RL — Load Resistance − W 1000 Figure 7 Figure 8 APPLICATION INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 VDD SO1 SI2 SI1/HOLD1/HOLD2 CLK1 and CLK2 1 2 3 4 5 6 7 8 9 10 11 12 13 VDD SI1/HOLD 1 CLK1 and CLK2 AO1 SO1 SI2/HOLD2 SO2 AO1/AO2 SO2 AO2 SERIAL PARALLEL Figure 9. Operational Connections Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 8 www.taosinc.com TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 APPLICATION INFORMATION Integration Time The integration time of the linear array is the period during which light is sampled and charge accumulates on each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature of the TAOS TSL14xx linear array family. By changing the integration time, a desired output voltage can be obtained on the output pin while avoiding saturation for a wide range of light levels. The integration time is the time between the SI (Start Integration) positive pulse and the HOLD positive pulse minus the 18 setup clocks. The TSL14xx linear array is normally configured with the SI and HOLD pins tied together. This configuration will be assumed unless otherwise noted. Sending a high pulse to SI (observing timing rules for setup and hold to clock edge) starts a new cycle of pixel output and integration setup. However, a minimum of (n+1) clocks, where n is the number of pixels, must occur before the next high pulse is applied to SI. It is not necessary to send SI immediately on/after the (n+1) clocks. A wait time adding up to a maximum total of 100 ms between SI pulses can be added to increase the integration time creating a higher output voltage in low light applications. Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the Functional Block Diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing switch S1 (position 2). At SI input, all of the pixel voltages are simultaneously scanned and held by moving S2 to position 2 for all pixels. During this event, S2 for pixel 1 is in position 3. This makes the voltage of pixel 1 available on the analog output. On the next clock, S2 for pixel 1 is put into position 2 and S2 for pixel 2 is put into position 3 so that the voltage of pixel 2 is available on the output. Following the SI pulse and the next 17 clocks after the SI pulse is applied, the S1 switch for all pixels remains in position 2 to reset (zero out) the integrating capacitor so that it is ready to begin the next integration cycle. On the rising edge of the 19th clock, the S1 switch for all the pixels is put into position 1 and all of the pixels begin a new integration cycle. The first 18 pixel voltages are output during the time the integrating capacitor is being reset. On the 19th clock following an SI pulse, pixels 1 through 18 have switch S2 in position 1 so that the sampling capacitor can begin storing charge. For the period from the 19th clock through the nth clock, S2 is put into position 3 to read the output voltage during the nth clock. On the next clock the previous pixel S2 switch is put into position 1 to start sampling the integrating capacitor voltage. For example, S2 for pixel 19 moves to position 1 on the 20th clock. On the n+1 clock, the S2 switch for the last (nth) pixel is put into position 1 and the output goes to a high-impedance state. If a SI was initiated on the n+1 clock, there would be no time for the sampling capacitor of pixel n to charge to the voltage level of the integrating capacitor. The minimum time needed to guarantee the sampling capacitor for pixel n will charge to the voltage level of the integrating capacitor is the charge transfer time of 20 μs. Therefore, after n+1 clocks, an extra 20 μs wait must occur before the next SI pulse to start a new integration and output cycle. The minimum integration time for any given array is determined by time required to clock out all the pixels in the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels in the array. A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency of 8 MHz. The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 9 TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 APPLICATION INFORMATION The minimum integration time can be calculated from the equation: T int(min) + where: n is the number of pixels 1 maximum clock frequency (n * 18) pixels ) 20ms In the case of the TSL1406RS with the maximum clock frequency of 8 MHz, the minimum integration time would be: T int(min) + 0.125 ms (384 * 18) ) 20 ms + 66.25 ms It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when inactive because the SI pulse required to start a new cycle is a low-to-high transition. The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits for integration time. If the amount of light incident on the array during a given integration period produces a saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing the period of time the light sampling window is active is to lower the output voltage level to prevent saturation. However, the integration time must still be greater than or equal to the minimum integration period. If the light intensity produces an output below desired signal levels, the output voltage level can be increased by increasing the integration period provided that the maximum integration time is not exceeded. The maximum integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated charge. The maximum integration time should not exceed 100 ms for accurate measurements. It should be noted that the data from the light sampled during one integration period is made available on the analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock period. In other words, at any given time, two groups of data are being handled by the linear array: the previous measured light data is clocked out as the next light sample is being integrated. Although the linear array is capable of running over a wide range of operating frequencies up to a maximum of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required for the analog-to-digital conversion must be less than the clock period. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 10 www.taosinc.com TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 MECHANICAL INFORMATION TOP VIEW 0.021 (0,533) DIA 13 Places 0.363 (9,220) 0.353 (8,966) 1 0.100 (2,54) x 12 = 1.2 (30,48) (Tolerance Noncumulative) 0.095 (2,41) 0.080 (2,03) 0.100 (2,54) BSC 0.535 (13,589) 0.515 (13,081) 0.510 (12,95) 0.490 (12,45) 13 0.242 (6,15) 0.222 (5,64) C L 0.091 (2,31) 0.087 (2,21) DIA (2 Places) Pixel 1 DETAIL A 2.26 (57,40) 2.24 (56,90) 2.415 (61,33) 2.405 (61,07) Pixel 768 0.228 (5,79) 0.208 (5,28) 0.086 (2,184) 0.076 (1,930) 0.130 (3,30) 0.120 (3,05) Linear Array 0.048 (1,22) 0.038 (0,97) Bonded Chip Bypass Cap DETAIL A NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). Pixel centers are located along the centerline of the mounting holes. The gap between the individual sensor dies in the array is 57 μm typical (51 μm minimum and 75 μm maximum). This drawing is subject to change without notice. The LUMENOLOGY r Company ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ Cover Glass Cover Glass (Index of Refraction = 1.52) 0.015 (0,38) Typical Free Area 0.027 (0,69) ÏÏÏÏÏ Figure 10. TSL1406R Mechanical Specifications r r Copyright E 2007, TAOS Inc. www.taosinc.com 11 TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 MECHANICAL INFORMATION TOP VIEW 0.021 (0,533) DIA 13 Places 0.100 (2,54) x 12 = 1.2 (30,48) (Tolerance Noncumulative) 0.095 (2,41) 0.080 (2,03) 0.100 (2,54) BSC 1 13 0.508 (12,90) 0.488 (12,39) 0.0563 (1,430) 0.0461 (1,171) Dia. 2 places 0.360 (9,144) 0.350 (8,890) 0.356 (9,042) 0.346 (8,788) 0.242 (6,15) 0.222 (5,64) Centerline of Pixels 0.055 (1,340) 0.045 (1,143) 0.047 (1,194) 0.037 (0,940) Pixel 1 DETAIL A 2.086 (52,984) 2.066 (52,476) 2.18 (55,4) 2.15 (54,6) Pixel 768 0.510 (12,95) 0.490 (12,45) 0.228 (5,79) 0.208 (5,28) 0.130 (3,30) 0.120 (3,05) Cover Glass (Index of Refraction = 1.52) 0.015 (0,38) Typical Free Area Linear Array 0.048 (1,22) 0.038 (0,97) Bonded Chip Bypass Cap DETAIL A NOTES: A. All linear dimensions are in inches (millimeters). B. The gap between the individual sensor dies in the array is 57 μm typical (51 μm minimum and 75 μm maximum). C. This drawing is subject to change without notice. Copyright E 2007, TAOS Inc. 12 ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ Cover Glass 0.027 (0,69) ÏÏÏÏÏÏ Figure 11. TSL1406RS Mechanical Specifications r r The LUMENOLOGY r Company www.taosinc.com TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 MECHANICAL INFORMATION THEORETICAL PIXEL LAYOUT FOR IDEAL CONTINUOUS DIE 55.50 8.00 N−2 63.50 N−1 N 1 2 3 ACTUAL MULTI-DIE PIXEL LAYOUT FOR DIE-TO-DIE EDGE JOINING 64.00 Note B 76.50 95.50 N−2 N−1 46.00 N 1 2 3 37.00 11.00 25.50 14.50 13.00 Note C NOTES: A. B. C. D. All linear dimensions are in micrometers. Spacing between outside pixels of adjacent die is typical. Die-to-die spacing. This drawing is subject to change without notice. 154.50 Figure 12. Edge Pixel Layout Dimensions The LUMENOLOGY r Company r r Copyright E 2007, TAOS Inc. www.taosinc.com 13 TSL1406R, TSL1406RS 768 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS042D − APRIL 2007 PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced Optoelectronic Solutions Incorporated. Copyright E 2007, TAOS Inc. r r The LUMENOLOGY r Company 14 www.taosinc.com