TSL2301

t t TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 D D D D D D D 102 × 1 Sensor Element Organization 300 Dots-per-Inch Pixel Pitch On-Chip 8-Bit Analog-to-Digital Converter Three-Zone Programmable Offset (Dark Level) and Gain High Speed (10 MHz) Clocked Serial Interface 1-MHz Pixel Rate Single 5-V Supply (TOP VIEW) SCLK VDD SDIN SDOUT 1 2 3 4 8 7 6 5 NC GND GND NC NC – No internal connection Description The TSL2301 is a 300-dpi, 102-pixel linear optical sensor array with an integrated 8-bit analog-to-digital converter. The pixels are on 85-µm centers and measure 85 µm (H) by 77 µm (W) with 8 µm between pixels. Associated with each pixel is a charge integrator/amplifier and sample-hold circuit. All pixels have concurrent integration periods and sampling times. Data communication is accomplished through a three-wire serial interface. The array is split into three 34-pixel zones, with each zone having programmable gain and offset levels. The TSL2301 is intended for use in high-performance, cost-critical imaging and optical sensing applications. Functional Block Diagram PIXEL ARRAY WITH INTEGRATORS AND S-H PIXCLK SI HOLD ZERO LEFT EVEN RIGHT ODD RIGHT EVEN IREF 8 SCLK SDIN SDOUT DIGITAL I/O AND CONTROL 5 DB ADDR READ WRITE OUTPUT CHARGE-TOVOLTAGE CONVERTER WITH PROGRAMMABLE GAINS AND OFFSETS VREF IREF BIAS BLOCK 3 SECTOR RESET/SAMPLE START ADCLK DUAL 8-BIT SA ADC VREF IREF www.taosinc.com Texas Advanced Optoelectronic Solutions Inc. 800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972) 673-0759 t t Copyright E 2000, TAOS Inc. 1 TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 Terminal Functions TERMINAL NAME GND SCLK SDIN SDOUT VDD NO. 6, 7 1 3 4 2 I/O Ground Clock input for SDIN and SDOUT Serial data input. Data is clocked in on the rising edge of CLK. Serial data output. Data is clocked out on the falling edge of CLK. Supply voltage, VDD is nominally 5 V. DESCRIPTION Detailed Description The sensor consist of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging on the pixels generates a photocurrent, which is then integrated by the active integration circuitry associated with each pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity (Ee) on that pixel and the integration time (tint). The array is divided into three 34-pixel zones, with each zone having programmable gain and offset (dark signal) correction. The offset correction is controlled by an 8-bit DAC and is performed in the analog domain prior to the digital conversion. There is a separate offset DAC for each of the three zones. The offset value is signed, with codes 0 – 7Fh corresponding to positive offset values and codes 80h – FFh corresponding to increasingly negative offset values. Offset adjustments should be made before setting the gain, but may have to be readjusted after the gain changes are made. The gain adjustment is controlled by a 5-bit DAC, with positive gain values ranging from 0 to 1Fh. There is a separate gain DAC for each of the three zones. Table 1 lists the gain settings and the resulting gain change. Integration, sampling, output, and reset of the integrators are performed by the control logic in response to commands input via the SDIN pin. A normal sequence of operation consists of a pixel reset (RESET), start of integration (STARTInt), sampling of integrators (SAMPLEInt), and pixel output (READPixel). Reset sets all the integrators to zero. Start of integration releases the integrators from the reset state and defines the beginning of the integration period. Sampling the integrators ends the integration period and stores the charge accumulated in each pixel in a sample and hold circuit. Reading the pixels causes the sampled value of each pixel to be converted to 8-bit digital format and output on the SDOUT pin. All 102 pixels are output sequentially unless interrupted by an abort (ABORTPixel) command or reset by a RESET command. The commands coming from the controller via the SDIN line are synchronous with the SCLK, which nominally operates at 10 MHz. The protocol for both the data and control words employs the USART convention of start/stop delimiters. There is one start bit and one stop bit. Copyright E 2000, TAOS Inc. t www.taosinc.com 2 t TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 Table 1. Gain Settings and Results GAIN CODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RELATIVE GAIN 1.00 1.02 1.05 1.07 1.09 1.12 1.15 1.18 1.21 1.24 1.27 1.31 1.34 1.38 1.43 1.47 2.17 2.22 2.27 2.33 2.38 2.44 2.50 2.56 2.63 2.70 2.78 2.86 2.94 3.03 3.13 % INCREASE GAIN CODE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RELATIVE GAIN 1.52 1.57 1.62 1.68 1.74 1.81 1.88 1.96 2.05 2.14 2.24 2.35 2.48 2.61 2.77 2.94 % INCREASE 3.23 3.33 3.45 3.57 3.70 3.85 4.00 4.17 4.35 4.55 4.76 5.00 5.26 5.56 5.88 6.25 Register address map The TSL2301 contains seven registers (Table 2). Three registers control the gain of the analog-to-digital converters (ADCs). Three other registers allow the offset of the system to be corrected. Together the gain and offset registers are used to maximize the achievable dynamic range. The last register is a mode register that selects both device cascade options and production test options. Note that device cascade options do not apply to the 8-pin packaged device. Table 2. Register Address Map ADDRESS 0 1 2 3 4 5 1F REGISTER DESCRIPTION Pixels 0–33 Offset Pixels 0–33 Gain Pixels 34–67 Offset Pixels 34–67 Gain Pixels 68–101 Offset Pixels 68–101 Gain Mode REGISTER WIDTH 8 5 8 5 8 5 4 The offset registers are 8-bit signed offsets and the gain registers are 5-bit magnitudes. The programmed offset correction is applied to the sampled energy, and then the gain is applied. (e.g., the gain will affect the offset correction). These two registers allow the user to maximize the dynamic range achievable in the given system. The mode register is used during factory testing and for future product enhancements. The user should always program zeros into the mode register. www.taosinc.com t Copyright E 2000, TAOS Inc. t 3 TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD +0.5 V Digital output current, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 to +10 mA Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA to 20 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25_C to 125_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions MIN Supply voltage, VDD High-level input voltage at SCLK, SDIN, VIH Low-level input voltage at SCLK, SDIN, VIL Operating junction temperature, TA 0 4.5 2 0.8 70 NOM 5 MAX 5.25 UNIT V V V °C Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH OH High level output voltage, SDOUT High-level out ut voltage, SDOUT TEST CONDITIONS VDD = 5.25 V, See Note 1 VDD = 4.75 V, VOL IDD VIL VIH IIH IIL Low-level Low level output voltage SDOUT voltage, Supply current Low-level input voltage (SCLK, SDIN) High-level input voltage (SCLK, SDIN) High-level input current (SCLK, SDIN) Low-level input current SCLK, SDIN VI = VDD VI = 0 VDD = 4.75 V, VDD = 4.75 V, A/D active A/D inactive 0 2 ±10 ±10 IO = 50 mA, IO = 4 mA VDD = 4.75 V IO = 4 mA 11 6 2.4 0.01 0.4 17 11 0.8 mA V V µΑ µΑ V MIN TYP MAX 3 UNIT V NOTE 1: Output high level is nominally 0.6 VDD with no load. Copyright E 2000, TAOS Inc. t www.taosinc.com 4 t TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 Optical Array Characteristics (single-die) at VDD = 5 V, TA = 25°C, λp = 590 nm, tint = 200 µs (unless otherwise noted) Ee=?????? PARAMETER DSNU PRNU Dark signal non uniformity non-uniformity Photo-response non-uniformity Dark-level effective illumination (measure of dark current) TEST CONDITIONS Gain register = 00000b, Gain register = 11111b, See Notes 3 and 4 TA = 70°C See Note 2 See Note 2 ±4% TBD MIN TYP 5 MAX 10 14 ±5% nJ/cm 2 LSB UNIT NOTES: 2. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not illuminated. 3. PRNU does not include DSNU. 4. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly illuminated at nominal white level (typical average output level = 200). Switching Characteristics over recommended operating range (unless otherwise noted) PARAMETER fmax tw(CLKH) tw(CLKL) tsu th tr tr td Ci Maximum clock frequency Clock high pulse duration Clock low pulse duration Input setup time Input hold time Rise time, output Fall time, output Delay from clock edge to data-out stable Input pin capacitance CL = 20 pF 20 TEST CONDITIONS MIN 10 30 30 20 20 10 10 20 10 TBD TYP MAX UNIT MHz ns ns ns ns ns ns ns pF Light-to-Digital Transfer Characteristics at VDD = 5 V, TA = 25°C, λp = 590 nm, tint = 200 µs (unless otherwise noted) Ee=??????? PARAMETER A-to-D converter resolution Gain register = 00000b Full-scale Full scale reference Gain register = 11111b For converter only, does not include photodiode characteristics Offset register = 00000000b Offset register = 00000000b 0 TBD 170 TBD 5 TEST CONDITIONS MIN TYP 8 6.3 2.1 ±150 17 TBD 200 TBD ±64 Gain register = 00000b Programmable offset step size Dark-level change with temperature Differential nonlinearity Integral nonlinearity Gain register = 00000b Dark level noise Power supply rejection ratio Gain register = 11111b Gain register = 11111b 0°C < TA < 70°C 0.5 1.5 2 ±0.5 ±1 0.5 1.5 TBD LSB dB LSB LSB LSB LSB 30 TBD 230 TBD LSB LSB 7.6 MAX UNIT Bits nJ/cm 2 ppm/°C Full-scale reference temperature sensitivity Gain register = 00000b Average dark level dark-level Average white level output Programmable offset steps Gain register = 11111b Gain register = 00000b Gain register = 11111b www.taosinc.com t Copyright E 2000, TAOS Inc. t 5 TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 APPLICATION INFORMATION Serial I/O SCLK SDIN Start B0 B1 B2 B3 B4 B5 B6 B7 Stop Start Serial Input Data Format SCLK SDOUT Start B0 B1 B2 B3 B4 B5 B6 B7 Stop Start Serial Output Data Format Command description The TSL2301 is a slave device that reacts strictly to commands received from the controller. There are three types of commands, reset commands, pixel action commands and register commands. These commands cause the device to perform functions such as: reset, integrate, sample, etc. Each command is described in more detail in Table 3. All commands are single-byte except for the register write command, which is two bytes. There is a requirement for delay of 8 clocks after each command to allow for processing of the command. Table 3. TSL2301 Command Set COMMAND IRESET RESET STARTInt SAMPLEInt READPixel ABORTPixel READHold READHoldNStart REGWrite REGRead Interface Reset Reset Integration and Read blocks Start pixel integration Stop integration and sample results Dump serial the contents of each sampled integrator Abort any READPixel operation in progress Combination of SAMPLEInt and READPixel commands Combination of SAMPLEInt, READPixel and STARTInt commands Write a gain, offset or mode register Read a gain, offset or mode register DESCRIPTION Copyright E 2000, TAOS Inc. t www.taosinc.com 6 t TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 Reset Commands Reset commands are used to put the TSL2301 into a known state. IRESET – Interface Initialization Encoding: Break Character IRESET initializes the internal state machine that keeps track of which command bytes have been received. This command should be first and given only once after power-up to synchronize TSL2301’s command interpreter. RESET – Main Reset Encoding: 0x1b: RESET resets most of the internal control logic of the TSL2301 and any READPixel command currently in progress is aborted. RESET puts the pixel integrators into the auto-zero/reset state. Any values that were being held in the array’s sample/hold circuits are lost. NOTE: On power up of the TSL2301, it is necessary to hold SDIN high for 30 clocks before initiating a reset command. In addition, to fully reset the device, it is recommended that 3 consecutive RESET commands be issued as part of the power up routine. NOTE: The value on the SDOUT pin is not guaranteed from the time power is applied until 30 clocks after the first RESET command is issued. Pixel Action Commands Pixel action commands allow the user to control pixel integration and reading of pixel data. STARTInt – Start Integration Encoding: 0x08: STARTInt causes each pixel to leave the reset state and to start integrating. The actual execution of STARTInt is delayed 20 clocks until the auto-zero cycle of the pixels has been completed. SAMPLEInt – Stop Integration Encoding: 0x10: SAMPLEInt causes each pixel to store its integrator’s contents into a sample and hold circuit. Also, the Integrator is returned to the reset state. READPixel – Read Pixel Data Encoding: 0x02: READPixel causes the sampled value of each pixel to be converted to an 8-bit digital value that is clocked out on the SDOUT pin. The LSB is the first data bit, which is preceded by a START bit (logic 0) and followed by a STOP bit (logic 1). Each pixel in the device is presented on SDOUT starting from pixel 00 and completes with pixel 101. It takes 20 clocks before the first pixel is available to be read and 10 clocks per pixel thereafter until all pixels are output. Gain and offset registers are used to adjust the ADC converter to maximize dynamic range and should be programmed prior to invoking the READPixel command. www.taosinc.com t Copyright E 2000, TAOS Inc. t 7 TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 ABORTPixel – Abort Pixel Data Read Encoding: 0x19: ABORTPixel is an optional command that stops a READPixel command during its execution. It also causes pixel integration to terminate and to enter the auto-zero/reset state. Any values that were being held in the array’s sample/hold circuits are lost. READHold – Sample and Read Combination Encoding: 0x12: READHold is a macro command that combines both the SAMPLEInt and READPixel commands into a single command. It is also provided as a shortcut for advanced users. READHoldNStart Combination Encoding: 0x16: READHold is a macro command that combines the SAMPLEInt, READPixel, and StartInt commands into a single command, and is provided as a shortcut for advanced users. Register Commands The register commands provide the user the capability of setting gain and offset corrections for each of the three zones of pixels. a4–a0 refer to the register address as given in Table 2. REGWrite – Write a Gain/Offset/Mode Register Encoding: 0x40 : REGWrite writes a value into either a gain, offset, or mode register. The 5-bit address of the register is encoded into the command byte (the first byte). A second byte, which contains the data to be written, follows the command byte. REGRead – Read a Gain/Offset/Mode Register Encoding: 0x60: REGRead reads the value previously stored in a gain, offset, or mode register. The 5-bit address of the register is encoded into the command byte. Then, following receipt of the REGRead command, the device places the contents of the selected register onto the SDOUT pin, LSB first. Data will be available to read 4 clocks after the execution of the command. Table 4. Summary of Command Types and Formats COMMAND TYPE Reset Pixel action Register read Register write < Command byte > < Command byte > < Command byte > < Command byte > < Data byte> FORMAT Copyright E 2000, TAOS Inc. t www.taosinc.com 8 t TSL2301 102 × 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG TO DIGITAL CONVERTER TAOS007 – JULY 2000 Normal programming sequence This section describes a typical programming sequence that can be used with the TSL2301 device: 30 clocks with SDIN high Send(RESET); Send(RESET); Send(RESET); Calibration Cycle * * while(1) for(i=0;i