ICM-42688-P Datasheet
High Precision 6-Axis MEMS MotionTrackingTM Device
ICM-42688-P HIGHLIGHTS
ICM-42688-P FEATURES
The ICM-42688-P is a 6-axis MEMS
MotionTracking device that combines a 3-axis
gyroscope and a 3-axis accelerometer. It has a
configurable host interface that supports I3CSM,
I2C and SPI serial communication, features a 2 kB
FIFO and 2 programmable interrupts with ultralow-power wake-on-motion support to minimize
system power consumption.
ICM-42688-P supports highly accurate external clock
input, that helps to reduce system level sensitivity
error, improve orientation measurement from
gyroscope data, reduce ODR sensitivity to
temperature and device to device variation.
The device includes industry first 20-bits data format
support in FIFO for high-data resolution. This FIFO
format encapsulates 19-bits of gyroscope data and 18bits of accelerometer data.
Other industry-leading features include
InvenSense on-chip APEX Motion Processing
engine for gesture recognition, activity
classification, and pedometer, along with
programmable digital filters, and an embedded
temperature sensor.
•
•
•
•
•
•
Gyroscope Noise: 2.8 mdps/Hz &
Accelerometer Noise: 70 µg/Hz
o Low-Noise mode 6-axis current
consumption of 0.88 mA
User selectable Gyro Full-scale range (dps):
± 15.6/31.2/62.5/125/250/500/1000/2000
User selectable Accelerometer Full-scale
range (g): ± 2/4/8/16
User-programmable digital filters for gyro,
accel, and temp sensor
APEX Motion Functions:
o Pedometer, Tilt Detection, Tap Detection
o Wake on Motion, Raise to Wake/Sleep,
Significant Motion Detection
Host interface: 12.5 MHz I3CSM, 1 MHz I2C,
24 MHz SPI
APPLICATIONS
•
•
•
•
•
•
AR/VR Controllers
Head Mounted Displays
Wearables
Sports
Robotics
IoT Applications
The device supports a VDD operating range of
1.71V to 3.6V, and a separate digital IO supply,
VDDIO from 1.71V to 3.6V.
ORDERING INFORMATION
BLOCK DIAGRAM
PART
TEMP RANGE
ICM-42688-P†
−40°C to +85°C
PACKAGE
2.5x3mm 14-Pin
LGA
†Denotes RoHS and Green-Compliant Package
TDK-INVENSENSE SENSORS FOR SMARTPHONE, MOBILE & IOT APPLICATIONS
Parameter
GYRO Noise (mdps/rt-Hz)
GYRO Offset Temp Stability (mdps/°C)
GYRO Range & Resolution
ACCEL Noise (µg/rt-Hz)
ACCEL Range & Resolution
ODR & Sample Synch
This document contains information on a pre-production product,
and should not be considered for production until qualification is
complete. InvenSense Inc. reserves the right to change specifications
and information herein without notice.
ICM-40607
ICM-42605
ICM-42686-P
ICM-42688-P
Sensorhub
Sensorhub
Handheld Action
HMD & Robotics
7
±30
±2000dps; 16-bits
110
±16g; 16-bits
8kHz; No RTC
3.8
±20
±2000dps; 16-bits
70
±16g; 16-bits
8kHz; No RTC
5.3
±10
±4000dps; 16/19-bits
70
±32g; 16/18-bits
32kHz; RTC
2.8
±5
±2000dps; 16/19-bits
AXY: 65; AZ: 70
±16g; 16/18-bits
32kHz; RTC
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
www.invensense.com
Document Number: DS-000347
Revision: 1.2
Rev. Date: 04/19/2020
ICM-42688-P
TABLE OF CONTENTS
ICM-42688-P Highlights ....................................................................................................................................... 1
Block Diagram ...................................................................................................................................................... 1
ICM-42688-P Features ......................................................................................................................................... 1
Applications ......................................................................................................................................................... 1
Ordering Information ........................................................................................................................................... 1
TDK-Invensense Sensors for Smartphone, Mobile & IoT Applications ................................................................ 1
Table of Figures ............................................................................................................................................................... 8
Table of Tables ................................................................................................................................................................ 8
1
2
3
4
Introduction ......................................................................................................................................................... 9
1.1
Purpose and Scope .................................................................................................................................... 9
1.2
Product Overview...................................................................................................................................... 9
1.3
Applications............................................................................................................................................... 9
Features ............................................................................................................................................................. 10
2.1
Gyroscope Features ................................................................................................................................ 10
2.2
Accelerometer Features .......................................................................................................................... 10
2.3
Motion Features ...................................................................................................................................... 10
2.4
Additional Features ................................................................................................................................. 10
Electrical Characteristics .................................................................................................................................... 11
3.1
Gyroscope Specifications ........................................................................................................................ 11
3.2
Accelerometer Specifications.................................................................................................................. 12
3.3
Electrical Specifications ........................................................................................................................... 13
3.4
I2C Timing Characterization ..................................................................................................................... 15
3.5
SPI Timing Characterization – 4-Wire SPI Mode ..................................................................................... 16
3.6
SPI Timing Characterization – 3-Wire SPI Mode ..................................................................................... 17
3.7
Absolute Maximum Ratings .................................................................................................................... 18
Applications Information ................................................................................................................................... 19
4.1
Pin Out Diagram and Signal Description ................................................................................................. 19
4.2
Typical Operating Circuit ......................................................................................................................... 20
4.3
Bill of Materials for External Components .............................................................................................. 21
4.4
System Block Diagram ............................................................................................................................. 22
4.5
Overview ................................................................................................................................................. 22
4.6
Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 22
4.7
Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning......................................... 22
4.8
I3CSM, I2C and SPI Host Interface ............................................................................................................. 22
4.9
Self-Test................................................................................................................................................... 22
4.10
Clocking............................................................................................................................................... 23
4.11
Sensor Data Registers ......................................................................................................................... 23
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5
6
4.12
Interrupts ............................................................................................................................................ 23
4.13
Digital-Output Temperature Sensor ................................................................................................... 24
4.14
Bias and LDOs ..................................................................................................................................... 24
4.15
Charge Pump ...................................................................................................................................... 24
4.16
Standard Power Modes ...................................................................................................................... 24
Signal Path ......................................................................................................................................................... 25
5.1
Summary of Parameters Used to Configure the Signal Path .................................................................. 25
5.2
Notch Filter ............................................................................................................................................. 25
5.3
Anti-Alias Filter ........................................................................................................................................ 27
5.4
User Programmable Offset ..................................................................................................................... 29
5.5
UI Filter Block .......................................................................................................................................... 29
5.6
UI Path ODR And FSR Selection ............................................................................................................... 33
FIFO .................................................................................................................................................................... 36
6.1
Packet Structure ...................................................................................................................................... 36
6.2
FIFO Header ............................................................................................................................................ 38
6.3
Maximum FIFO Storage ........................................................................................................................... 39
6.4
FIFO Configuration Registers ................................................................................................................... 39
7
Programmable Interrupts .................................................................................................................................. 41
8
APEX Motion Functions ..................................................................................................................................... 42
9
10
8.1
APEX ODR Support .................................................................................................................................. 42
8.2
DMP Power Save Mode .......................................................................................................................... 43
8.3
Pedometer Programming ........................................................................................................................ 43
8.4
Tilt Detection Programming .................................................................................................................... 44
8.5
Raise to Wake/Sleep Programming ........................................................................................................ 44
8.6
Tap Detection Programming ................................................................................................................... 45
8.7
Wake on Motion Programming............................................................................................................... 46
8.8
Significant Motion Detection Programming ........................................................................................... 46
Digital Interface ................................................................................................................................................. 48
9.1
I3CSM, I2C and SPI Serial Interfaces .......................................................................................................... 48
9.2
I3CSM Interface ........................................................................................................................................ 48
9.3
I2C Interface............................................................................................................................................. 48
9.4
I2C Communications Protocol ................................................................................................................. 48
9.5
I2C Terms ................................................................................................................................................. 50
9.6
SPI Interface ............................................................................................................................................ 52
Assembly ............................................................................................................................................................ 53
10.1
Orientation of Axes ............................................................................................................................. 53
10.2
Package Dimensions ........................................................................................................................... 54
11
Part Number Package Marking .......................................................................................................................... 56
12
Use Notes ........................................................................................................................................................... 57
12.1
Accelerometer Mode Transitions ....................................................................................................... 57
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13
14
12.2
Accelerometer Low Power (LP) Mode Averaging Filter Setting.......................................................... 57
12.3
Settings for I2C, I3CSM, and SPI Operation ........................................................................................... 57
12.4
Notch Filter and Anti-Alias Filter Operation ....................................................................................... 57
12.5
External Clock Input Effect on ODR .................................................................................................... 57
12.6
INT_ASYNC_RESET Configuration ....................................................................................................... 58
12.7
FIFO Timestamp Interval Scaling......................................................................................................... 58
12.8
Supplementary Information for FIFO_HOLD_LAST_DATA_EN ........................................................... 58
Register Map ...................................................................................................................................................... 60
13.1
User Bank 0 Register Map................................................................................................................... 60
13.2
User Bank 1 Register Map................................................................................................................... 61
13.3
User Bank 2 Register Map................................................................................................................... 62
13.4
User Bank 4 Register Map................................................................................................................... 62
User Bank 0 Register Map – Descriptions .......................................................................................................... 63
14.1
DEVICE_CONFIG .................................................................................................................................. 63
14.2
DRIVE_CONFIG .................................................................................................................................... 63
14.3
INT_CONFIG ........................................................................................................................................ 64
14.4
FIFO_CONFIG ...................................................................................................................................... 64
14.5
TEMP_DATA1 ...................................................................................................................................... 64
14.6
TEMP_DATA0 ...................................................................................................................................... 65
14.7
ACCEL_DATA_X1 ................................................................................................................................. 65
14.8
ACCEL_DATA_X0 ................................................................................................................................. 65
14.9
ACCEL_DATA_Y1 ................................................................................................................................. 65
14.10
ACCEL_DATA_Y0 ................................................................................................................................. 66
14.11
ACCEL_DATA_Z1 ................................................................................................................................. 66
14.12
ACCEL_DATA_Z0 ................................................................................................................................. 66
14.13
GYRO_DATA_X1 .................................................................................................................................. 66
14.14
GYRO_DATA_X0 .................................................................................................................................. 66
14.15
GYRO_DATA_Y1 .................................................................................................................................. 67
14.16
GYRO_DATA_Y0 .................................................................................................................................. 67
14.17
GYRO_DATA_Z1 .................................................................................................................................. 67
14.18
GYRO_DATA_Z0 .................................................................................................................................. 67
14.19
TMST_FSYNCH .................................................................................................................................... 67
14.20
TMST_FSYNCL ..................................................................................................................................... 68
14.21
INT_STATUS ........................................................................................................................................ 68
14.22
FIFO_COUNTH..................................................................................................................................... 68
14.23
FIFO_COUNTL ..................................................................................................................................... 69
14.24
FIFO_DATA .......................................................................................................................................... 69
14.25
APEX_DATA0 ....................................................................................................................................... 69
14.26
APEX_DATA1 ....................................................................................................................................... 69
14.27
APEX_DATA2 ....................................................................................................................................... 70
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15
14.28
APEX_DATA3 ....................................................................................................................................... 70
14.29
APEX_DATA4 ....................................................................................................................................... 71
14.30
APEX_DATA5 ....................................................................................................................................... 71
14.31
INT_STATUS2 ...................................................................................................................................... 72
14.32
INT_STATUS3 ...................................................................................................................................... 72
14.33
SIGNAL_PATH_RESET .......................................................................................................................... 72
14.34
INTF_CONFIG0 .................................................................................................................................... 73
14.35
INTF_CONFIG1 .................................................................................................................................... 74
14.36
PWR_MGMT0 ..................................................................................................................................... 75
14.37
GYRO_CONFIG0 .................................................................................................................................. 76
14.38
ACCEL_CONFIG0 ................................................................................................................................. 77
14.39
GYRO_CONFIG1 .................................................................................................................................. 78
14.40
GYRO_ACCEL_CONFIG0 ...................................................................................................................... 79
14.41
ACCEL_CONFIG1 ................................................................................................................................. 80
14.42
TMST_CONFIG .................................................................................................................................... 80
14.43
APEX_CONFIG0 ................................................................................................................................... 81
14.44
SMD_CONFIG ...................................................................................................................................... 81
14.45
FIFO_CONFIG1 .................................................................................................................................... 82
14.46
FIFO_CONFIG2 .................................................................................................................................... 82
14.47
FIFO_CONFIG3 .................................................................................................................................... 82
14.48
FSYNC_CONFIG ................................................................................................................................... 83
14.49
INT_CONFIG0 ...................................................................................................................................... 83
14.50
INT_CONFIG1 ...................................................................................................................................... 84
14.51
INT_SOURCE0 ..................................................................................................................................... 84
14.52
INT_SOURCE1 ..................................................................................................................................... 85
14.53
INT_SOURCE3 ..................................................................................................................................... 85
14.54
INT_SOURCE4 ..................................................................................................................................... 86
14.55
FIFO_LOST_PKT0 ................................................................................................................................. 86
14.56
FIFO_LOST_PKT1 ................................................................................................................................. 86
14.57
SELF_TEST_CONFIG............................................................................................................................. 87
14.58
WHO_AM_I ......................................................................................................................................... 87
14.59
REG_BANK_SEL ................................................................................................................................... 87
User Bank 1 Register Map – Descriptions .......................................................................................................... 88
15.1
SENSOR_CONFIG0 .............................................................................................................................. 88
15.2
GYRO_CONFIG_STATIC2 ..................................................................................................................... 88
15.3
GYRO_CONFIG_STATIC3 ..................................................................................................................... 88
15.4
GYRO_CONFIG_STATIC4 ..................................................................................................................... 89
15.5
GYRO_CONFIG_STATIC5 ..................................................................................................................... 89
15.6
GYRO_CONFIG_STATIC6 ..................................................................................................................... 89
15.7
GYRO_CONFIG_STATIC7 ..................................................................................................................... 89
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16
17
15.8
GYRO_CONFIG_STATIC8 ..................................................................................................................... 90
15.9
GYRO_CONFIG_STATIC9 ..................................................................................................................... 90
15.10
GYRO_CONFIG_STATIC10 ................................................................................................................... 90
15.11
XG_ST_DATA ....................................................................................................................................... 91
15.12
YG_ST_DATA ....................................................................................................................................... 91
15.13
ZG_ST_DATA ....................................................................................................................................... 91
15.14
TMSTVAL0 ........................................................................................................................................... 91
15.15
TMSTVAL1 ........................................................................................................................................... 92
15.16
TMSTVAL2 ........................................................................................................................................... 92
15.17
INTF_CONFIG4 .................................................................................................................................... 92
15.18
INTF_CONFIG5 .................................................................................................................................... 93
15.19
INTF_CONFIG6 .................................................................................................................................... 93
User Bank 2 Register Map – Descriptions .......................................................................................................... 94
16.1
ACCEL_CONFIG_STATIC2 .................................................................................................................... 94
16.2
ACCEL_CONFIG_STATIC3 .................................................................................................................... 94
16.3
ACCEL_CONFIG_STATIC4 .................................................................................................................... 94
16.4
XA_ST_DATA ....................................................................................................................................... 94
16.5
YA_ST_DATA ....................................................................................................................................... 95
16.6
ZA_ST_DATA ....................................................................................................................................... 95
User Bank 4 Register Map – Descriptions .......................................................................................................... 96
17.1
APEX_CONFIG1 ................................................................................................................................... 96
17.2
APEX_CONFIG2 ................................................................................................................................... 97
17.3
APEX_CONFIG3 ................................................................................................................................... 98
17.4
APEX_CONFIG4 ................................................................................................................................... 99
17.5
APEX_CONFIG5 ................................................................................................................................... 99
17.6
APEX_CONFIG6 ................................................................................................................................. 100
17.7
APEX_CONFIG7 ................................................................................................................................. 100
17.8
APEX_CONFIG8 ................................................................................................................................. 100
17.9
APEX_CONFIG9 ................................................................................................................................. 101
17.10
ACCEL_WOM_X_THR ........................................................................................................................ 101
17.11
ACCEL_WOM_Y_THR ........................................................................................................................ 101
17.12
ACCEL_WOM_Z_THR ........................................................................................................................ 101
17.13
INT_SOURCE6 ................................................................................................................................... 102
17.14
INT_SOURCE7 ................................................................................................................................... 102
17.15
INT_SOURCE8 ................................................................................................................................... 103
17.16
INT_SOURCE9 ................................................................................................................................... 103
17.17
INT_SOURCE10 ................................................................................................................................. 104
17.18
OFFSET_USER0 .................................................................................................................................. 104
17.19
OFFSET_USER1 .................................................................................................................................. 104
17.20
OFFSET_USER2 .................................................................................................................................. 105
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17.21
OFFSET_USER3 .................................................................................................................................. 105
17.22
OFFSET_USER4 .................................................................................................................................. 105
17.23
OFFSET_USER5 .................................................................................................................................. 105
17.24
OFFSET_USER6 .................................................................................................................................. 106
17.25
OFFSET_USER7 .................................................................................................................................. 106
17.26
OFFSET_USER8 .................................................................................................................................. 106
18
Reference ......................................................................................................................................................... 107
19
Document Information .................................................................................................................................... 108
19.1
Revision History ................................................................................................................................ 108
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ICM-42688-P
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram ........................................................................................................................................ 15
Figure 2. 4-Wire SPI Bus Timing Diagram ............................................................................................................................ 16
Figure 3. 3-Wire SPI Bus Timing Diagram ............................................................................................................................ 17
Figure 4. Pin Out Diagram for ICM-42688-P 2.5x3.0x0.91 mm LGA.................................................................................... 19
Figure 5. ICM-42688-P Application Schematic (I3CSM / I2C Interface to Host) ..................................................................... 20
Figure 6. ICM-42688-P Application Schematic (SPI Interface to Host) ................................................................................ 20
Figure 7. ICM-42688-P System Block Diagram .................................................................................................................... 22
Figure 8. ICM-42688-P Signal Path ...................................................................................................................................... 25
Figure 9. FIFO Packet Structure ........................................................................................................................................... 36
Figure 10. Maximum FIFO Storage ...................................................................................................................................... 39
Figure 11. START and STOP Conditions ............................................................................................................................. 49
Figure 12. Acknowledge on the I2C Bus ............................................................................................................................... 49
Figure 13. Complete I2C Data Transfer ................................................................................................................................. 50
Figure 14. Typical SPI Master/Slave Configuration .............................................................................................................. 52
Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................. 53
TABLE OF TABLES
Table 1. Gyroscope Specifications ....................................................................................................................................... 11
Table 2. Accelerometer Specifications ................................................................................................................................. 12
Table 3. D.C. Electrical Characteristics ................................................................................................................................ 13
Table 4. A.C. Electrical Characteristics ................................................................................................................................. 14
Table 5. I2C Timing Characteristics ....................................................................................................................................... 15
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ......................................................................................... 16
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ......................................................................................... 17
Table 8. Absolute Maximum Ratings .................................................................................................................................... 18
Table 9. Signal Descriptions ................................................................................................................................................. 19
Table 10. Bill of Materials ...................................................................................................................................................... 21
Table 11. Standard Power Modes for ICM-42688-P ............................................................................................................. 24
Table 12. I2C Terms .............................................................................................................................................................. 51
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ICM-42688-P
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on the ICM-42688-P
Single-Interface MotionTracking device. The device is housed in a small 2.5x3x0.91 mm 14-pin LGA package.
1.2 PRODUCT OVERVIEW
The ICM-42688-P is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometer in a small
2.5x3x0.91 mm (14-pin LGA) package. It also features a 2K-byte FIFO that can lower the traffic on the serial bus interface, and
reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. ICM42688-P, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system
level integration of discrete devices, guaranteeing optimal motion performance for consumers.
The gyroscope supports eight programmable full-scale range settings from ±15.625dps to ±2000dps, and the accelerometer supports
four programmable full-scale range settings from ±2g to ±16g.
ICM-42688-P also supports external clock input for highly accurate 31kHz to 50kHz clock, that helps to reduce system level sensitivity
error, improve orientation measurement from gyroscope data, reduce ODR sensitivity to temperature and device to device
variation.
The device includes industry first 20-bits data format support in FIFO for high-data resolution. This FIFO format encapsulates 19-bits
of gyroscope data and 18-bits of accelerometer data for high precision applications. Other industry-leading features include on-chip
16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features
I3CSM, I2C and SPI serial interfaces, a VDD operating range of 1.71 V to 3.6 V, and a separate VDDIO operating range of 1.71 V to 3.6
V.
The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface supports speeds up to
12.5MHz (data rates up to 12.5Mbps in SDR mode, 25Mbps in DDR mode), the I 2C interface supports speeds up to 1 MHz, and the
SPI interface supports speeds up to 24 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
2.5x3x0.91 mm (14-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness by
supporting 20,000g shock reliability.
1.3
APPLICATIONS
•
•
•
•
•
AR/VR Controllers
Head Mounted Displays
Wearables
Sports
Robotics
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ICM-42688-P
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-42688-P includes a wide range of features:
• Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±15.625, ±31.25,
±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec
• Low Noise (LN) power mode support
• Digitally-programmable low-pass filters
• Factory calibrated sensitivity scale factor
• Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-42688-P includes a wide range of features:
• Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2g, ±4g ±8g and ±16g
• Low Noise (LN) and Low Power (LP) power modes support
• User-programmable interrupts
• Wake-on-motion interrupt for low power operation of applications processor
• Self-test
2.3 MOTION FEATURES
ICM-42688-P includes the following motion features, also known as APEX (Advanced Pedometer and Event Detection – neXt gen)
• Pedometer: Tracks Step Count, also issues Step Detect interrupt
• Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 for more than a programmable time
• Raise to Wake/Sleep: Gesture detection for wake and sleep events. Interrupt is issued when either of these two events are
detected
• Tap Detection: Issues an interrupt when a tap is detected, along with the tap count
• Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold
• Significant Motion Detection: Detects Significant Motion if Wake on Motion events are detected during a programmable time
window
2.4 ADDITIONAL FEATURES
ICM-42688-P includes the following additional features:
• External clock input supports highly accurate clock input from 31kHz to 50kHz, helps to reduce system level sensitivity error,
improve orientation measurement from gyroscope data, reduce ODR sensitivity to temperature and device to device variation
• 2K byte FIFO buffer enables the applications processor to read the data in bursts
• 20-bits data format support in FIFO for high-data resolution
• User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
• 12.5MHz I3CSM (data rates up to 12.5Mbps in SDR mode, 25Mbps in DDR mode) / 1 MHz I2C / 24 MHz SPI slave host interface
• Digital-output temperature sensor
• Smallest and thinnest LGA package for portable devices: 2.5x3x0.91 mm (14-pin LGA)
• 20,000 g shock tolerant
• MEMS structure hermetically sealed and bonded at wafer level
• RoHS and Green compliant
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ICM-42688-P
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
Full-Scale Range
Gyroscope ADC Word Length
Sensitivity Scale Factor
GYRO_FS_SEL=0
GYRO_FS_SEL =1
±2000
º/s
±1000
º/s
2
2
GYRO_FS_SEL =2
±500
º/s
2
GYRO_FS_SEL =3
±250
º/s
2
GYRO_FS_SEL =4
±125
º/s
2
GYRO_FS_SEL =5
±62.5
º/s
2
GYRO_FS_SEL =6
±31.25
º/s
2
GYRO_FS_SEL =7
±15.625
º/s
2
16
bits
2, 5
GYRO_FS_SEL=0
GYRO_FS_SEL =1
16.4
LSB/(º/s)
2
32.8
LSB/(º/s)
2
GYRO_FS_SEL =2
65.5
LSB/(º/s)
2
GYRO_FS_SEL =3
131
LSB/(º/s)
2
GYRO_FS_SEL =4
262
LSB/(º/s)
2
GYRO_FS_SEL =5
524.3
LSB/(º/s)
2
GYRO_FS_SEL =6
1048.6
LSB/(º/s)
2
GYRO_FS_SEL =7
2097.2
LSB/(º/s)
2
±0.5
%
1
±0.005
%/ºC
3
Output in two’s complement format
Sensitivity Scale Factor Initial Tolerance
Component and Board-level, 25°C
Sensitivity Scale Factor Variation Over
Temperature
0°C to +70°C
Nonlinearity
Best fit straight line; 25°C
±0.1
%
3
Cross-Axis Sensitivity
Board-level
±1.25
%
3
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
Board-level, 25°C
ZRO Variation vs. Temperature
0°C to +70°C
±0.5
º/s
3
±0.005
º/s/ºC
3
OTHER PARAMETERS
Rate Noise Spectral Density
@ 10 Hz
0.0028
º/s /√Hz
1
Total RMS Noise
Bandwidth = 100 Hz
0.028
º/s-rms
4
29
KHz
1
Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start-Up Time
Output Data Rate
25
ODR < 1kHz
5
500
Hz
2
ODR ≥ 1kHz
Time from gyro enable to gyro drive ready
42
3979
Hz
ms
Hz
2
3
2
3.
4.
5.
Tested in production.
Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.
Calculated from Rate Noise Spectral Density.
20-bits data format supported in FIFO, see section 6.1.
Page 11 of 109
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30
12.5
Table 1. Gyroscope Specifications
Notes:
1.
2.
27
32000
ICM-42688-P
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
Full-Scale Range
ACCEL_FS_SEL =0
±16
g
ACCEL_FS_SEL =1
±8
g
2
2
ACCEL_FS_SEL =2
±4
g
2
ACCEL_FS_SEL =3
±2
g
2
16
bits
2, 5
ACCEL_FS_SEL =0
2,048
LSB/g
2
ACCEL_FS_SEL =1
4,096
LSB/g
2
ACCEL_FS_SEL =2
8,192
LSB/g
2
16,384
LSB/g
2
Sensitivity Scale Factor Initial Tolerance
ACCEL_FS_SEL =3
Component and Board-level, 25°C
±0.5
%
1
Sensitivity Change vs. Temperature
-40°C to +85°C
±0.005
%/ºC
3
Nonlinearity
Best Fit Straight Line, ±2g
±0.1
%
3
Cross-Axis Sensitivity
Board-level
±1
%
3
Initial Tolerance
Board-level, all axes
Zero-G Level Change vs. Temperature
-40°C to +85°C
ADC Word Length
Sensitivity Scale Factor
Output in two’s complement format
ZERO-G OUTPUT
±20
mg
3
±0.15
mg/ºC
3
X and Y-axis
65
µg/√Hz
1
Z-axis
70
µg/√Hz
1
X and Y-axis
0.65
mg-rms
4
Z-axis
0.70
mg-rms
4
OTHER PARAMETERS
Power Spectral Density
RMS Noise
Low-Pass Filter Response
Accelerometer Startup Time
Output Data Rate
@ 10 Hz
Bandwidth = 100 Hz
ODR < 1kHz
5
500
Hz
2
ODR ≥ 1kHz
From sleep mode to valid data
42
3979
Hz
ms
Hz
2
3
2
1.5625
Table 2. Accelerometer Specifications
Notes:
1.
2.
3.
4.
5.
Tested in production.
Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.
Calculated from Power Spectral Density.
20-bits data format supported in FIFO, see section 6.1.
Page 12 of 109
Document Number: DS-000347
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32000
ICM-42688-P
ELECTRICAL SPECIFICATIONS
3.3
3.3.1
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
VDD
1.71
1.8
3.6
V
1
VDDIO
1.71
1.8
3.6
V
1
SUPPLY VOLTAGES
SUPPLY CURRENTS
Low-Noise Mode
Full-Chip Sleep Mode
Specified Temperature Range
6-Axis Gyroscope + Accelerometer
0.88
mA
2
3-Axis Accelerometer
0.28
mA
2
3-Axis Gyroscope
0.73
mA
2
At 25ºC
7.5
µA
2
°C
1
TEMPERATURE RANGE
Performance parameters are not applicable
beyond Specified Temperature Range
-40
Table 3. D.C. Electrical Characteristics
Notes:
1.
2.
Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.
Page 13 of 109
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Revision: 1.2
+85
ICM-42688-P
3.3.2
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
Supply Ramp Time
CONDITIONS
MIN
SUPPLIES
Monotonic ramp. Ramp rate is 10% to 90% of
the final value
TYP
0.01
MAX
3
Power Supply Noise
10
UNITS
ms
NOTES
1
mV
peak-peak
1
°C
LSB
bits
Hz
°C
µs
LSB/°C
LSB/°C
1
3
2
2
3
2
1
1
ms
1
TEMPERATURE SENSOR
Operating Range
25°C Output
ADC Resolution
ODR
Room Temperature Offset
Stabilization Time
Sensitivity
Sensitivity for FIFO data
Ambient
Start-up time for register read/write
From power-up
-40
85
0
16
Output in two’s complement format
With Filter
25°C
25
-5
8000
5
14000
Untrimmed
132.48
2.07
POWER-ON RESET
1
I2C ADDRESS
AP_AD0 = 0
AP_AD0 = 1
I2C ADDRESS
1101000
1101001
DIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
0.7*VDDIO
VIH, High Level Input Voltage
V
VIL, Low Level Input Voltage
0.3*VDDIO
CI, Input Capacitance
< 10
DIGITAL OUTPUT (SDO, INT1, INT2)
0.9*VDDIO
VOH, High Level Output Voltage
RLOAD=1 MΩ;
VOL1, LOW-Level Output Voltage
RLOAD=1 MΩ;
VOL.INT, INT Low-Level Output Voltage
Output Leakage Current
OPEN=1, 0.3 mA sink
Current
OPEN=1
tINT, INT Pulse Width
int_tpulse_duration= 0 , 1 (100us, 8us ) ;
V
1
pF
V
0.1*VDDIO
V
0.1
V
100
1
nA
8
100
µs
VIL, LOW-Level Input Voltage
-0.5 V
0.3*VDDIO
V
VIH, HIGH-Level Input Voltage
0.7*VDDIO
VDDIO +
0.5 V
V
I2C I/O (SCL, SDA)
Vhys, Hysteresis
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
0.1*VDDIO
3 mA sink current
0
VOL=0.4 V
VOL=0.6 V
3
6
Output Leakage Current
tof, Output Fall Time from VIHmax to VILmax
Clock Frequency Initial Tolerance
Frequency Variation over Temperature
Clock Frequency
20+0.1Cb
1
nA
300
ns
INTERNAL CLOCK SOURCE
CLKSEL=`2b00 or gyro inactive; 25°C
-3
+3
%
1
CLK_SEL=`2b01 and gyro active; 25°C
+1
%
1
CLK_SEL=`2b00 or gyro inactive; -40°C to +85°C
±3
%
1
CLK_SEL=`2b01 and gyro active; -40oC to +85oC
EXTERNAL CLOCK SOURCE
31
±2
%
1
50
kHz
1
-1
Expected results based on design, will be updated after characterization. Not tested in production.
Guaranteed by design.
Production tested.
Page 14 of 109
Document Number: DS-000347
Revision: 1.2
V
mA
mA
100
Cb bus capacitance in pf
Table 4. A.C. Electrical Characteristics
Notes:
1.
2.
3.
V
0.4
32
ICM-42688-P
3.4
I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
Parameters
Conditions
I2C TIMING
I2C FAST-MODE PLUS
Min
Typical
fSCL, SCL Clock Frequency
Max
Units
Notes
1
MHz
1
tHD.STA, (Repeated) START Condition Hold Time
0.26
µs
1
tLOW, SCL Low Period
0.5
µs
1
tHIGH, SCL High Period
0.26
µs
1
tSU.STA, Repeated START Condition Setup Time
0.26
µs
1
tHD.DAT, SDA Data Hold Time
0
µs
1
tSU.DAT, SDA Data Setup Time
50
ns
1
tr, SDA and SCL Rise Time
Cb bus cap. from 10 to 400 pF
120
ns
1
tf, SDA and SCL Fall Time
Cb bus cap. from 10 to 400 pF
120
ns
1
tSU.STO, STOP Condition Setup Time
0.5
µs
1
tBUF, Bus Free Time Between STOP and START
Condition
0.5
µs
1
Cb, Capacitive Load for each Bus Line
pF
1
tVD.DAT, Data Valid Time
< 400
0.45
µs
1
tVD.ACK, Data Valid Acknowledge Time
0.45
µs
1
Table 5. I2C Timing Characteristics
Notes:
1.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf
SDA
tSU.DAT
tr
70%
30%
70%
30%
continued below at
tf
SCL
tr
70%
30%
S
tHD.STA
tVD.DAT
70%
30%
tHD.DAT
1/fSCL
tLOW
1st clock cycle
9th clock cycle
tHIGH
tBUF
SDA
70%
30%
A
tSU.STA
tHD.STA
SCL
70%
30%
Sr
tSU.STO
tVD.ACK
9th clock cycle
Figure 1. I2C Bus Timing Diagram
Page 15 of 109
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P
S
A
ICM-42688-P
SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE
3.5
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
24
MHz
1
SPI TIMING
Default
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
17
ns
1
tHIGH, SCLK High Period
17
ns
1
tSU.CS, CS Setup Time
39
ns
1
tHD.CS, CS Hold Time
18
ns
1
tSU.SDI, SDI Setup Time
13
ns
1
tHD.SDI, SDI Hold Time
8
ns
1
ns
1
ns
1
ns
1
tVD.SDO, SDO Valid Time
Cload = 20 pF
tHD.SDO, SDO Hold Time
Cload = 20 pF
21.5
3.5
tDIS.SDO, SDO Output Disable Time
28
Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
CS
70%
30%
tFall
tSU;CS
SCLK
tHIGH
70%
30%
tLOW
tHD;SDI
LSB IN
MSB IN
tVD;SDO
SDO
MSB OUT
70%
30%
Page 16 of 109
tDIS;SDO
tHD;SDO
Figure 2. 4-Wire SPI Bus Timing Diagram
Document Number: DS-000347
Revision: 1.2
tHD;CS
70%
30%
tSU;SDI
SDI
tRise
1/fCLK
LSB OUT
ICM-42688-P
SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
3.6
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
24
MHz
1
SPI TIMING
Default
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
17
ns
1
tHIGH, SCLK High Period
17
ns
1
tSU.CS, CS Setup Time
39
ns
1
tHD.CS, CS Hold Time
5
ns
1
tSU.SDIO, SDIO Input Setup Time
13
ns
1
tHD.SDIO, SDIO Input Hold Time
8
ns
1
ns
1
ns
1
ns
1
tVD.SDIO, SDIO Output Valid Time
Cload = 20 pF
tHD.SDIO, SDIO Output Hold Time
Cload = 20 pF
18.5
3.5
28
tDIS.SDIO, SDIO Output Disable Time
Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation)
Notes:
1.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
CS
70%
30%
tFall
tSU;CS
SCLK
tHIGH
SDIO
O
70%
30%
tLOW
tHD;SDIO
LSB IN
MSB IN
tVD;SDIO
MSB OUT
70%
30%
Page 17 of 109
tDIS;SDIO
tHD;SDIO
Figure 3. 3-Wire SPI Bus Timing Diagram
Document Number: DS-000347
Revision: 1.2
tHD;CS
70%
30%
tSU;SDIO
I
tRise
1/fCLK
LSB OUT
ICM-42688-P
3.7
ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
Parameter
Rating
Supply Voltage, VDD
-0.5 V to +4 V
Supply Voltage, VDDIO
-0.5 V to +4 V
Input Voltage Level (FSYNC, SCL, SDA)
-0.5 V to VDDIO + 0.5 V
Acceleration (Any Axis, unpowered)
20,000g for 0.2 ms
Operating Temperature Range
-40°C to +85°C
Storage Temperature Range
-40°C to +125°C
2 kV (HBM);
Electrostatic Discharge (ESD) Protection
500 V (CDM)
JEDEC Class II (2),125°C
Latch-up
±100 mA
Table 8. Absolute Maximum Ratings
Page 18 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
4 APPLICATIONS INFORMATION
4.1
PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Number
Pin Name
1
AP_SDO / AP_AD0
2
RESV
Pin Description
AP_SDO: AP SPI serial data output (4-wire mode);
AP_AD0: AP I3CSM / I2C slave address LSB
No Connect or Connect to GND
3
RESV
No Connect or Connect to GND
4
INT1 / INT
5
VDDIO
INT1: Interrupt 1 (Note: INT1 can be push-pull or open drain)
INT: All interrupts mapped to pin 4
IO power supply voltage
6
GND
Power supply ground
7
RESV
Connect to GND
8
VDD
9
INT2 / FSYNC / CLKIN
10
RESV
Power supply voltage
INT2: Interrupt 2 (Note: INT2 can be push-pull or open drain)
FSYNC: Frame sync input; Connect to GND if FSYNC not used
CLKIN: External clock input
No Connect or Connect to GND
11
RESV
12
AP_CS
13
AP_SCL / AP_SCLK
No Connect or Connect to GND
AP SPI Chip select (AP SPI interface); Connect to VDDIO if using AP I3CSM / I2C
interface
AP_SCL: AP I3CSM / I2C serial clock; AP_SCLK: AP SPI serial clock
14
AP_SDA / AP_SDIO /
AP_SDI
AP_SDA: AP I3CSM / I2C serial data; AP_SDIO: AP SPI serial data I/O (3-wire
mode); AP_SDI: AP SPI serial data input (4-wire mode)
AP_SDA / AP_SDIO / AP_SDI
AP_SCL / AP_SCLK
AP_CS
14
13
12
Table 9. Signal Descriptions
AP_SDO / AP_AD0
1
RESV
2
RESV
3
9
INT2 / FSYNC / CLKIN
INT1 / INT
4
8
VDD
11
RESV
10
RESV
+Z
7
6
5
ICM-42688-P
RESV
GND
VDDIO
+Y
Figure 4. Pin Out Diagram for ICM-42688-P 2.5x3.0x0.91 mm LGA
Page 19 of 109
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Revision: 1.2
+X
ICM-42688-P
4.2
TYPICAL OPERATING CIRCUIT
RESV
14
AP_SCL
AP_SDA
AP_AD0
13
VDDIO
12
1
2
11
RESV
10
RESV
ICM-42688-P
RESV
INT1 / INT
3
9
4
8
INT2 / FSYNC / CLKIN
– 3.6VDC
5
6
VDD
7
RESV
GND
VDDIO
C1, 0.1 mF
C2, 2.2 mF
– 3.6VDC
C3, 10 nF
Figure 5. ICM-42688-P Application Schematic (I3CSM / I2C Interface to Host)
Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
RESV
14
AP_SCLK
AP_SDIO /
AP_SDI
AP_SDO
AP_CS
13
12
1
2
11
RESV
10
RESV
ICM-42688-P
RESV
INT1 / INT
3
9
4
8
INT2 / FSYNC / CLKIN
– 3.6VDC
5
6
VDD
7
RESV
GND
VDDIO
C1, 0.1 mF
C2, 2.2 mF
– 3.6VDC
C3, 10 nF
Figure 6. ICM-42688-P Application Schematic (SPI Interface to Host)
Page 20 of 109
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Revision: 1.2
ICM-42688-P
4.3
BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component
Label
Specification
VDD Bypass Capacitors
C1
C2
X7R, 0.1µF ±10%
X7R, 2.2µF ±10%
1
1
VDDIO Bypass Capacitor
C3
X7R, 10nF ±10%
1
Table 10. Bill of Materials
Page 21 of 109
Document Number: DS-000347
Revision: 1.2
Quantity
ICM-42688-P
4.4
SYSTEM BLOCK DIAGRAM
Figure 7. ICM-42688-P System Block Diagram
Note: The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options.
4.5
OVERVIEW
The ICM-42688-P is comprised of the following key blocks and functions:
• Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
o 20-bits data format support in FIFO for high-data resolution (see section 6 for details)
• Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
o 20-bits data format support in FIFO for high-data resolution (see section 6 for details)
SM 2
• I3C , I C and SPI serial communications interfaces
• Self-Test
• Clocking
• Sensor Data Registers
• FIFO
• Interrupts
• Digital-Output Temperature Sensor
• Bias and LDOs
• Charge Pump
• Standard Power Modes
4.6
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-42688-P includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes. When the
gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The
resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is
digitized using on-chip Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be
digitally programmed to ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees per second (dps).
4.7
THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-42688-P includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of a proof mass
in the MEMS structure, and capacitive sensors detect the displacement. The ICM-42688-P architecture reduces the accelerometers’
susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on
the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of
supply voltage. The full-scale range of the digital output can be adjusted to ±2g, ±4g, ±8g and ±16g.
4.8
I3CSM, I2C AND SPI HOST INTERFACE
The ICM-42688-P communicates to the application processor using an I3CSM, I2C, or SPI serial interface. The ICM-42688-P always acts
as a slave when communicating to the application processor.
4.9
SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers.
Page 22 of 109
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Revision: 1.2
ICM-42688-P
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
Self-test response = Sensor output with self-test enabled – Sensor output with self-test disabled
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed selftest. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
CLOCKING
4.10
The ICM-42688-P has a flexible clocking scheme, allowing external or internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers.
The CLKIN pin on ICM-42688-P provides the ability to input an external clock. A highly accurate external clock may be used rather
than the internal clocks sources, if greater clock accuracy is desired. External clock input supports highly accurate clock input from
31kHz to 50kHz, resulting in improvement of the following:
a)
ODR uncertainty due to process, temperature, operating mode (PLL vs. RCOSC), and design limitations. This uncertainty can
be as high as ±8% in RCOSC mode and ±1% in PLL mode. The CLKIN, assuming a 50ppm or better 32.768kHz source, will
improve the ODR accuracy from ±80,000ppm to ±50ppm in RCOSC mode, or from ±10,000ppm to ±50ppm in PLL mode.
b) System level sensitivity error. Any clock uncertainty directly impacts gyroscope sensitivity at the system level.
Sophisticated systems can estimate ODR inaccuracy to some extent, but not to the extent improved by using CLKIN.
c) System-level clock/sensor synchronization. When using CLKIN, the accelerometer and gyroscope are on the same clock as
the host. There is no need to continually re-synchronize the sensor data as the sensor sample points and period are known
to be in exact alignment with the common system clock.
d) CLKIN helps EIS (Electronic Image Stabilization) performance by providing:
o Very accurate gyroscope sample points for use during integration to find true angular displacement.
o Automatic time alignment between the motion sensor and the host and potentially the camera system.
e) Other applications that benefit from CLKIN include navigation, gaming, robotics.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
For internal sources, the only setting supporting specified performance in all modes is option b). It is recommended that option b)
be used when using internal clock source.
4.11
SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
4.12
INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the interrupt pins
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be
read from the Interrupt Status register.
Page 23 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
4.13
DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-42688-P die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
Temperature sensor register data TEMP_DATA is updated with new data at max(Accelerometer ODR, Gyroscope ODR).
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
4.14
BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-42688-P.
4.15
CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.16
STANDARD POWER MODES
The following table lists the user-accessible power modes for ICM-42688-P.
Mode
1
2
3
4
5
6
Name
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode
Gyro
Off
Drive On
Off
Off
On
On
Table 11. Standard Power Modes for ICM-42688-P
Page 24 of 109
Document Number: DS-000347
Revision: 1.2
Accel
Off
Off
Duty-Cycled
On
Off
On
ICM-42688-P
5 SIGNAL PATH
The following figure shows a block diagram of the signal path for ICM-42688-P.
Gyro Only
ADC
Decimation
Filter
(32kHz)
Notch Filter
0
1
Anti-Alias
Filter (AAF)
0
1
User
Programmable
Offset
UI Filter Block
(order, BW, ODR)
Sensor
Registers
UI Interface
FSR Selection
GYRO_NF_DIS
AAF_DIS
Figure 8. ICM-42688-P Signal Path
The signal path starts with ADCs for the gyroscope and accelerometer. Other components of the signal path are described below in
further detail.
5.1
SUMMARY OF PARAMETERS USED TO CONFIGURE THE SIGNAL PATH
The following table shows the parameters that can control the signal path.
Parameter Name
Description
GYRO_AAF_DIS
GYRO_AAF_DELT
GYRO_AAF_DELTSQR
GYRO_AAF_BITSHIFT
ACCEL_AAF_DIS
ACCEL_AAF_DEL
ACCEL_AAF_DELTSQR
ACCEL_AAF_BITSHIFT
GYRO_NF_DIS
Disables the Gyroscope Anti Alias Filter (AAF)
Three parameters required to program the gyroscope AAF. This is a 2 nd order filter with
programmable low pass filter. This is a user programmable filter which can be used to select
the desired BW. This filter allows trading off RMS noise vs. latency for a given ODR.
Disables the Accelerometer Anti Alias Filter
Three parameters required to program the accelerometer AAF. This is a 2 nd order filter with
programmable low pass filter. This is a user programmable filter which can be used to select
the desired BW. This filter allows trading off RMS noise vs. latency for a given ODR.
Disables the gyro Notch Filter
Factory trimmed parameters, designed to position a Notch at or near the sense peak
frequency of Gyro. This allows the user to suppress only sense peak contribution to noise,
while still maintaining a low latency high BW/ODR interface from the Sensor. This filter is
available only in Gyro, and the parameters for X, Y, and Z are chosen independently.
Factory trimmed parameter to cancel noise created by sense peak from Gyro. This parameter
is common to all three axes
GYRO_X/Y/Z_NF_COSWZ
GYRO_X/Y/Z_NF_COSWZ_SEL
GYRO_NF_BW_SEL
5.2
NOTCH FILTER
The Notch Filter is supported only for the gyroscope signal path. The following steps can be used to program the notch filter. Note
that the notch filter is specific to each axis in the gyroscope, so the X, Y and Z axis can be programmed independently.
Frequency of Notch Filter (each axis)
To operate the Notch filter, two parameters NF_COSWZ, and NF_COSWZ_SEL must be programmed for each gyroscope axis.
Parameters NF_COSWZ are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ (register bank 1, register 0x0Fh & register
0x12h), GYRO_Y_NF_COSWZ (register bank 1, register 0x10h & register 0x12h), GYRO_Z_NF_COSWZ (register bank 1, register 0x11h
& register 0x12h). Note that the parameters have 9-bit values across two different registers.
Page 25 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
Parameters NF_COSWZ_SEL are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ_SEL (register bank 1, register 0x12h,
bit 3), GYRO_Y_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 4), GYRO_Z_NF_COSWZ_SEL (register bank 1, register 0x12h, bit
5).
Each value must be calculated using the steps described below, and programmed into the corresponding register locations
mentioned above.
fdesired is the desired frequency of the Notch Filter in kHz. The lower bound for fdesired is 1kHz, and the upper bound is 3kHz.
Operating the notch filter outside this range is not supported.
Step1: COSWZ = cos(2*pi*fdesired/32)
Step2:
If abs(COSWZ)≤0.875
NF_COSWZ = round[COSWZ*256]
NF_COSWZ_SEL = 0
else
NF_COSWZ_SEL = 1
if COSWZ > 0.875
NF_COSWZ = round [8*(1-COSWZ)*256]
else if COSWZ < -0.875
NF_COSWZ = round [-8*(1+COSWZ)*256]
end
End
Bandwidth of Notch Filter (common to all axes)
The notch filter allows the user to control the width of the notch from eight possible values using a 3-bit parameter
GYRO_NF_BW_SEL in register bank 1, register 0x13h, bits 6:4. This parameter is common to all three axes.
GYRO_NF_BW_SEL
Notch Filter Bandwidth (Hz)
0
1449
1
680
2
329
3
162
4
80
5
40
6
20
7
10
The notch filter can be selected or bypassed by using the parameter GYRO_NF_DIS in register bank 1, register 0x0Bh, bit 0 as shown
below.
GYRO_NF_DIS
Function
0
Enable notch filter
1
Disable notch filter
Page 26 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
5.3
ANTI-ALIAS FILTER
Anti-alias filters for gyroscope and accelerometer can be independently programmed to have bandwidths ranging from 42 Hz to
3979 Hz. To program the anti-alias filter for a required bandwidth, use the table below to map the bandwidth to register values as
shown:
a.
b.
c.
d.
e.
f.
Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows programming the
bandwidth for accelerometer anti-alias filter
Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0, ACCEL_AAF_DELTSQR: Square of the
delt value for accelerometer
Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometer used in hardware
implementation
Register bank 1, register 0x0Ch, bits 5:0, GYRO_AAF_DELT: Code from 1 to 63 that allows programming the
bandwidth for gyroscope anti-alias filter
Register bank 1, register 0x0Dh, bits 7:0 and Bank 1, register 0x0Eh, bits 3:0, GYRO_AAF_DELTSQR: Square of the
delt value for gyroscope
Register bank 1, register 0x0Eh, bits 7:4, GYRO_AAF_BITSHIFT: Bitshift value for gyroscope used in hardware
implementation
3dB Bandwidth (Hz)
42
84
126
170
213
258
303
348
394
441
488
536
585
634
684
734
785
837
890
943
997
1051
1107
1163
1220
1277
1336
ACCEL_AAF_DELT; ACCEL_AAF_DELTSQR; ACCEL_AAF_BITSHIFT;
GYRO_AAF_DELT GYRO_AAF_DELTSQR GYRO_AAF_BITSHIFT
1
1
15
2
4
13
3
9
12
4
16
11
5
25
10
6
36
10
7
49
9
8
64
9
9
81
9
10
100
8
11
122
8
12
144
8
13
170
8
14
196
7
15
224
7
16
256
7
17
288
7
18
324
7
19
360
6
20
400
6
21
440
6
22
488
6
23
528
6
24
576
6
25
624
6
26
680
6
27
736
5
Page 27 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1395
1454
1515
1577
1639
1702
1766
1830
1896
1962
2029
2097
2166
2235
2306
2377
2449
2522
2596
2671
2746
2823
2900
2978
3057
3137
3217
3299
3381
3464
3548
3633
3718
3805
3892
3979
784
848
896
960
1024
1088
1152
1232
1296
1376
1440
1536
1600
1696
1760
1856
1952
2016
2112
2208
2304
2400
2496
2592
2720
2816
2944
3008
3136
3264
3392
3456
3584
3712
3840
3968
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
The anti-alias filter can be selected or bypassed for the gyroscope by using the parameter GYRO_AAF_DIS in register bank 1, register
0x0Bh, bit 1 as shown below.
GYRO_AAF_DIS
Function
0
Enable gyroscope anti-aliasing filter
1
Disable gyroscope anti-aliasing filter
Page 28 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in register bank 2,
register 0x03h, bit 0 as shown below.
5.4
ACCEL_AAF_DIS
Function
0
Enable accelerometer anti-aliasing filter
1
Disable accelerometer anti-aliasing filter
USER PROGRAMMABLE OFFSET
Gyroscope and accelerometer offsets can be programmed by the user by using registers OFFSET_USER0, through OFFSET_USER8, in
bank 0, registers 0x77h through 0x7Fh (bank 4) as shown below.
Register Address
Register Name
Bits
0x77h
OFFSET_USER0
7:0
0x78h
OFFSET_USER1
3:0
7:4
0x79h
OFFSET_USER2
7:0
0x7Ah
OFFSET_USER3
7:0
0x7Bh
OFFSET_USER4
3:0
7:4
0x7Ch
OFFSET_USER5
7:0
0x7Dh
OFFSET_USER6
7:0
0x7Eh
OFFSET_USER7
3:0
7:4
0x7Fh
5.5
OFFSET_USER8
7:0
Function
Lower bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Lower bits of Y-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Lower bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of Z-gyro offset programmed by user.
Max value is ±64 dps, resolution is 1/32 dps.
Upper bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of X-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Upper bits of Y-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Upper bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
Lower bits of Z-accel offset programmed by user.
Max value is ±1 g, resolution is 0.5 g.
UI FILTER BLOCK
The UI filter block can be programmed to select filter order and bandwidth independently for gyroscope and accelerometer.
Gyroscope filter order can be selected by programming the parameter GYRO_UI_FILT_ORD in register bank 0, register 0x51h, bits
3:2, as shown below.
Page 29 of 109
Document Number: DS-000347
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ICM-42688-P
GYRO_UI_FILT_ORD
Filter Order
00
1st order
01
2nd order
10
3rd order
11
Reserved
Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0, register 0x53h,
bits 4:3, as shown below.
ACCEL_UI_FILT_ORD
Filter Order
00
1st order
01
2nd order
10
3rd order
11
Reserved
Gyroscope and accelerometer filter 3dB bandwidth can be selected by programming the parameter GYRO_UI_FILT_BW in register
bank 0, register 0x52h, bits 3:0, and the parameter ACCEL_UI_FILT_BW in register bank 0, register 0x52h, bits 7:4, as shown below.
The values shown in bold correspond to low noise and the values shown in italics correspond to low latency. User can select the
appropriate setting based on the application requirements for power and latency. Corresponding Noise Bandwidth (NBW) and
Group Delay values are also shown.
1st Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
1
2
3
4
5
6
15
7
8
9
10
11
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
0
1
2
3
498.3
249.1
99.6
49.8
24.9
12.5
12.5
227.2
113.6
90.9
90.9
90.9
90.9
90.9
188.9
94.4
75.5
75.5
75.5
75.5
75.5
111.0
55.5
44.4
44.4
44.4
44.4
44.4
4
5
8400.0
4194.1
2096.3
1048.1
524.0
92.4 59.6
46.2 29.8
37.0 23.8
37.0 23.8
37.0 23.8
37.0 23.8
37.0 23.8
6
7
48.8 23.9
24.4 11.9
19.5 9.6
19.5 9.6
19.5 9.6
19.5 9.6
19.5 9.6
14
15
262.0
131.0
104.8
104.8
104.8
104.8
104.8
2096.3
1048.1
419.2
209.6
104.8
52.4
52.4
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
1
2
3
ODR(Hz)
32000
16000
8000
0
1
2
3
Page 30 of 109
Document Number: DS-000347
Revision: 1.2
4
5
8831.7
4410.6
2204.6
6
7
14
15
ICM-42688-P
4
5
6
15
7
8
9
10
11
4000
2000
1000
500
200
100
50
25
12.5
551.1
280.5
112.2
56.1
28.1
14.1
14.1
230.8 196.3
115.4 98.2
92.4 78.5
92.4
78.5
92.4
78.5
92.4
78.5
92.4
78.5
126.5
63.3
50.6
50.6
50.6
50.6
50.6
1102.2
551.1
108.9 75.8
54.5 37.9
43.6 30.3
43.6 30.3
43.6 30.3
43.6 30.3
43.6 30.3
64.1
32.1
25.7
25.7
25.7
25.7
25.7
34.1
17.1
13.7
13.7
13.7
13.7
13.7
275.6
137.8
110.3
110.3
110.3
110.3
110.3
2204.6
1102.2
440.9
220.5
110.3
55.2
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
1
2
3
4
5
6
15
7
8
9
10
11
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
0
1
2
3
4
0.6
1.1
2.7
5.3
10.5
21.0
21.0
1.8
3.6
4.4
4.4
4.4
4.4
4.4
2.0
4.0
5.0
5.0
5.0
5.0
5.0
2.8
5.5
6.8
6.8
6.8
6.8
6.8
3.1
6.1
7.6
7.6
7.6
7.6
7.6
5
0.1
0.1
0.2
0.4
0.8
4.1
8.1
10.2
10.2
10.2
10.2
10.2
6
7
14
15
4.7
9.3
11.7
11.7
11.7
11.7
11.7
8.1
16.2
20.3
20.3
20.3
20.3
20.3
1.5
3.0
3.8
3.8
3.8
3.8
3.8
0.2
0.4
1.0
1.9
3.8
7.5
7.5
2nd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
1
2
3
4
5
6
15
7
8
9
10
11
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
0
493.3
246.7
98.7
49.3
24.7
12.3
12.3
1
2
230.7 191.6
115.3 95.8
92.3 76.6
92.3
76.6
92.3
76.6
92.3
76.6
92.3
76.6
3
117.5
58.8
47.0
47.0
47.0
47.0
47.0
Page 31 of 109
Document Number: DS-000347
Revision: 1.2
4
5
8400.0
4194.1
2096.3
1048.1
524.0
97.1 59.6
48.5 29.8
38.8 23.8
38.8 23.8
38.8 23.8
38.8 23.8
38.8 23.8
6
7
48.0 21.3
24.0 10.6
19.2 8.5
19.2 8.5
19.2 8.5
19.2 8.5
19.2 8.5
14
15
262.0
131.0
104.8
104.8
104.8
104.8
104.8
2096.3
1048.1
419.2
209.6
104.8
52.4
52.4
ICM-42688-P
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
1
2
3
4
5
6
15
7
8
9
10
11
ODR(Hz)
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
0
551.1
259.6
103.9
52.0
26.0
13.0
13.0
1
2
3
223.7 189.9
111.9 95.0
89.5 76.0
89.5
76.0
89.5
76.0
89.5
76.0
89.5
76.0
4
122.7
61.4
49.1
49.1
49.1
49.1
49.1
5
8831.7
4410.6
2204.6
1102.2
551.1
102.8 64.7
51.4 32.4
41.2 25.9
41.2 25.9
41.2 25.9
41.2 25.9
41.2 25.9
6
7
52.5 23.7
26.3 11.9
21.0 9.5
21.0 9.5
21.0 9.5
21.0 9.5
21.0 9.5
14
15
275.6
137.8
110.3
110.3
110.3
110.3
110.3
2204.6
1102.2
440.9
220.5
110.3
55.2
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
1
2
3
4
5
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
6
15
7
8
9
10
11
0
1
2
3
4
5
6
7
14
15
1.5
3.0
3.8
3.8
3.8
3.8
3.8
0.2
0.4
1.0
1.9
3.8
7.5
7.5
0.1
0.1
0.2
0.4
0.8
0.7
1.3
3.3
6.5
12.9
25.7
25.7
2.1
4.1
5.1
5.1
5.1
5.1
5.1
2.4
4.7
5.8
5.8
5.8
5.8
5.8
3.2
6.4
8.0
8.0
8.0
8.0
8.0
3.7
7.3
9.1
9.1
9.1
9.1
9.1
5.2
10.4
12.9
12.9
12.9
12.9
12.9
6.1
12.2
15.3
15.3
15.3
15.3
15.3
12.0
24.0
30.0
30.0
30.0
30.0
30.0
3rd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay
3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_ODR
ODR(Hz)
1
2
3
4
5
32000
16000
8000
4000
2000
1000
500
200
6
15
7
0
492.9
246.4
98.6
1
234.7
117.4
93.9
2
195.8
97.9
78.3
GYRO/ACCEL_UI_FILT_BW
3
4
5
6
8400.0
4194.1
2096.3
1048.1
524.0
118.9 97.9 60.8 46.8 25.2
59.5 48.9 30.4 23.4 12.6
47.6 39.2 24.3 18.7 10.1
Page 32 of 109
Document Number: DS-000347
Revision: 1.2
7
14
15
262.0
131.0
104.8
2096.3
1048.1
419.2
ICM-42688-P
8
9
10
11
100
50
25
12.5
49.3
24.6
12.3
12.3
93.9
93.9
93.9
93.9
78.3
78.3
78.3
78.3
47.6
47.6
47.6
47.6
39.2
39.2
39.2
39.2
24.3
24.3
24.3
24.3
18.7
18.7
18.7
18.7
10.1
10.1
10.1
10.1
104.8
104.8
104.8
104.8
209.6
104.8
52.4
52.4
NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
1
2
3
4
5
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
6
15
7
8
9
10
11
0
1
551.1
252.0
100.8
50.4
25.2
12.6
12.6
2
3
221.3 188.5
110.7 94.3
88.6 75.4
88.6
75.4
88.6
75.4
88.6
75.4
88.6
75.4
4
120.1
60.1
48.1
48.1
48.1
48.1
48.1
5
8831.7
4410.6
2204.6
1102.2
551.1
100.0 62.9
50.0 31.5
40.0 25.2
40.0 25.2
40.0 25.2
40.0 25.2
40.0 25.2
6
7
14
15
48.6
24.3
19.5
19.5
19.5
19.5
19.5
26.4
13.2
10.6
10.6
10.6
10.6
10.6
275.6
137.8
110.3
110.3
110.3
110.3
110.3
2204.6
1102.2
440.9
220.5
110.3
55.2
55.2
Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter)
GYRO/ACCEL_UI_FILT_BW
GYRO/ACCEL_ODR
ODR(Hz)
1
2
3
4
5
32000
16000
8000
4000
2000
1000
500
200
100
50
25
12.5
6
15
7
8
9
10
11
5.6
0
1
2
3
4
5
6
7
14
15
1.5
3.0
3.8
3.8
3.8
3.8
3.8
0.2
0.4
1.0
1.9
3.8
7.5
7.5
0.1
0.1
0.2
0.4
0.8
0.8
1.6
4.0
8.0
15.9
31.8
31.8
2.3
4.6
5.8
5.8
5.8
5.8
5.8
2.7
5.4
6.8
6.8
6.8
6.8
6.8
4.0
7.9
9.8
9.8
9.8
9.8
9.8
4.6
9.2
11.4
11.4
11.4
11.4
11.4
6.6
13.2
16.5
16.5
16.5
16.5
16.5
8.2
16.3
20.4
20.4
20.4
20.4
20.4
14.1
28.1
35.2
35.2
35.2
35.2
35.2
UI PATH ODR AND FSR SELECTION
Gyroscope ODR can be selected by programming the parameter GYRO_ODR in register bank 0, register 0x4Fh, bits 3:0 as shown
below.
GYRO_ODR
Gyroscope ODR Value
0000
Reserved
0001
32kHz
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ICM-42688-P
0010
16kHz
0011
8kHz
0100
4kHz
0101
2kHz
0110
1kHz (default)
0111
200Hz
1000
100Hz
1001
50Hz
1010
25Hz
1011
12.5Hz
1100
Reserved
1101
Reserved
1110
Reserved
1111
500Hz
Gyroscope FSR can be selected by programming the parameter GYRO_UI_FS_SEL in register bank 0, register 0x4Fh, bits 7:5 as shown
below.
GYRO_UI_FS_SEL
Gyroscope FSR Value
000
2000dps
001
1000dps
010
500dps
011
250dps
100
125dps
101
62.5dps
110
31.25dps
111
15.625dps
Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h, bits 3:0 as shown
below.
ACCEL_ODR
Accelerometer ODR Value
0000
Reserved
0001
32kHz (LN mode)
0010
16kHz (LN mode)
0011
8kHz (LN mode)
0100
4kHz (LN mode)
0101
2kHz (LN mode)
0110
1kHz (LN mode) (default)
0111
200Hz (LP or LN mode)
1000
100Hz (LP or LN mode)
1001
50Hz (LP or LN mode)
1010
25Hz (LP or LN mode)
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ICM-42688-P
1011
12.5Hz (LP or LN mode)
1100
6.25Hz (LP mode)
1101
3.125Hz (LP mode)
1110
1.5625Hz (LP mode)
1111
500Hz (LP or LN mode)
Accelerometer FSR can be selected by programming the parameter ACCEL_UI_FS_SEL in register bank 0, register 0x50h, bits 7:5 as
shown below.
ACCEL_UI_FS_SEL
Accelerometer FSR Value
000
16g
001
8g
010
4g
011
2g
100
Reserved
101
Reserved
110
Reserved
111
Reserved
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ICM-42688-P
6 FIFO
The ICM-42688-P contains a 2K byte FIFO register that is accessible via the serial interface. The FIFO configuration register
determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer data, temperature readings,
and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO.
6.1
PACKET STRUCTURE
The following figure shows the FIFO packet structures supported in ICM-42688-P. Base data format for gyroscope and
accelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures. When 20-bits data
format is used, gyroscope data consists of 19-bits of actual data and the LSB is always set to 0, accelerometer data consists of 18-bits
of actual data and the two lowest order bits are always set to 0. When 20-bits data format is used, the only FSR settings that are
operational are ±2000dps for gyroscope and ±16g for accelerometer, even if the FSR selection register settings are configured for
other FSR values. The corresponding sensitivity scale factor values are 131 LSB/dps for gyroscope and 8192 LSB/g for
accelerometer.
Header
(1 byte)
Header
(1 byte)
Header
(1 byte)
Header
(1 byte)
Accelerometer Data
(6 bytes)
Gyroscope Data
(6 bytes)
Accelerometer Data
(6 bytes)
Accelerometer Data
(6 bytes)
Temperature Data
(1 byte)
Temperature Data
(1 byte)
Gyroscope Data
(6 bytes)
Gyroscope Data
(6 bytes)
Temperature Data
(1 byte)
Temperature Data
(2 bytes)
TimeStamp
(2 bytes)
TimeStamp
(2 bytes)
Packet 1
Packet 2
Packet 3
20-bit Extension
(3 bytes)
Packet 4
Figure 9. FIFO Packet Structure
The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures.
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ICM-42688-P
Packet 1: Individual data is packaged in Packet 1 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Content
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Temperature[7:0]
Packet 2: Individual data is packaged in Packet 2 as shown below.
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Content
FIFO Header
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]
Temperature[7:0]
Packet 3: Individual data is packaged in Packet 3 as shown below.
Byte
Content
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
FIFO Header
Accel X [15:8]
Accel X [7:0]
Accel Y [15:8]
Accel Y [7:0]
Accel Z [15:8]
Accel Z [7:0]
Gyro X [15:8]
Gyro X [7:0]
Gyro Y [15:8]
Gyro Y [7:0]
Gyro Z [15:8]
Gyro Z [7:0]
Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]
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ICM-42688-P
Packet 4: Individual data is packaged in Packet 4 as shown below.
6.2
Byte
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
Content
FIFO Header
Accel X [19:12]
Accel X [11:4]
Accel Y [19:12]
Accel Y [11:4]
Accel Z [19:12]
Accel Z [11:4]
Gyro X [19:12]
Gyro X [11:4]
Gyro Y [19:12]
Gyro Y [11:4]
Gyro Z [19:12]
Gyro Z [11:4]
Temperature[15:8]
Temperature[7:0]
TimeStamp[15:8]
TimeStamp[7:0]
Accel X [3:0]
Gyro X [3:0]
Accel Y [3:0]
Gyro Y [3:0]
0x13
Accel Z [3:0]
Gyro Z [3:0]
FIFO HEADER
The following table shows the structure of the 1byte FIFO header.
Bit Field
Item
Description
1: FIFO is empty
7
HEADER_MSG
0: Packet contains sensor data
1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN
6
HEADER_ACCEL
must be 1
0: Packet does not contain accel sample
1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must
5
HEADER_GYRO
be 1
0: Packet does not contain gyro sample
1 : Packet has a new and valid sample of extended 20-bit data for gyro and/or accel
4
HEADER_20
0 : Packet does not contain a new and valid extended 20-bit data
00: Packet does not contain timestamp or FSYNC time data
01: Reserved
3:2
HEADER_TIMESTAMP_FSYNC 10: Packet contains ODR Timestamp
11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC
(only if FIFO_TMST_FSYNC_EN is 1)
1: The ODR for accel is different for this accel data packet compared to the previous
1
HEADER_ODR_ACCEL
accel packet
0: The ODR for accel is the same as the previous packet with accel
1: The ODR for gyro is different for this gyro data packet compared to the previous
0
HEADER_ODR_GYRO
gyro packet
0: The ODR for gyro is the same as the previous packet with gyro
Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set.
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ICM-42688-P
6.3
MAXIMUM FIFO STORAGE
The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As shown in the figure
below, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected (see section 6.1) is reserved to
prevent reading a packet during write operation. Additionally, a read cache 2 packets wide is available.
When there is no serial interface operation, the read cache is not available for storing packets, being fed by the serial interface clock.
When serial interface operation happens, depending on the operation length and the packet size chosen, either 1 or 2 of the packet
entries in read cache may become available for storing packets. In that case the total storage available is up to the maximum
number of packets that can be accommodated in 2048 (2040 in case of 20 bytes packets) bytes + 1 packet size, depending on the
packet size used.
Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest size of 2080 bytes.
FIFO 2048 Bytes
2 Packet Size
Read Cache
2048 Bytes – 1 packet size
1 Packet Size
Reserved to prevent reading a
packet during write operation
Figure 10. Maximum FIFO Storage
6.4
FIFO CONFIGURATION REGISTERS
The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values of these bits may change
while the FIFO is being filled without corruption of the FIFO.
BIT
NAME
4
FIFO_HIRES_EN
3
FIFO_TMST_FSYNC_EN
1
FIFO_GYRO_EN
0
FIFO_ACCEL_EN
FUNCTION
0: Default setting; Sensor data have regular resolution
1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes
packet with priority on other setting below
0: FIFO will only contain ODR timestamp information
1: FIFO can also contain FSYNC time and FSYNC flag for one ODR after an
FSYNC event
0: Default setting; Gyroscope data not placed into FIFO
1: Enables gyroscope data packets of 6-bytes to be placed in FIFO
0: Default setting; Accelerometer data not placed into FIFO
1: Enables accelerometer data packets of 6-bytes to be placed in FIFO
Configuration register settings above impact FIFO header and FIFO packet size as follows:
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ICM-42688-P
FIFO_HIRES_EN
FIFO_ACCEL_EN
FIFO_GYRO_EN
1
1
0
0
0
0
0
X
X
1
1
1
0
0
X
X
1
1
0
1
0
FIFO_TMST_
FSYNC_EN
0
1
0
1
X
X
X
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Header
Packet size
8’b_0111_10xx
8’b_0111_11xx
8’b_0110_10xx
8’b_0110_11xx
8’b_0100_00xx
8’b_0010_00xx
No FIFO writes
20 Bytes
20 Bytes
16 Bytes
16 Bytes
8 Bytes
8 Bytes
No FIFO writes
ICM-42688-P
7 PROGRAMMABLE INTERRUPTS
The ICM-42688-P has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate
the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two interrupt outputs. Any
interrupt may be mapped to either interrupt pin as explained in the register section. The following configuration options are
available for the interrupts
•
•
•
INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low
Additionally, ICM-42688-P includes In-band Interrupt (IBI) support for the I3CSM interface.
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ICM-42688-P
8 APEX MOTION FUNCTIONS
The APEX (Advanced Pedometer and Event Detection – neXt gen) features ICM-42688-P consist of:
•
•
•
•
•
•
8.1
Pedometer: Tracks Step count and issues a Step Detect Interrupt
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmable time.
Raise to Wake/Sleep: Gesture detection for wake and sleep events. Interrupt is issued when either of these two events are
detected.
Tap Detection: Issues an interrupt when Tap is detected, along with a register containing the Tap Count.
Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmable threshold. This motion
event can be used to enable chip operation from sleep mode.
Significant Motion Detector (SMD): Detects motion if WoM events are detected during a programmable time window (2s or
4s).
APEX ODR SUPPORT
APEX algorithms are designed to work with the accelerometer, for a variety of ODR settings. However, there is a minimum ODR
required for each algorithm. The following table shows the relationship between the available accelerometer ODRs and the
operation of the APEX algorithms. In order to allow more flexible operation where we can control the ODR of the APEX algorithms
independent of the accelerometer ODR, we allow for an additional selection determined by the field DMP_ODR. The tables below
shows how DMP_ODR should be configured in relation to the accelerometer ODR and the expected performance.
Accel ODR
DMP_ODR
Tap Detection
Pedometer
Tilt Detection
Raise to Wake/Sleep
< 25Hz
X
Disabled
Disabled
Disabled
Disabled
≥ 25Hz
0 (25Hz)
Disabled
Low Power
Low Power
Enabled
≥ 50Hz
2 (50Hz)
Disabled
Normal
Normal
Enabled
Accel ODR
Tap Detection
200Hz
Low Power
500Hz
Normal
1kHz
High Performance
> 1kHz
Disabled
If the accelerometer ODR is set below the minimum DMP ODR (25 Hz), the APEX features cannot be enabled.
When the accelerometer ODR needs to be set differently from the DMP ODR, only the integer multiple of DMP ODR for
accelerometer sensor ODR is suitable to use with DMP. For example, when the accelerometer ODR is set as 200 Hz, the APEX
features can be enabled with choices of 25 Hz, or 50 Hz, depending on the DMP_ODR register setting.
DMP ODR should not be changed on the fly. The following sequence should be followed for changing the DMP ODR:
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ICM-42688-P
1.
2.
3.
4.
5.
Disable Pedometer, and Tilt Detection if they are enabled
Change DMP ODR
Set DMP_INIT_EN for one cycle (Register 0x4Bh in Bank 0)
Unset DMP_INIT_EN (Register 0x4Bh in Bank 0)
Enable APEX features of interest
DMP POWER SAVE MODE
8.2
DMP Power Save Mode can be enabled or disabled by DMP_POWER_SAVE (Register 0x56h in Bank 0). When the DMP Power Save
Mode is enabled, APEX features are enabled only when WOM is detected. WOM must be explicitly enabled for the DMP to work in
this mode. When WOM is not detected the APEX features are on pause. If the user does not want to use DMP Power Save Mode
they may set DMP_POWER_SAVE = 0, and use APEX functions without WOM detection.
PEDOMETER PROGRAMMING
8.3
•
Pedometer configuration parameters
1. LOW_ENERGY_AMP_TH_SEL (Register 0x40h in Bank 4)
2. PED_AMP_TH_SEL (Register 0x41h in Bank 4)
3. PED_STEP_CNT_TH_SEL (Register 0x41h in Bank 4)
4. PED_HI_EN_TH_SEL (Register 0x42h in Bank 4)
5. PED_SB_TIMER_TH_SEL (Register 0x42h in Bank 4)
6. PED_STEP_DET_TH_SEL (Register 0x42h in Bank 4)
7. SENSITIVITY_MODE (Register 0x48h in Bank 4)
8. There are 2 ODR and 2 sensitivity modes
Accel ODR (DMP_ODR)
25 Hz (0)
50 Hz (2)
normal
low power
high performance
slow walk
low power and slow walk
slow walk
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR to 50 Hz (Register 0x50h in Bank 0)
2. Set accelerometer to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Eh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR = 50 Hz and turn on Pedometer feature (Register 0x56h in Bank 0)
4. Wait 1 millisecond
•
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set LOW_ENERGY_AMP_TH_SEL to 10 (Register 0x40h in Bank 4)
4. Set PED_AMP_TH_SEL to 8 (Register 0x41h in Bank 4)
5. Set PED_STEP_CNT_TH_SEL to 5 (Register 0x41h in Bank 4)
6. Set PED_HI_EN_TH_SEL to 1 (Register 0x42h in Bank 4)
7. Set PED_SB_TIMER_TH_SEL to 4 (Register 0x42h in Bank 4)
8. Set PED_STEP_DET_TH_SEL to 2 (Register 0x42h in Bank 4)
9. Set SENSITIVITY_MODE to 0 (Register 0x48h in Bank 4)
10. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
11. Enable STEP detection, source for INT1 by setting bit 5 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or
if INT2 is selected for STEP detection, enable STEP detection source by setting bit 5 in register INT_SOURCE7
(Register 0x4Eh in Bank 4) to 1.
12. Wait 50 milliseconds
13. Turn on Pedometer feature by setting PED_ENABLE to 1 (Register 0x56h in Bank 0)
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ICM-42688-P
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for STEP_DET_INT
2. If the step count is equal to or greater than 65535 (uint16), the STEP_CNT_OVF_INT (Register 0x38h in Bank 0) will
be set to 1. Example:
▪ Take 1 step =>output step count = 65533 (real step count is 65533)
▪ Take 1 step => output step count = 65534 (real step count is 65534)
▪ Take 1 step => output step count = 0 and interrupt is fired (real step count is 65535+0= 65535)
▪ Take 1 step => output step count = 1 (real step count is 65535+1=65536)
3. Read the step count in STEP_CNT (Register 0x31h and 0x32h in Bank 0)
4. Read the step cadence in STEP_CADENCE (Register 0x33h in Bank 0)
5. Read the activity class in ACTIVITY_CLASS (Register 0x34h in Bank 0)
TILT DETECTION PROGRAMMING
8.4
•
Tilt Detection configuration parameters
1. TILT_WAIT_TIME (Register 0x43h in Bank 4)
This parameter configures how long of a delay after tilt is detected before interrupt is triggered
Default is 2 (4 s).
Range is 0 = 0 s, 1 = 2 s, 2 = 4 s, 3 = 6 s
For example, setting TILT_WAIT_TIME = 2 is equivalent to 4 seconds for all ODRs
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz or 10 for 25 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Set DMP ODR (Register 0x56h in Bank 0)
DMP_ODR = 0 for 25 Hz, 2 for 50 Hz
4. Wait 1 millisecond
•
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set TILT_WAIT_TIME (Register 0x43h in Bank 4) if default value does not meet needs
4. Wait 1 millisecond
5. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
6. Enable Tilt Detection, source for INT1 by setting bit 3 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or
if INT2 is selected for Tilt Detection, enable Tilt Detection source by setting bit 3 in register INT_SOURCE7 (Register
0x4Eh in Bank 4) to 1.
7. Wait 50 milliseconds
8. Turn on Tilt Detection feature by setting TILT_ENABLE to 1 (Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TILT_DET_INT
RAISE TO WAKE/SLEEP PROGRAMMING
8.5
•
Raise to Wake/Sleep configuration parameters
1. SLEEP_TIME_OUT (Register 0x43h in Bank 4)
2. MOUNTING_MATRIX (Register 0x44h in Bank 4)
3. SLEEP_GESTURE_DELAY (Register 0x45h in Bank 4)
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 10 for 25 Hz
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2.
3.
4.
Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
Set DMP ODR (Register 0x56h in Bank 0)
DMP_ODR = 0 for 25 Hz, 2 for 50 Hz
Wait 1 millisecond
•
Initialize APEX hardware
1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0)
2. Wait 1 millisecond
3. Set SLEEP_TIME_OUT (Register 0x43h in Bank 4) if default value does not meet needs
4. Wait 1 millisecond
5. Set MOUNTING_MATRIX (Register 0x44h in Bank 4) if default value does not meet needs
6. Wait 1 millisecond
7. Set SLEEP_GESTURE_DELAY (Register 0x45h in Bank 4) if default value does not meet needs
8. Wait 1 millisecond
9. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0)
10. Enable Raise to Wake/Sleep, source for INT1 by setting bit 2,1 in register INT_SOURCE6 (Register 0x4Dh in Bank 4)
to 1. Or if INT2 is selected for Raise to Wake/Sleep, enable Raise to Wake/Sleep source by setting bit 2,1 in register
INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
11. Wait 50 milliseconds
12. Turn on Raise to Wake/Sleep feature by setting R2W_EN to 1 (Register 0x56h in Bank 0)
•
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for WAKE_INT, SLEEP_INT
TAP DETECTION PROGRAMMING
8.6
•
Tap Detection configuration parameters
1. TAP_TMAX (Register 0x47h in Bank 4)
2. TAP_TMIN (Register 0x47h in Bank 4)
3. TAP_TAVG (Register 0x47h in Bank 4)
4. TAP_MIN_JERK_THR (Register 0x46h in Bank 4)
5. TAP_MAX_PEAK_TOL (Register 0x46h in Bank 4)
6. TAP_ENABLE (Register 0x56h in Bank 0)
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 15 for 500 Hz (ODR of 200Hz or 1kHz may also be used)
2. Set power modes and filter configurations as shown below
▪ For ODR up to 500Hz, set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and ACCEL_LP_CLK_SEL = 0, (Register 0x4Dh in Bank 0) for low power mode
Set filter settings as follows: ACCEL_DEC2_M2_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW = 4
(Register 0x52h in Bank 0)
•
For ODR of 1kHz, set Accel to Low Noise mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 1
Set filter settings as follows: ACCEL_UI_FILT_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW =
0 (Register 0x52h in Bank 0)
3.
•
Wait 1 millisecond
Initialize APEX hardware
1. Set TAP_TMAX to 2 (Register 0x47h in Bank 4)
2. Set TAP_TMIN to 3 (Register 0x47h in Bank 4)
3. Set TAP_TAVG to 3 (Register 0x47h in Bank 4)
4. Set TAP_MIN_JERK_THR to 17 (Register 0x46h in Bank 4)
5. Set TAP_MAX_PEAK_TOL to 2 (Register 0x46h in Bank 4)
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6.
7.
8.
9.
•
Wait 1 millisecond
Enable TAP source for INT1 by setting bit 0 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is
selected for TAP, enable TAP source by setting bit 0 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1.
Wait 50 milliseconds
Turn on TAP feature by setting TAP_ENABLE to 1 (Register 0x56h in Bank 0)
Output registers
1. Read interrupt register (Register 0x38h in Bank 0) for TAP_DET_INT
2. Read the tap count in TAP_NUM (Register 0x35h in Bank 0)
3. Read the tap axis in TAP_AXIS (Register 0x35h in Bank 0)
4. Read the polarity of tap pulse in TAP_DIR (Register 0x35h in Bank 0)
WAKE ON MOTION PROGRAMMING
8.7
•
Wake on Motion configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
•
Initialize Sensor in a typical configuration
1. Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
3. Wait 1 millisecond
•
Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1 (Register 0x66h in Bank 0)
to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM sources by setting bits 2:0 in register INT_SOURCE4
(Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on WOM feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 1 (Register 0x56h in
Bank 0)
•
Output registers
1. Read interrupt register (Register 0x7Dh in Bank 0) for WOM_X_INT
2. Read interrupt register (Register 0x7Dh in Bank 0) for WOM_Y_INT
3. Read interrupt register (Register 0x7Dh in Bank 0) for WOM_Z_INT
SIGNIFICANT MOTION DETECTION PROGRAMMING
8.8
•
Significant Motion Detection configuration parameters
1. WOM_X_TH (Register 0x4Ah in Bank 4)
2. WOM_Y_TH (Register 0x4Bh in Bank 4)
3. WOM_Z_TH (Register 0x4Ch in Bank 4)
4. WOM_INT_MODE (Register 0x57h in Bank 0)
5. WOM_MODE (Register 0x57h in Bank 0)
6. SMD_MODE (Register 0x57h in Bank 0)
•
Initialize Sensor in a typical configuration
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1.
2.
3.
Set accelerometer ODR (Register 0x50h in Bank 0)
ACCEL_ODR = 9 for 50 Hz
Set Accel to Low Power mode (Register 0x4Eh in Bank 0)
ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode
Wait 1 millisecond
•
Initialize APEX hardware
1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4)
2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4)
3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4)
4. Wait 1 millisecond
5. Enable SMD source for INT1 by setting bit 3 in register INT_SOURCE1 (Register 0x66h in Bank 0) to 1. Or if INT2 is
selected for SMD, enable SMD source by setting bit 3 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1.
6. Wait 50 milliseconds
7. Turn on SMD feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 3 (Register 0x56h in
Bank 0)
•
Output registers
1. Read interrupt register (Register 0x7Dh in Bank 0) for SMD_INT
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9 DIGITAL INTERFACE
I3CSM, I2C AND SPI SERIAL INTERFACES
9.1
The internal registers and memory of the ICM-42688-P can be accessed using I3CSM at 12.5MHz (data rates up to 12.5Mbps in SDR
mode, 25Mbps in DDR mode), I2C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire mode. Pin assignments for serial
interfaces are described in Section 4.1.
I3CSM INTERFACE
9.2
I3CSM is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3C SM is intended to improve
upon the I2C interface, while preserving backward compatibility.
I3CSM carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides
the higher data rates, simpler pads, and lower power of SPI. I3CSM adds higher throughput for a given frequency, in-band interrupts
(from slave to master), dynamic addressing.
ICM-42688-P supports the following features of I3CSM:
•
•
•
•
•
•
•
•
SDR data rate up to 12.5Mbps
DDR data rate up to 25Mbps
Dynamic address allocation
In-band Interrupt (IBI) support
Support for synchronous timing control
Support for asynchronous timing control mode 0
Error detection (CRC and/or Parity)
Common Command Code (CCC)
The ICM-42688-P always operates as an I3CSM slave device when communicating to the system processor, which thus acts as the
I3CSM master. I3CSM master controls an active pullup resistance on SDA, which it can enable and disable. The pullup resistance may
be a board level resistor controlled by a pin, or it may be internal to the I3CSM master.
9.3
I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bidirectional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-42688-P always operates as a slave device when communicating to the system processor, which thus acts as the master.
SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-42688-P is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic
level on pin AP_AD0. This allows two ICM-42688-Ps to be connected to the same I2C bus. When used in this configuration, the
address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address of the other should be b1101001 (pin
AP_AD0 is logic high).
9.4
I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
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SDA
SCL
S
P
START condition
STOP condition
Figure 11. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 12. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
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SDA
SCL
1–7
8
1–7
9
8
1–7
9
8
9
S
P
START ADDRESS
condition
R/W
ACK
DATA
ACK
DATA
ACK
STOP
condition
Figure 13. Complete I2C Data Transfer
To write the internal ICM-42688-P registers, the master transmits the start condition (S), followed by the I 2C address and the write
bit (0). At the 9th clock cycle (when the clock is high), the ICM-42688-P acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the ICM-42688-P acknowledges the reception of the register address, the master puts the register
data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM42688-P automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
ACK
DATA
ACK
P
ACK
Burst Write Sequence
Master
Slave
S
AD+W
RA
ACK
DATA
ACK
DATA
ACK
P
ACK
To read the internal ICM-42688-P registers, the master sends a start condition, followed by the I 2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the ICM-42688-P, the master transmits a start signal
followed by the slave address and read bit. As a result, the ICM-42688-P sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
ACK
S
AD+R
ACK
NACK
ACK
P
DATA
Burst Read Sequence
Master
Slave
9.5
S
AD+W
RA
ACK
S
ACK
AD+R
ACK
ACK
DATA
NACK
DATA
I2C TERMS
Signal
S
AD
Description
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
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P
ICM-42688-P
W
R
ACK
NACK
RA
DATA
P
Write bit (0)
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock
cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-42688-P internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 12. I2C Terms
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9.6
SPI INTERFACE
The ICM-42688-P supports 3-wire or 4-wire SPI for the host interface. The ICM-42688-P always operates as a Slave device during
standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input (SDI), and the Serial
Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz
5. SPI read operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the SPI Address,
and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates
the Read (1) operation. The following 7 bits contain the Register Address. In cases of multiple-byte Reads, data is two or
more bytes:
SPI Address format
MSB
R/W
A6
A5
A4
A3
A2
A1
LSB
A0
D6
D5
D4
D3
D2
D1
LSB
D0
SPI Data format
MSB
D7
6.
SPI write operations are completed in 16 clock cycles (two bytes). The first byte contains the SPI Address, and the second
byte contains the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Write (0) operation.
The following 7 bits contain the Register Address.
7.
Supports Single or Burst Reads and Single Writes.
SCLK
SDIO
SPI Master
CS1
nCS
SPI Slave 1
CS2
SCLK
SDIO
SPI Slave 2
nCS
Figure 14. Typical SPI Master/Slave Configuration
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10 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) devices packaged in
LGA package.
10.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the
figure.
+Z
+Y
+Z
+Y
+X
+X
Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation
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10.2
PACKAGE DIMENSIONS
14 Lead LGA (2.5x3x0.91) mm NiAu pad finish
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DIMENSIONS IN MILLIMETERS
Total Thickness
Substrate Thickness
Mold Thickness
Body Size
SYMBOLS
A
A1
A2
NOM
0.91
0.105
0.8
MAX
0.97
REF
REF
D
2.5
BSC
E
3
BSC
Lead Width
W
0.2
0.25
0.3
Lead Length
L
e
n
0.425
0.475
0.5
14
0.525
BSC
Lead Pitch
Lead Count
Edge Pin Center to Center
Body Center to Contact Pin
Package Edge Tolerance
Mold Flatness
Coplanarity
D1
1.5
BSC
E1
SD
1
0.25
BSC
BSC
aaa
bbb
ddd
0.1
0.2
0.08
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MIN
0.85
ICM-42688-P
11 PART NUMBER PACKAGE MARKING
The part number package marking for ICM-42688-P devices is summarized below:
Part Number
ICM-42688-P
Part Number Package Marking
I428P
TOP VIEW
Part Number
Lot Traceability Code
I428P
XXXXXX
YYWW
Y Y = Year Code
W W = Work Week
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12 USE NOTES
12.1 ACCELEROMETER MODE TRANSITIONS
When transitioning from accelerometer Low Power (LP) mode to accelerometer Low Noise (LN) mode, if ODR is 6.25Hz or lower,
software should change ODR to a value of 12.5Hz or higher, because accelerometer LN mode does not support ODR values below
12.5Hz.
When transitioning from accelerometer LN mode to accelerometer LP mode, if ODR is greater than 500Hz, software should change
ODR to a value of 500Hz or lower, because accelerometer LP mode does not support ODR values above 500Hz.
12.2 ACCELEROMETER LOW POWER (LP) MODE AVERAGING FILTER SETTING
Software drivers provided with the device use Averaging Filter setting of 16x. This setting is recommended for meeting Android
noise requirements in LP mode, and to minimize accelerometer offset variation when transitioning from LP to Low Noise (LN) mode.
1x averaging filter can be used by following the setting configuration shown in section 14.38.
12.3 SETTINGS FOR I2C, I3CSM, AND SPI OPERATION
Upon bootup the device comes up in SPI mode. The following settings should be used for I2C, I3CSM, and SPI operation.
Scenario 1: INT1/INT2 pins are used for interrupt assertion in I3CSM mode.
Register Field
I3C_EN (bit 4, register INTF_CONFIG6, address 0x7C, bank 1)
I3C_SDR_EN (bit 0, register INTF_CONFIG6, address 0x7C, bank 1)
I3C_DDR_EN (bit 1, register INTF_CONFIG6, address 0x7C, bank 1)
I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A, bank 1)
I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address 0x13, bank 0)
SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address 0x13, bank 0)
I2C Driver Setting
I3CSM Driver Setting
SPI Driver Setting
1
0
0
0
1
1
1
1
0
0
0
5
1
1
1
0
0
5
I2C Driver Setting
I3CSM Driver Setting
SPI Driver Setting
1
0
0
0
1
1
1
1
1
0
0
5
1
1
1
0
0
5
Scenario 2: IBI is used for interrupt assertion in I3CSM mode.
Register Field
I3C_EN (bit 4, register INTF_CONFIG6, address 0x7C, bank 1)
I3C_SDR_EN (bit 0, register INTF_CONFIG6, address 0x7C, bank 1)
I3C_DDR_EN (bit 1, register INTF_CONFIG6, address 0x7C, bank 1)
I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A, bank 1)
I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address 0x13, bank 0)
SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address 0x13, bank 0)
12.4 NOTCH FILTER AND ANTI-ALIAS FILTER OPERATION
Use of Notch Filter and Anti-Alias Filter is supported only for Low Noise (LN) mode operation. The host is responsible for keeping the
UI path in LN mode while Notch Filter and Anti-Alias Filter are turned on.
12.5 EXTERNAL CLOCK INPUT EFFECT ON ODR
ODR values supported by the device scale with external clock frequency, if external clock input is used. The ODR values shown in the
datasheet are supported with external clock input frequency of 32kHz. For any other external clock input frequency, these ODR
values will scale by a factor of (External clock value in kHz / 32). For example, if an external clock frequency of 32.768kHz is used,
instead of ODR value of 500Hz, it will be 500 * (32.768 / 32) = 512Hz.
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12.6 INT_ASYNC_RESET CONFIGURATION
For register INT_CONFIG1 (bank 0 register 0x64) bit 4 INT_ASYNC_RESET, user should change setting to 0 from default setting of 1,
for proper INT1 and INT2 pin operation.
12.7 FIFO TIMESTAMP INTERVAL SCALING
When RTC_MODE =1 (bank 0 register 0x4D bit2) and register INTF_CONFIG5 (bank 1 register 0x7B) bit 2:1 (PIN9_FUNCTION) is set to
10 for CLKIN input;
THEN
Timestamp interval reported in FIFO requires scaling by a factor of 32.768/30. For example when ODR = 1kHz, the true timestamp
interval should be 1000µs. But the value in FIFO toggles between 915 and 916µs. After scaling 915.5 * 32.768/30 = 1000µs.
ELSE
Timestamp interval reported in FIFO requires scaling by a factor of 32/30. For example when ODR = 1kHz, the true timestamp
interval should be 1000µs. But the value in FIFO toggles between 937 and 938µs. After scaling 937.5 * 32/30 = 1000µs.
12.8 SUPPLEMENTARY INFORMATION FOR FIFO_HOLD_LAST_DATA_EN
This section contains supplementary information for using register field FIFO_HOLD_LAST_DATA_EN (bit 7) of register
INTF_CONFIG0 (address 0x4C, bank 0) .
The following table shows the values in FIFO:
16-bit FIFO
Packet
FIFO_HOLD_LAST_DATA_EN
0 (Insert Invalid code)
1 (“copy last valid” mode: No
invalid code insertion)
Valid sample
All values in:
{-32766 to
+32767}
Invalid sample
-32768
Valid sample
All values in:
{-32768 to
+32767}
Invalid sample
20-bit FIFO Packet
Gyro: All Even numbers in {-524256 to
+524286}
Example: {-524256, -524254, -524252, -524250
…..+524284, +524286}
Accel: Every Other Even number in {-524256 to
+524284}
Example: {-524256, -524252, -524248, -524244
…..+524280, +524284}
-524288
Gyro: All Even numbers in {-524288 to
+524286}
Example: {-524288, -524286, -524284, -524282
…..+524284, +524286 }
Accel: Every Other Even number in {-524288 to
+524284 }
Example: {-524288, -524284, -524280
…..+524280, +524284}
Copy last valid sample
The following table shows the values in sense registers on reset:
Power On Reset till
First Sample
FIFO_HOLD_LAST_DATA_EN = 0
FIFO_HOLD_LAST_DATA_EN = 1
Accel/Gyro/Temperature Sensor = -32768
Accel/Gyro/Temperature Sensor = 0
The following table shows the values in sense registers after first sample is received. As shown in table, the combination of
FIFO_HOLD_LAST_DATA_EN and FSYNC Tag determine the range of values read for valid samples and invalid samples.
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FIFO_HOLD_LAST_DATA_EN
0 (Insert
Invalid code)
Valid sample
Invalid
sample
1 (“copy last
valid” mode:
No invalid
code
insertion)
Valid sample
Invalid
sample
FSYNC tag disabled
All values in:
{-32766 to +32767}
FSYNC Enabled on one Sensor
Other Sensor Not
Sensor selected for FSYNC Tag
selected for FSYNC
tagging
FSYNC tagged
FSYNC not tagged
All ODD values in:
All EVEN values in:
All values in:
{-32765 to +32767}
{-32766 to +32766}
{-32766 to +32767}
Registers do not receive invalid samples. Registers hold last valid sample until new one arrives
All values in:
{-32768 to +32767}
All ODD values in:
{-32767 to +32767}
All values in:
{-32768 to +32767}
Registers do not receive invalid samples. Registers hold last valid sample until new one arrives
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All EVEN values in:
{-32768 to +32766}
ICM-42688-P
13 REGISTER MAP
This section lists the register map for the ICM-42688-P, for user banks 0, 1, 2, 3, 4.
USER BANK 0 REGISTER MAP
13.1
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
11
17
DEVICE_CONFIG
R/W
13
19
DRIVE_CONFIG
R/W
14
20
Bit7
Bit6
Bit5
-
INT_CONFIG
Bit4
Bit3
Bit2
SPI_MODE
-
I2C_SLEW_RATE
-
INT2_DRIVE_
CIRCUIT
INT2_MODE
22
FIFO_CONFIG
R/W
29
TEMP_DATA1
SYNCR
1E
30
TEMP_DATA0
SYNCR
TEMP_DATA[7:0]
1F
31
ACCEL_DATA_X1
SYNCR
ACCEL_DATA_X[15:8]
20
32
ACCEL_DATA_X0
SYNCR
ACCEL_DATA_X[7:0]
21
33
ACCEL_DATA_Y1
SYNCR
ACCEL_DATA_Y[15:8]
22
34
ACCEL_DATA_Y0
SYNCR
ACCEL_DATA_Y[7:0]
23
35
ACCEL_DATA_Z1
SYNCR
ACCEL_DATA_Z[15:8]
24
36
ACCEL_DATA_Z0
SYNCR
ACCEL_DATA_Z[7:0]
25
37
GYRO_DATA_X1
SYNCR
GYRO _DATA_X[15:8]
26
38
GYRO _DATA_X0
SYNCR
GYRO _DATA_X[7:0]
27
39
GYRO _DATA_Y1
SYNCR
GYRO _DATA_Y[15:8]
28
40
GYRO _DATA_Y0
SYNCR
GYRO _DATA_Y[7:0]
29
41
GYRO _DATA_Z1
SYNCR
GYRO_DATA_Z[15:8]
2A
42
GYRO _DATA_Z0
SYNCR
GYRO_DATA_Z[7:0]
2B
43
TMST_FSYNCH
SYNCR
TMST_FSYNC_DATA[15:8]
2C
44
TMST_FSYNCL
SYNCR
FIFO_MODE
INT1_DRIVE_
CIRCUIT
INT1_POLARI
TY
FIFO_THS_IN
T
FIFO_FULL_I
NT
AGC_RDY_IN
T
-
TMST_FSYNC_DATA[7:0]
UI_FSYNC_IN
T
-
PLL_RDY_INT
RESET_DONE
_INT
DATA_RDY_I
NT
45
INT_STATUS
R/C
2E
46
FIFO_COUNTH
R
FIFO_COUNT[15:8]
2F
47
FIFO_COUNTL
R
FIFO_COUNT[7:0]
30
48
FIFO_DATA
R
FIFO_DATA
31
49
APEX_DATA0
SYNCR
STEP_CNT[7:0]
32
50
APEX_DATA1
SYNCR
STEP_CNT[15:8]
33
51
APEX_DATA2
R
34
52
APEX_DATA3
R
35
53
APEX_DATA4
R
36
54
APEX_DATA5
R
37
55
INT_STATUS2
R/C
STEP_CADENCE
-
DMP_IDLE
-
TAP_NUM
-
R/C
ACTIVITY_CLASS
TAP_AXIS
TAP_DIR
DOUBLE_TAP_TIMING
-
SMD_INT
STEP_DET_IN
T
-
4B
75
SIGNAL_PATH_RESET
W/C
-
DMP_INIT_E
N
4C
76
INTF_CONFIG0
R/W
FIFO_HOLD_L
AST_DATA_E
N
FIFO_COUNT
_REC
4D
77
INTF_CONFIG1
R/W
4E
78
PWR_MGMT0
R/W
4F
79
GYRO_CONFIG0
R/W
50
80
ACCEL_CONFIG0
51
81
GYRO_CONFIG1
52
82
GYRO_ACCEL_CONFIG0
R/W
ACCEL_UI_FILT_BW
53
83
ACCEL_CONFIG1
R/W
-
WOM_Z_INT
WOM_Y_INT
WOM_X_INT
STEP_CNT_O
VF_INT
TILT_DET_IN
T
WAKE_INT
SLEEP_INT
TAP_DET_INT
ABORT_AND
_RESET
TMST_STROB
E
FIFO_FLUSH
-
DMP_MEM_
RESET_EN
-
FIFO_COUNT
_ENDIAN
SENSOR_DAT
A_ENDIAN
-
ACCEL_LP_CL
K_SEL
TEMP_DIS
IDLE
GYRO_FS_SEL
-
R/W
ACCEL_FS_SEL
-
R/W
TEMP_FILT_BW
-
UI_SIFS_CFG
RTC_MODE
CLKSEL
GYRO_MODE
ACCEL_MODE
GYRO_ODR
ACCEL_ODR
GYRO_UI_FILT_ORD
GYRO_DEC2_M2_ORD
GYRO_UI_FILT_BW
ACCEL_UI_FILT_ORD
Page 60 of 109
Document Number: DS-000347
Revision: 1.2
INT1_MODE
TEMP_DATA[15:8]
2D
INT_STATUS3
SOFT_RESET_
CONFIG
SPI_SLEW_RATE
INT2_POLARI
TY
16
56
Bit0
-
1D
38
Bit1
ACCEL_DEC2_M2_ORD
-
ICM-42688-P
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
54
84
TMST_CONFIG
R/W
56
86
APEX_CONFIG0
R/W
57
87
SMD_CONFIG
R/W
5F
95
FIFO_CONFIG1
R/W
60
96
FIFO_CONFIG2
R/W
61
97
FIFO_CONFIG3
R/W
62
98
FSYNC_CONFIG
R/W
63
99
INT_CONFIG0
R/W
Bit7
Bit6
-
DMP_POWE
R_SAVE
TAP_ENABLE
FIFO_RESUM
E_PARTIAL_R
D
-
-
65
101
INT_SOURCE0
R/W
-
UI_FSYNC_IN
T1_EN
66
102
INT_SOURCE1
R/W
-
I3C_PROTOC
OL_ERROR_I
NT1_EN
68
104
INT_SOURCE3
R/W
-
UI_FSYNC_IN
T2_EN
69
105
INT_SOURCE4
R/W
-
I3C_PROTOC
OL_ERROR_I
NT2_EN
6C
108
FIFO_LOST_PKT0
R
6D
109
FIFO_LOST_PKT1
R
WHO_AM_I
R
118
REG_BANK_SEL
R/W
Bit0
TMST_TO_RE
GS_EN
TMST_RES
TMST_DELTA
_EN
TMST_FSYNC
_EN
TMST_EN
TILT_ENABLE
R2W_EN
-
DMP_ODR
WOM_INT_
MODE
WOM_MODE
SMD_MODE
FIFO_TMST_F
SYNC_EN
FIFO_TEMP_
EN
FIFO_HIRES_
EN
FIFO_ACCEL_
EN
FSYNC_UI_FL
AG_CLEAR_S
EL
FIFO_THS_INT_CLEAR
INT_TDEASSE
RT_DISABLE
INT_ASYNC_
RESET
PLL_RDY_INT
1_EN
RESET_DONE
_INT1_EN
FIFO_FULL_INT_CLEAR
-
PLL_RDY_INT
2_EN
FSYNC_POLA
RITY
RESET_DONE
_INT2_EN
-
UI_DRDY_INT
1_EN
FIFO_THS_IN
T1_EN
FIFO_FULL_I
NT1_EN
UI_AGC_RDY
_INT1_EN
SMD_INT1_E
N
WOM_Z_INT
1_EN
WOM_Y_INT
1_EN
WOM_X_INT
1_EN
UI_DRDY_INT
2_EN
FIFO_THS_IN
T2_EN
FIFO_FULL_I
NT2_EN
UI_AGC_RDY
_INT2_EN
SMD_INT2_E
N
WOM_Z_INT
2_EN
WOM_Y_INT
2_EN
WOM_X_INT
2_EN
EN_GZ_ST
EN_GY_ST
EN_GX_ST
FIFO_LOST_PKT_CNT[15:8]
FIFO_LOST_PKT_CNT[7:0]
ACCEL_ST_P
OWER
R/W
EN_AZ_ST
EN_AY_ST
EN_AX_ST
WHOAMI
-
BANK_SEL
USER BANK 1 REGISTER MAP
13.2
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
03
03
SENSOR_CONFIG0
R/W
0B
11
GYRO_CONFIG_STATIC2
R/W
Bit7
Bit6
-
Bit5
Bit4
Bit3
Bit2
ZG_DISABLE
YG_DISABLE
XG_DISABLE
ZA_DISABLE
0C
12
GYRO_CONFIG_STATIC3
R/W
13
GYRO_CONFIG_STATIC4
R/W
0E
14
GYRO_CONFIG_STATIC5
R/W
0F
15
GYRO_CONFIG_STATIC6
R/W
GYRO_X_NF_COSWZ[7:0]
10
16
GYRO_CONFIG_STATIC7
R/W
GYRO_Y_NF_COSWZ[7:0]
11
17
GYRO_CONFIG_STATIC8
R/W
-
GYRO_AAF_BITSHIFT
GYRO_Z_NF_COSWZ[7:0]
GYRO_Z_NF_
COSWZ_SEL[
0]
GYRO_X_NF_
COSWZ_SEL[
0]
13
19
GYRO_CONFIG_STATIC10
R/W
5F
95
XG_ST_DATA
R/W
XG_ST_DATA
60
96
YG_ST_DATA
R/W
YG_ST_DATA
61
97
ZG_ST_DATA
R/W
ZG_ST_DATA
62
98
TMSTVAL0
R
TMST_VALUE[7:0]
63
99
TMSTVAL1
R
64
100
TMSTVAL2
R
7B
123
INTF_CONFIG5
R/W
124
INTF_CONFIG6
R/W
-
GYRO_Y_NF_
COSWZ_SEL[
0]
R/W
R/W
-
GYRO_Z_NF_
COSWZ[8]
GYRO_NF_BW_SEL
GYRO_Y_NF_
COSWZ[8]
GYRO_X_NF_
COSWZ[8]
-
TMST_VALUE[15:8]
-
TMST_VALUE[19:16]
I3C_BUS_MO
DE
SPI_AP_4WIR
E
-
-
PIN9_FUNCTION
I3C_EN
Page 61 of 109
Document Number: DS-000347
Revision: 1.2
XA_DISABLE
GYRO_NF_DI
S
GYRO_AAF_DELTSQR[11:8]
GYRO_CONFIG_STATIC9
INTF_CONFIG4
YA_DISABLE
GYRO_AAF_D
IS
GYRO_AAF_DELT
18
122
Bit0
GYRO_AAF_DELTSQR[7:0]
12
7A
Bit1
-
0D
7C
FIFO_GYRO_
EN
FIFO_WM[11:8]
UI_DRDY_INT_CLEAR
-
117
Bit1
FSYNC_UI_SEL
R/W
76
FIFO_WM_G
T_TH
-
INT_CONFIG1
75
Bit2
FIFO_WM[7:0]
100
SELF_TEST_CONFIG
Bit3
-
64
112
PED_ENABLE
Bit4
-
INT_TPULSE_
DURATION
70
Bit5
I3C_IBI_BYTE
_EN
I3C_IBI_EN
I3C_DDR_EN
I3C_SDR_EN
ICM-42688-P
USER BANK 2 REGISTER MAP
13.3
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
Bit7
03
03
ACCEL_CONFIG_STATIC2
R/W
-
04
04
ACCEL_CONFIG_STATIC3
R/W
05
05
ACCEL_CONFIG_STATIC4
R/W
3B
59
XA_ST_DATA
R/W
XA_ST_DATA
3C
60
YA_ST_DATA
R/W
YA_ST_DATA
3D
61
ZA_ST_DATA
R/W
ZA_ST_DATA
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ACCEL_AAF_
DIS
ACCEL_AAF_DELT
ACCEL_AAF_DELTSQR[7:0]
ACCEL_AAF_BITSHIFT
ACCEL_AAF_DELTSQR[11:8]
USER BANK 4 REGISTER MAP
13.4
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
40
64
APEX_CONFIG1
R/W
LOW_ENERGY_AMP_TH_SEL
41
65
APEX_CONFIG2
R/W
PED_AMP_TH_SEL
42
66
APEX_CONFIG3
R/W
43
67
APEX_CONFIG4
R/W
44
68
APEX_CONFIG5
R/W
45
69
APEX_CONFIG6
46
70
APEX_CONFIG7
47
71
APEX_CONFIG8
R/W
48
72
APEX_CONFIG9
R/W
4A
74
ACCEL_WOM_X_THR
R/W
WOM_X_TH
4B
75
ACCEL_WOM_Y_THR
R/W
WOM_Y_TH
4C
76
ACCEL_WOM_Z_THR
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
DMP_POWER_SAVE_TIME_SEL
PED_STEP_CNT_TH_SEL
PED_STEP_DET_TH_SEL
PED_SB_TIMER_TH_SEL
TILT_WAIT_TIME_SEL
Bit0
PED_HI_EN_TH_SEL
SLEEP_TIME_OUT
-
-
MOUNTING_MATRIX
R/W
-
SLEEP_GESTURE_DELAY
R/W
TAP_MIN_JERK_THR
-
TAP_TMAX
TAP_MAX_PEAK_TOL
TAP_TAVG
TAP_TMIN
SENSITIVITY_
MODE
-
WOM_Z_TH
4D
77
INT_SOURCE6
R/W
-
STEP_DET_IN
T1_EN
4E
78
INT_SOURCE7
R/W
-
STEP_DET_IN
T2_EN
STEP_CNT_O
FL_INT2_EN
TILT_DET_IN
T2_EN
WAKE_DET_I
NT2_EN
SLEEP_DET_I
NT2_EN
TAP_DET_INT
2_EN
4F
79
INT_SOURCE8
R/W
-
FSYNC_IBI_E
N
PLL_RDY_IBI_
EN
UI_DRDY_IBI
_EN
FIFO_THS_IBI
_EN
FIFO_FULL_IB
I_EN
AGC_RDY_IBI
_EN
50
80
INT_SOURCE9
R/W
SMD_IBI_EN
WOM_Z_IBI_
EN
WOM_Y_IBI_
EN
WOM_X_IBI_
EN
-
51
81
INT_SOURCE10
R/W
STEP_CNT_O
FL_IBI_EN
TILT_DET_IBI
_EN
WAKE_DET_I
BI_EN
SLEEP_DET_I
BI_EN
TAP_DET_IBI
_EN
77
119
OFFSET_USER0
R/W
78
120
OFFSET_USER1
R/W
79
121
OFFSET_USER2
R/W
7A
122
OFFSET_USER3
R/W
7B
123
OFFSET_USER4
R/W
7C
124
OFFSET_USER5
R/W
7D
125
OFFSET_USER6
R/W
7E
126
OFFSET_USER7
R/W
7F
127
OFFSET_USER8
R/W
I3C_PROTOC
OL_ERROR_I
BI_EN
-
-
STEP_DET_IB
I_EN
STEP_CNT_O
FL_INT1_EN
TILT_DET_IN
T1_EN
WAKE_DET_I
NT1_EN
SLEEP_DET_I
NT1_EN
TAP_DET_INT
1_EN
GYRO_X_OFFUSER[7:0]
GYRO_Y_OFFUSER[11:8]
GYRO_X_OFFUSER[11:8]
GYRO_Y_OFFUSER[7:0]
GYRO_Z_OFFUSER[7:0]
ACCEL_X_OFFUSER[11:8]
GYRO_Z_OFFUSER[11:8]
ACCEL_X_OFFUSER[7:0]
ACCEL_Y_OFFUSER[7:0]
ACCEL_Z_OFFUSER[11:8]
ACCEL_Y_OFFUSER[11:8]
ACCEL_Z_OFFUSER[7:0]
Detailed register descriptions are provided in the sections that follow. Please note the following regarding Clock Domain for each
register:
•
Clock Domain: SCLK_UI means that the register is controlled from the UI interface
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used to determine the
default value of reserved register fields, and unless otherwise noted this default value must be maintained even if the values of
other register fields are modified by the user.
Page 62 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14 USER BANK 0 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 0.
Note: The device powers up in sleep mode.
14.1
DEVICE_CONFIG
Name: DEVICE_CONFIG
Address: 17 (11h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:5 4
3:1
0
14.2
SPI_MODE
SOFT_RESET_CONFIG
FUNCTION
Reserved
SPI mode selection
0: Mode 0 and Mode 3 (default)
1: Mode 1 and Mode 2
Reserved
Software reset configuration
0: Normal (default)
1: Enable reset
After writing 1 to this bitfield, wait 1ms for soft reset to be effective, before
attempting any other register access
DRIVE_CONFIG
Name: DRIVE_CONFIG
Address: 19 (13h)
Serial IF: R/W
Reset value: 0x05
Clock Domain: SCLK_UI
BIT NAME
7:6 -
5:3
I2C_SLEW_RATE
2:0
SPI_SLEW_RATE
FUNCTION
Reserved
Controls slew rate for output pin 14 in I2C mode only
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
100: 2ns-6ns
101: < 2ns
110: Reserved
111: Reserved
Controls slew rate for output pin 14 in SPI or I3CSM mode, and for all other
output pins
000: 20ns-60ns
001: 12ns-36ns
010: 6ns-18ns
011: 4ns-12ns
100: 2ns-6ns
101: < 2ns
110: Reserved
111: Reserved
Page 63 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.3
INT_CONFIG
Name: INT_CONFIG
Address: 20 (14h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
INT2_MODE
4
INT2_DRIVE_CIRCUIT
3
INT2_POLARITY
2
INT1_MODE
1
INT1_DRIVE_CIRCUIT
0
INT1_POLARITY
14.4
FIFO_CONFIG
Name: FIFO_CONFIG
Address: 22 (16h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 FIFO_MODE
5:0
14.5
-
FUNCTION
Reserved
INT2 interrupt mode
0: Pulsed mode
1: Latched mode
INT2 drive circuit
0: Open drain
1: Push pull
INT2 interrupt polarity
0: Active low (default)
1: Active high
INT1 interrupt mode
0: Pulsed mode
1: Latched mode
INT1 drive circuit
0: Open drain
1: Push pull
INT1 interrupt polarity
0: Active low (default)
1: Active high
FUNCTION
00: Bypass Mode (default)
01: Stream-to-FIFO Mode
10: STOP-on-FULL Mode
11: STOP-on-FULL Mode
Reserved
TEMP_DATA1
Name: TEMP_DATA1
Address: 29 (1Dh)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 TEMP_DATA[15:8]
FUNCTION
Upper byte of temperature data
Page 64 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.6
TEMP_DATA0
Name: TEMP_DATA0
Address: 30 (1Eh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 TEMP_DATA[7:0]
FUNCTION
Lower byte of temperature data
Temperature sensor register data TEMP_DATA is updated with new data at max(Accelerometer ODR, Gyroscope ODR).
Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigrade by using the
following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25
14.7
ACCEL_DATA_X1
Name: ACCEL_DATA_X1
Address: 31 (1Fh)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_X[15:8]
14.8
ACCEL_DATA_X0
Name: ACCEL_DATA_X0
Address: 32 (20h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_X[7:0]
14.9
FUNCTION
Upper byte of Accel X-axis data
FUNCTION
Lower byte of Accel X-axis data
ACCEL_DATA_Y1
Name: ACCEL_DATA_Y1
Address: 33 (21h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Y[15:8]
FUNCTION
Upper byte of Accel Y-axis data
Page 65 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.10
ACCEL_DATA_Y0
Name: ACCEL_DATA_Y0
Address: 34 (22h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Y[7:0]
14.11
ACCEL_DATA_Z1
Name: ACCEL_DATA_Z1
Address: 35 (23h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Z[15:8]
14.12
FUNCTION
Lower byte of Accel Z-axis data
GYRO_DATA_X1
Name: GYRO_DATA_X1
Address: 37 (25h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_X[15:8]
14.14
FUNCTION
Upper byte of Accel Z-axis data
ACCEL_DATA_Z0
Name: ACCEL_DATA_Z0
Address: 36 (24h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 ACCEL_DATA_Z[7:0]
14.13
FUNCTION
Lower byte of Accel Y-axis data
FUNCTION
Upper byte of Gyro X-axis data
GYRO_DATA_X0
Name: GYRO_DATA_X0
Address: 38 (26h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_X[7:0]
FUNCTION
Lower byte of Gyro X-axis data
Page 66 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.15
GYRO_DATA_Y1
Name: GYRO_DATA_Y1
Address: 39 (27h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Y[15:8]
14.16
GYRO_DATA_Y0
Name: GYRO_DATA_Y0
Address: 40 (28h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Y[7:0]
14.17
FUNCTION
Lower byte of Gyro Z-axis data
TMST_FSYNCH
Name: TMST_FSYNCH
Address: 43 (2Bh)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
FUNCTION
Upper byte of Gyro Z-axis data
GYRO_DATA_Z0
Name: GYRO_DATA_Z0
Address: 42 (2Ah)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Z[7:0]
14.19
FUNCTION
Lower byte of Gyro Y-axis data
GYRO_DATA_Z1
Name: GYRO_DATA_Z1
Address: 41 (29h)
Serial IF: SYNCR
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:0 GYRO_DATA_Z[15:8]
14.18
FUNCTION
Upper byte of Gyro Y-axis data
TMST_FSYNC_DATA_UI[15:8]
FUNCTION
Stores the upper byte of the time delta from the rising edge of FSYNC to
the latest ODR until the UI Interface reads the FSYNC tag in the status
register
Page 67 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.20
TMST_FSYNCL
Name: TMST_FSYNCL
Address: 44 (2Ch)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
14.21
TMST_FSYNC_DATA_UI[7:0]
INT_STATUS
Name: INT_STATUS
Address: 45 (2Dh)
Serial IF: R/C
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7
6
UI_FSYNC_INT
5
PLL_RDY_INT
4
RESET_DONE_INT
3
DATA_RDY_INT
2
FIFO_THS_INT
1
FIFO_FULL_INT
0
AGC_RDY_INT
14.22
FUNCTION
Reserved
This bit automatically sets to 1 when a UI FSYNC interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when a PLL Ready interrupt is generated. The
bit clears to 0 after the register has been read.
This bit automatically sets to 1 when software reset is complete. The bit
clears to 0 after the register has been read.
This bit automatically sets to 1 when a Data Ready interrupt is generated.
The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer reaches the threshold
value. The bit clears to 0 after the register has been read.
This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to
0 after the register has been read.
This bit automatically sets to 1 when an AGC Ready interrupt is generated.
The bit clears to 0 after the register has been read.
FIFO_COUNTH
Name: FIFO_COUNTH
Address: 46 (2Eh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
FUNCTION
Stores the lower byte of the time delta from the rising edge of FSYNC to
the latest ODR until the UI Interface reads the FSYNC tag in the status
register
FIFO_COUNT[15:8]
FUNCTION
High Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH
and FIFO_COUNTL.
Page 68 of 109
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Revision: 1.2
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14.23
FIFO_COUNTL
Name: FIFO_COUNTL
Address: 47 (2Fh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
14.24
FIFO_COUNT[7:0]
FIFO_DATA
Name: FIFO_DATA
Address: 48 (30h)
Serial IF: R
Reset value: 0xFF
Clock Domain: SCLK_UI
BIT NAME
7:0 FIFO_DATA
14.25
FUNCTION
FIFO data port
APEX_DATA0
Name: APEX_DATA0
Address: 49 (31h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 STEP_CNT[7:0]
14.26
FUNCTION
Low Bits, count indicates the number of records or bytes available in FIFO
according to FIFO_COUNT_REC setting.
Reading this byte latches the data for both FIFO_COUNTH, and
FIFO_COUNTL.
FUNCTION
Pedometer Output: Lower byte of Step Count measured by pedometer
APEX_DATA1
Name: APEX_DATA1
Address: 50 (32h)
Serial IF: SYNCR
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 STEP_CNT[15:8]
FUNCTION
Pedometer Output: Upper byte of Step Count measured by pedometer
Page 69 of 109
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14.27
APEX_DATA2
Name: APEX_DATA2
Address: 51 (33h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
STEP_CADENCE
14.28
APEX_DATA3
Name: APEX_DATA3
Address: 52 (34h)
Serial IF: R
Reset value: 0x04
Clock Domain: SCLK_UI
BIT NAME
7:3 2
1:0
DMP_IDLE
ACTIVITY_CLASS
FUNCTION
Pedometer Output: Walk/run cadency in number of samples. Format is
u6.2. e.g. At 50Hz ODR and 2Hz walk frequency, the cadency is 25 samples.
The register will output 100.
FUNCTION
Reserved
0: Indicates DMP is running
1: Indicates DMP is idle
Pedometer Output: Detected activity
00: Unknown
01: Walk
10: Run
11: Reserved
Page 70 of 109
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14.29
APEX_DATA4
Name: APEX_DATA4
Address: 53 (35h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:5 -
4:3
TAP_NUM
2:1
TAP_AXIS
0
TAP_DIR
14.30
APEX_DATA5
Name: APEX_DATA5
Address: 54 (36h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 -
5:0
FUNCTION
Reserved
Tap Detection Output: Number of taps in the current Tap event
00: No tap
01: Single tap
10: Double tap
11: Reserved
Tap Detection Output: Represents the accelerometer axis on which tap
energy is concentrated
00: X-axis
01: Y-axis
10: Z-axis
11: Reserved
Tap Detection Output: Polarity of tap pulse
0: Current accelerometer value – Previous accelerometer value is a positive
value
1: Current accelerometer value – Previous accelerometer value is a negative
value or zero
DOUBLE_TAP_TIMING
FUNCTION
Reserved
DOUBLE_TAP_TIMING measures the time interval between the two taps
when double tap is detected. It counts every 16 accelerometer samples as
one unit between the 2 tap pulses. Therefore, the value is related to the
accelerometer ODR.
Time in seconds = DOUBLE_TAP_TIMING * 16 / ODR
For example, if the accelerometer ODR is 500 Hz, and the
DOUBLE_TAP_TIMING register reading is 6, the time interval value is
6*16/500 = 0.192 seconds.
Page 71 of 109
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Revision: 1.2
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14.31
INT_STATUS2
Name: INT_STATUS2
Address: 55 (37h)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3
SMD_INT
2
WOM_Z_INT
1
WOM_Y_INT
0
WOM_X_INT
14.32
INT_STATUS3
Name: INT_STATUS3
Address: 56 (38h)
Serial IF: R/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
STEP_DET_INT
4
STEP_CNT_OVF_INT
3
TILT_DET_INT
2
WAKE_INT
1
SLEEP_INT
0
TAP_DET_INT
14.33
FUNCTION
Reserved
Significant Motion Detection Interrupt, clears on read
Wake on Motion Interrupt on Z-axis, clears on read
Wake on Motion Interrupt on Y-axis, clears on read
Wake on Motion Interrupt on X-axis, clears on read
FUNCTION
Reserved
Step Detection Interrupt, clears on read
Step Count Overflow Interrupt, clears on read
Tilt Detection Interrupt, clears on read
Wake Event Interrupt, clears on read
Sleep Event Interrupt, clears on read
Tap Detection Interrupt, clears on read
SIGNAL_PATH_RESET
Name: SIGNAL_PATH_RESET
Address: 75 (4Bh)
Serial IF: W/C
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6
DMP_INIT_EN
5
DMP_MEM_RESET_EN
4
3
ABORT_AND_RESET
2
TMST_STROBE
1
0
FIFO_FLUSH
-
FUNCTION
Reserved
When this bit is set to 1, the DMP is enabled
When this bit is set to 1, the DMP memory is reset
Reserved
When this bit is set to 1, the signal path is reset by restarting the ODR
counter and signal path controls
When this bit is set to 1, the time stamp counter is latched into the time
stamp register. This is a write on clear bit.
When set to 1, FIFO will get flushed.
Reserved
Page 72 of 109
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Revision: 1.2
ICM-42688-P
14.34
INTF_CONFIG0
Name: INTF_CONFIG0
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x30
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
This bit selects the treatment of invalid samples. See Invalid Data
Generation note below this register description.
Setting this bit to 0:
In order to signal an invalid sample, and to differentiate it from a valid
sample based on values only:
Sense Registers:
• Do not receive invalid samples. They hold the last valid
sample. Repeated reading before new sample received will yield copies
of the last valid sample.
• Valid samples of values -32768, -32767 are replaced with -32766
• FSYNC Tagging can modify the least significant bit and further limit
values (see section 12.8).
7
FIFO_HOLD_LAST_DATA_E
N
FIFO:
• 16-bit FIFO packet: Same as Sense Registers, except:
o FSYNC tagging is not applied to data in FIFO.
• 20-bit FIFO packet:
o Invalid samples are indicated with the value -524288
o Valid samples in {-524288 to -524258} are replaced by -524256
o Valid Gyro samples: All Even numbers in { -524256 to
+524286}
o Valid Accel samples: All numbers divisible by 4 in {-524256 to
+524284}
o FSYNC tagging is not applied to data in FIFO.
Setting this bit to 1:
Sense registers:
• Do not receive invalid samples. They hold the last valid
sample. Repeated reading before new sample received will yield copies
of the last valid sample.
• FSYNC Tagging can modify the least significant bit and further limit
values (see section 12.8).
FIFO:
• Invalid sample will get copy of last valid sample
• 16-bit FIFO packet: Same as Sense Registers, except:
o FSYNC tagging is not applied to data in FIFO.
• 20-bit FIFO packet:
o Valid Gyro samples: All Even numbers in {-524288 to
+524286}
o - Valid Accel samples: All numbers divisible by 4 in {-524288 to
+524284}
o FSYNC tagging is not applied to data in FIFO.
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6
FIFO_COUNT_REC
5
FIFO_COUNT_ENDIAN
4
SENSOR_DATA_ENDIAN
3:2
-
1:0
UI_SIFS_CFG
0: FIFO count is reported in bytes
1: FIFO count is reported in records (1 record = 16 bytes for header + gyro +
accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel +
temp sensor data, or 20 bytes for header + gyro + accel + temp sensor data +
time stamp + 20-bit extension data)
0: FIFO count is reported in Little Endian format
1: FIFO count is reported in Big Endian format (default)
0: Sensor data is reported in Little Endian format
1: Sensor data is reported in Big Endian format (default)
Reserved
0x: Reserved
10: Disable SPI
11: Disable I2C
Invalid Data Generation: FIFO/Sense Registers may contain invalid data under the following conditions:
a) From power on reset to first ODR sample of any sensor (accel, gyro, temp sensor)
b) When any sensor is disabled (accel, gyro, temp sensor)
c) When accel and gyro are enabled with different ODRs. In this case, the sensor with lower ODR will generate invalid samples
when it has no new data.
Invalid data can take special values or can hold last valid sample received. For -32768 to be used as a flag for invalid accel/gyro
samples, the valid accel/gyro sample range is limited in such case as well. Bit 7 of INTF_CONFIG0 controls what values invalid (and
valid) samples can take as shown above.
14.35
INTF_CONFIG1
Name: INTF_CONFIG1
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x91
Clock Domain: SCLK_UI
BIT NAME
7:4 3
ACCEL_LP_CLK_SEL
2
RTC_MODE
1:0
CLKSEL
FUNCTION
Reserved
0: Accelerometer LP mode uses Wake Up oscillator clock
1: Accelerometer LP mode uses RC oscillator clock
0: No input RTC clock is required
1: RTC clock input is required
00: Always select internal RC oscillator
01: Select PLL when available, else select RC oscillator (default)
10: Reserved
11: Disable all clocks
Page 74 of 109
Document Number: DS-000347
Revision: 1.2
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14.36
PWR_MGMT0
Name: PWR_MGMT0
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
TEMP_DIS
4
IDLE
3:2
1:0
GYRO_MODE
ACCEL_MODE
FUNCTION
Reserved
0: Temperature sensor is enabled (default)
1: Temperature sensor is disabled
If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro
are powered off.
Nominally this bit is set to 0, so when Accel and Gyro are powered off,
the chip will go to OFF state, since the RC oscillator will also be powered off
00: Turns gyroscope off (default)
01: Places gyroscope in Standby Mode
10: Reserved
11: Places gyroscope in Low Noise (LN) Mode
Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning
from OFF to any of the other modes, do not issue any register writes for
200µs.
00: Turns accelerometer off (default)
01: Turns accelerometer off
10: Places accelerometer in Low Power (LP) Mode
11: Places accelerometer in Low Noise (LN) Mode
When transitioning from OFF to any of the other modes, do not issue any
register writes for 200µs.
Page 75 of 109
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Revision: 1.2
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14.37
GYRO_CONFIG0
Name: GYRO_CONFIG0
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x06
Clock Domain: SCLK_UI
BIT NAME
7:5
4
3:0
GYRO_FS_SEL
-
GYRO_ODR
FUNCTION
Full scale select for gyroscope UI interface output
000: ±2000dps (default)
001: ±1000dps
010: ±500dps
011: ±250dps
100: ±125dps
101: ±62.5dps
110: ±31.25dps
111: ±15.625dps
Reserved
Gyroscope ODR selection for UI interface output
0000: Reserved
0001: 32kHz
0010: 16kHz
0011: 8kHz
0100: 4kHz
0101: 2kHz
0110: 1kHz (default)
0111: 200Hz
1000: 100Hz
1001: 50Hz
1010: 25Hz
1011: 12.5Hz
1100: Reserved
1101: Reserved
1110: Reserved
1111: 500Hz
Page 76 of 109
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Revision: 1.2
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14.38
ACCEL_CONFIG0
Name: ACCEL_CONFIG0
Address: 80 (50h)
Serial IF: R/W
Reset value: 0x06
Clock Domain: SCLK_UI
BIT NAME
7:5
4
3:0
ACCEL_FS_SEL
-
ACCEL_ODR
FUNCTION
Full scale select for accelerometer UI interface output
000: ±16g (default)
001: ±8g
010: ±4g
011: ±2g
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Reserved
Accelerometer ODR selection for UI interface output
0000: Reserved
0001: 32kHz (LN mode)
0010: 16kHz (LN mode)
0011: 8kHz (LN mode)
0100: 4kHz (LN mode)
0101: 2kHz (LN mode)
0110: 1kHz (LN mode) (default)
0111: 200Hz (LP or LN mode)
1000: 100Hz (LP or LN mode)
1001: 50Hz (LP or LN mode)
1010: 25Hz (LP or LN mode)
1011: 12.5Hz (LP or LN mode)
1100: 6.25Hz (LP mode)
1101: 3.125Hz (LP mode)
1110: 1.5625Hz (LP mode)
1111: 500Hz (LP or LN mode)
Page 77 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.39
GYRO_CONFIG1
Name: GYRO_CONFIG1
Address: 81 (51h)
Serial IF: R/W
Reset value: 0x16
Clock Domain: SCLK_UI
BIT NAME
7:5
4
TEMP_FILT_BW
-
3:2
GYRO_UI_FILT_ORD
1:0
GYRO_DEC2_M2_ORD
FUNCTION
Sets the bandwidth of the temperature signal DLPF
000: DLPF BW = 4000Hz; DLPF Latency = 0.125ms (default)
001: DLPF BW = 170Hz; DLPF Latency = 1ms
010: DLPF BW = 82Hz; DLPF Latency = 2ms
011: DLPF BW = 40Hz; DLPF Latency = 4ms
100: DLPF BW = 20Hz; DLPF Latency = 8ms
101: DLPF BW = 10Hz; DLPF Latency = 16ms
110: DLPF BW = 5Hz; DLPF Latency = 32ms
111: DLPF BW = 5Hz; DLPF Latency = 32ms
Reserved
Selects order of GYRO UI filter
00: 1st Order
01: 2nd Order
10: 3rd Order
11: Reserved
Selects order of GYRO DEC2_M2 Filter
00: Reserved
01: Reserved
10: 3rd Order
11: Reserved
Page 78 of 109
Document Number: DS-000347
Revision: 1.2
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14.40
GYRO_ACCEL_CONFIG0
Name: GYRO_ACCEL_CONFIG0
Address: 82 (52h)
Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT NAME
7:4
3:0
ACCEL_UI_FILT_BW
GYRO_UI_FILT_BW
FUNCTION
LN Mode:
Bandwidth for Accel LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(200Hz, 8*ODR)
LP Mode:
0 Reserved
1 1x AVG filter (default)
2 to 5 Reserved
6 16x AVG filter
7 to 15 Reserved
LN Mode:
Bandwidth for Gyro LPF
0 BW=ODR/2
1 BW=max(400Hz, ODR)/4 (default)
2 BW=max(400Hz, ODR)/5
3 BW=max(400Hz, ODR)/8
4 BW=max(400Hz, ODR)/10
5 BW=max(400Hz, ODR)/16
6 BW=max(400Hz, ODR)/20
7 BW=max(400Hz, ODR)/40
8 to 13: Reserved
14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(400Hz, ODR)
15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2
runs at max(200Hz, 8*ODR)
Page 79 of 109
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Revision: 1.2
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14.41
ACCEL_CONFIG1
Name: ACCEL_CONFIG1
Address: 83 (53h)
Serial IF: R/W
Reset value: 0x0D
Clock Domain: SCLK_UI
BIT NAME
7:5 -
4:3
ACCEL_UI_FILT_ORD
2:1
ACCEL_DEC2_M2_ORD
0
14.42
-
FUNCTION
Reserved
Selects order of ACCEL UI filter
00: 1st Order
01: 2nd Order
10: 3rd Order
11: Reserved
Order of Accelerometer DEC2_M2 filter
00: Reserved
01: Reserved
10: 3rd order
11: Reserved
Reserved
TMST_CONFIG
Name: TMST_CONFIG
Address: 84 (54h)
Serial IF: R/W
Reset value: 0x23
Clock Domain: SCLK_UI
BIT NAME
7:5 4
TMST_TO_REGS_EN
3
TMST_RES
2
TMST_DELTA_EN
1
TMST_FSYNC_EN
0
TMST_EN
FUNCTION
Reserved
0: TMST_VALUE[19:0] read always returns 0s
1: TMST_VALUE[19:0] read returns timestamp value
Time Stamp resolution: When set to 0 (default), time stamp resolution is 1
µs. When set to 1, resolution is 16µs
Time Stamp delta enable: When set to 1, the time stamp field contains the
measurement of time since the last occurrence of ODR.
Time Stamp register FSYNC enable (default). When set to 1, the contents of
the Timestamp feature of FSYNC is enabled. The user also needs to select
FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the
FIFO.
0: Time Stamp register disable
1: Time Stamp register enable (default)
Page 80 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.43
APEX_CONFIG0
Name: APEX_CONFIG0
Address: 86 (56h)
Serial IF: R/W
Reset value: 0x82
Clock Domain: SCLK_UI
BIT NAME
7
DMP_POWER_SAVE
6
TAP_ENABLE
5
PED_ENABLE
4
TILT_ENABLE
3
R2W_EN
2
-
1:0
14.44
DMP_ODR
FUNCTION
0: DMP power save mode not active
1: DMP power save mode active (default)
0: Tap Detection not enabled
1: Tap Detection enabled when accelerometer ODR is set to one of the ODR
values supported by Tap Detection (200Hz, 500Hz, 1kHz)
0: Pedometer not enabled
1: Pedometer enabled
0: Tilt Detection not enabled
1: Tilt Detection enabled
0: Raise to Wake/Sleep not enabled
1: Raise to Wake/Sleep enabled
Reserved
00: 25Hz
01: Reserved
10: 50Hz
11: Reserved
SMD_CONFIG
Name: SMD_CONFIG
Address: 87 (57h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3
WOM_INT_MODE
2
WOM_MODE
1:0
SMD_MODE
FUNCTION
Reserved
0: Set WoM interrupt on the OR of all enabled accelerometer thresholds
1: Set WoM interrupt on the AND of all enabled accelerometer threshold
0: Initial sample is stored. Future samples are compared to initial sample
1: Compare current sample to previous sample
00: SMD disabled
01: Reserved
10: SMD short (1 sec wait) An SMD event is detected when two WOM are
detected 1 sec apart
11: SMD long (3 sec wait) An SMD event is detected when two WOM are
detected 3 sec apart
Page 81 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.45
FIFO_CONFIG1
Name: FIFO_CONFIG1
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6
FIFO_RESUME_PARTIAL_RD
5
FIFO_WM_GT_TH
4
FIFO_HIRES_EN
3
2
1
0
FIFO_TMST_FSYNC_EN
FIFO_TEMP_EN
FIFO_GYRO_EN
FIFO_ACCEL_EN
14.46
FIFO_CONFIG2
Name: FIFO_CONFIG2
Address: 96 (60h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
14.47
FIFO_WM[7:0]
FUNCTION
Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_REC setting. FIFO_WM_EN must be zero before writing this
register. Interrupt only fires once. This register should be set to non-zero
value, before choosing this interrupt source.
FIFO_CONFIG3
Name: FIFO_CONFIG3
Address: 97 (61h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 -
3:0
FUNCTION
Reserved
0: Partial FIFO read disabled, requires re-reading of the entire FIFO
1: FIFO read can be partial, and resume from last read point
Trigger FIFO watermark interrupt on every ODR (DMA write) if
FIFO_COUNT ≥ FIFO_WM_TH
Enable 3 bytes of extended 20-bits accel, gyro data + 1 byte of extended
16-bit temperature sensor data to be placed into the FIFO
Must be set to 1 for all FIFO use cases when FSYNC is used.
Enable temperature sensor packets to go to FIFO
Enable gyroscope packets to go to FIFO
Enable accelerometer packets to go to FIFO
FIFO_WM[11:8]
FUNCTION
Reserved
Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches
or exceeds FIFO_WM size in bytes or records according to
FIFO_COUNT_REC setting. FIFO_WM_EN must be zero before writing this
register. Interrupt only fires once. This register should be set to non-zero
value, before choosing this interrupt source.
Note: Do not set FIFO_WM to value 0.
Page 82 of 109
Document Number: DS-000347
Revision: 1.2
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14.48
FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 98 (62h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7
-
6:4
FSYNC_UI_SEL
3:2
-
1
FSYNC_UI_FLAG_CLEAR_SE
L
0
FSYNC_POLARITY
FUNCTION
Reserved
000: Do not tag FSYNC flag
001: Tag FSYNC flag to TEMP_OUT LSB
010: Tag FSYNC flag to GYRO_XOUT LSB
011: Tag FSYNC flag to GYRO_YOUT LSB
100: Tag FSYNC flag to GYRO_ZOUT LSB
101: Tag FSYNC flag to ACCEL_XOUT LSB
110: Tag FSYNC flag to ACCEL_YOUT LSB
111: Tag FSYNC flag to ACCEL_ZOUT LSB
Reserved
0: FSYNC flag is cleared when UI sensor register is updated
1: FSYNC flag is cleared when UI interface reads the sensor register LSB of
FSYNC tagged axis
0: Start from Rising edge of FSYNC pulse to measure FSYNC interval
1: Start from Falling edge of FSYNC pulse to measure FSYNC interval
Please also refer to Section 12.8 for supplementary information on FSYNC tag.
14.49
INT_CONFIG0
Name: INT_CONFIG0
Address: 99 (63h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 -
5:4
UI_DRDY_INT_CLEAR
3:2
FIFO_THS_INT_CLEAR
1:0
FIFO_FULL_INT_CLEAR
FUNCTION
Reserved
Data Ready Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on Sensor Register Read
11: Clear on Status Bit Read AND on Sensor Register read
FIFO Threshold Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
FIFO Full Interrupt Clear Option (latched mode)
00: Clear on Status Bit Read (default)
01: Clear on Status Bit Read
10: Clear on FIFO data 1Byte Read
11: Clear on Status Bit Read AND on FIFO data 1 byte read
Page 83 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.50
INT_CONFIG1
Name: INT_CONFIG1
Address: 100 (64h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7
6
INT_TPULSE_DURATION
5
INT_TDEASSERT_DISABLE
4
INT_ASYNC_RESET
3:0
14.51
-
FUNCTION
Reserved
Interrupt pulse duration
0: Interrupt pulse duration is 100µs. Use only if ODR < 4kHz. (Default)
1: Interrupt pulse duration is 8 µs. Required if ODR ≥ 4kHz, optional for ODR
< 4kHz.
Interrupt de-assertion duration
0: The interrupt de-assertion duration is set to a minimum of 100µs. Use
only if ODR < 4kHz. (Default)
1: Disables de-assert duration. Required if ODR ≥ 4kHz, optional for ODR <
4kHz.
User should change setting to 0 from default setting of 1, for proper INT1
and INT2 pin operation
Reserved
INT_SOURCE0
Name: INT_SOURCE0
Address: 101 (65h)
Serial IF: R/W
Reset value: 0x10
Clock Domain: SCLK_UI
BIT NAME
7
6
UI_FSYNC_INT1_EN
5
PLL_RDY_INT1_EN
4
RESET_DONE_INT1_EN
3
UI_DRDY_INT1_EN
2
FIFO_THS_INT1_EN
1
FIFO_FULL_INT1_EN
0
UI_AGC_RDY_INT1_EN
FUNCTION
Reserved
0: UI FSYNC interrupt not routed to INT1
1: UI FSYNC interrupt routed to INT1
0: PLL ready interrupt not routed to INT1
1: PLL ready interrupt routed to INT1
0: Reset done interrupt not routed to INT1
1: Reset done interrupt routed to INT1
0: UI data ready interrupt not routed to INT1
1: UI data ready interrupt routed to INT1
0: FIFO threshold interrupt not routed to INT1
1: FIFO threshold interrupt routed to INT1
0: FIFO full interrupt not routed to INT1
1: FIFO full interrupt routed to INT1
0: UI AGC ready interrupt not routed to INT1
1: UI AGC ready interrupt routed to INT1
Page 84 of 109
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Revision: 1.2
ICM-42688-P
14.52
INT_SOURCE1
Name: INT_SOURCE1
Address: 102 (66h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
I3C_PROTOCOL_ERROR_IN
6
T1_EN
5:4 3
SMD_INT1_EN
2
WOM_Z_INT1_EN
1
WOM_Y_INT1_EN
0
WOM_X_INT1_EN
14.53
FUNCTION
Reserved
0: I3CSM protocol error interrupt not routed to INT1
1: I3CSM protocol error interrupt routed to INT1
Reserved
0: SMD interrupt not routed to INT1
1: SMD interrupt routed to INT1
0: Z-axis WOM interrupt not routed to INT1
1: Z-axis WOM interrupt routed to INT1
0: Y-axis WOM interrupt not routed to INT1
1: Y-axis WOM interrupt routed to INT1
0: X-axis WOM interrupt not routed to INT1
1: X-axis WOM interrupt routed to INT1
INT_SOURCE3
Name: INT_SOURCE3
Address: 104 (68h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6
UI_FSYNC_INT2_EN
5
PLL_RDY_INT2_EN
4
RESET_DONE_INT2_EN
3
UI_DRDY_INT2_EN
2
FIFO_THS_INT2_EN
1
FIFO_FULL_INT2_EN
0
UI_AGC_RDY_INT2_EN
FUNCTION
Reserved
0: UI FSYNC interrupt not routed to INT2
1: UI FSYNC interrupt routed to INT2
0: PLL ready interrupt not routed to INT2
1: PLL ready interrupt routed to INT2
0: Reset done interrupt not routed to INT2
1: Reset done interrupt routed to INT2
0: UI data ready interrupt not routed to INT2
1: UI data ready interrupt routed to INT2
0: FIFO threshold interrupt not routed to INT2
1: FIFO threshold interrupt routed to INT2
0: FIFO full interrupt not routed to INT2
1: FIFO full interrupt routed to INT2
0: UI AGC ready interrupt not routed to INT2
1: UI AGC ready interrupt routed to INT2
Page 85 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
14.54
INT_SOURCE4
Name: INT_SOURCE4
Address: 105 (69h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
I3C_PROTOCOL_ERROR_IN
6
T2_EN
5:4 3
SMD_INT2_EN
2
WOM_Z_INT2_EN
1
WOM_Y_INT2_EN
0
WOM_X_INT2_EN
14.55
FIFO_LOST_PKT0
Name: FIFO_LOST_PKT0
Address: 108 (6Ch)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 FIFO_LOST_PKT_CNT[7:0]
14.56
FUNCTION
Reserved
0: I3CSM protocol error interrupt not routed to INT2
1: I3CSM protocol error interrupt routed to INT2
Reserved
0: SMD interrupt not routed to INT2
1: SMD interrupt routed to INT2
0: Z-axis WOM interrupt not routed to INT2
1: Z-axis WOM interrupt routed to INT2
0: Y-axis WOM interrupt not routed to INT2
1: Y-axis WOM interrupt routed to INT2
0: X-axis WOM interrupt not routed to INT2
1: X-axis WOM interrupt routed to INT2
FUNCTION
Low byte, number of packets lost in the FIFO
FIFO_LOST_PKT1
Name: FIFO_LOST_PKT1
Address: 109 (6Dh)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0 FIFO_LOST_PKT_CNT[15:8]
FUNCTION
High byte, number of packets lost in the FIFO
Page 86 of 109
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Revision: 1.2
ICM-42688-P
14.57
SELF_TEST_CONFIG
Name: SELF_TEST_CONFIG
Address: 112 (70h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7
6
ACCEL_ST_POWER
5
4
3
2
1
0
EN_AZ_ST
EN_AY_ST
EN_AX_ST
EN_GZ_ST
EN_GY_ST
EN_GX_ST
14.58
FUNCTION
Reserved
Set to 1 for accel self-test
Otherwise set to 0; Set to 0 after self-test is completed
Enable Z-accel self-test
Enable Y-accel self-test
Enable X-accel self-test
Enable Z-gyro self-test
Enable Y-gyro self-test
Enable X-gyro self-test
WHO_AM_I
Name: WHO_AM_I
Address: 117 (75h)
Serial IF: R
Reset value: 0x47
Clock Domain: SCLK_UI
BIT NAME
7:0 WHOAMI
FUNCTION
Register to indicate to user which device is being accessed
Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the
register is 0x47. This is different from the I2C address of the device as seen on the slave I2C controller by the applications processor.
14.59
REG_BANK_SEL
Note: This register is accessible from all register banks
Name: REG_BANK_SEL
Address: 118 (76h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: ALL
BIT NAME
7:3 -
2:0
BANK_SEL
FUNCTION
Reserved
Register bank selection
000: Bank 0 (default)
001: Bank 1
010: Bank 2
011: Bank 3
100: Bank 4
101: Reserved
110: Reserved
111: Reserved
Page 87 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
15 USER BANK 1 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 1.
15.1
SENSOR_CONFIG0
Name: SENSOR_CONFIG0
Address: 03 (03h)
Serial IF: R/W
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:6 5
ZG_DISABLE
4
YG_DISABLE
3
XG_DISABLE
2
ZA_DISABLE
1
YA_DISABLE
0
XA_DISABLE
15.2
GYRO_CONFIG_STATIC2
Name: GYRO_CONFIG_STATIC2
Address: 11 (0Bh)
Serial IF: R/W
Reset value: 0xA0
Clock Domain: SCLK_UI
BIT NAME
7:2 1
GYRO_AAF_DIS
0
GYRO_NF_DIS
15.3
FUNCTION
Reserved
0: Enable gyroscope anti-aliasing filter (default)
1: Disable gyroscope anti-aliasing filter
0: Enable Notch Filter (default)
1: Disable Notch Filter
GYRO_CONFIG_STATIC3
Name: GYRO_CONFIG_STATIC3
Address: 12 (0Ch)
Serial IF: R/W
Reset value: 0x0D
Clock Domain: SCLK_UI
BIT NAME
7:6 5:0
FUNCTION
Reserved
0: Z gyroscope is on
1: Z gyroscope is disabled
0: Y gyroscope is on
1: Y gyroscope is disabled
0: X gyroscope is on
1: X gyroscope is disabled
0: Z accelerometer is on
1: Z accelerometer is disabled
0: Y accelerometer is on
1: Y accelerometer is disabled
0: X accelerometer is on
1: X accelerometer is disabled
GYRO_AAF_DELT
FUNCTION
Reserved
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
Page 88 of 109
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Revision: 1.2
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15.4
GYRO_CONFIG_STATIC4
Name: GYRO_CONFIG_STATIC4
Address: 13 (0Dh)
Serial IF: R/W
Reset value: 0xAA
Clock Domain: SCLK_UI
BIT NAME
7:0
15.5
GYRO_AAF_DELTSQR[7:0]
GYRO_CONFIG_STATIC5
Name: GYRO_CONFIG_STATIC5
Address: 14 (0Eh)
Serial IF: R/W
Reset value: 0x80
Clock Domain: SCLK_UI
BIT NAME
7:4
GYRO_AAF_BITSHIFT
3:0
GYRO_AAF_DELTSQR[11:8]
15.6
FUNCTION
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
FUNCTION
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
Controls bandwidth of the gyroscope anti-alias filter
See section 5.2 for details
GYRO_CONFIG_STATIC6
Name: GYRO_CONFIG_STATIC6
Address: 15 (0Fh)
Serial IF: R/W
Reset value: 0xXX (Factory trimmed on an individual device basis)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Used for gyroscope X-axis notch filter frequency selection
7:0 GYRO_X_NF_COSWZ[7:0]
See section 5.1 for details
15.7
GYRO_CONFIG_STATIC7
Name: GYRO_CONFIG_STATIC7
Address: 16 (10h)
Serial IF: R/W
Reset value: 0xXX (Factory trimmed on an individual device basis)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Used for gyroscope Y-axis notch filter frequency selection
7:0 GYRO_Y_NF_COSWZ[7:0]
See section 5.1 for details
Page 89 of 109
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Revision: 1.2
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15.8
GYRO_CONFIG_STATIC8
Name: GYRO_CONFIG_STATIC8
Address: 17 (11h)
Serial IF: R/W
Reset value: 0xXX (Factory trimmed on an individual device basis)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
Used for gyroscope Z-axis notch filter frequency selection
7:0 GYRO_Z_NF_COSWZ[7:0]
See section 5.1 for details
15.9
GYRO_CONFIG_STATIC9
Name: GYRO_CONFIG_STATIC9
Address: 18 (12h)
Serial IF: R/W
Reset value: 0xXX (Factory trimmed on an individual device basis)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:6 Reserved
Used for gyroscope Z-axis notch filter frequency selection
5
GYRO_Z_NF_COSWZ_SEL[0]
See section 5.1 for details
Used for gyroscope Y-axis notch filter frequency selection
4
GYRO_Y_NF_COSWZ_SEL[0]
See section 5.1 for details
Used for gyroscope X-axis notch filter frequency selection
3
GYRO_X_NF_COSWZ_SEL[0]
See section 5.1 for details
Used for gyroscope Z-axis notch filter frequency selection
2
GYRO_Z_NF_COSWZ[8]
See section 5.1 for details
Used for gyroscope Y-axis notch filter frequency selection
1
GYRO_Y_NF_COSWZ[8]
See section 5.1 for details
Used for gyroscope X-axis notch filter frequency selection
0
GYRO_X_NF_COSWZ[8]
See section 5.1 for details
15.10
GYRO_CONFIG_STATIC10
Name: GYRO_CONFIG_STATIC10
Address: 19 (13h)
Serial IF: R/W
Reset value: 0x11
Clock Domain: SCLK_UI
BIT NAME
7
6:4
GYRO_NF_BW_SEL
3:0
-
FUNCTION
Reserved
Selects bandwidth for gyroscope notch filter
See section 5.1 for details
Reserved
Page 90 of 109
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Revision: 1.2
ICM-42688-P
15.11
XG_ST_DATA
Name: XG_ST_DATA
Address: 95 (5Fh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 XG_ST_DATA
X-gyro self-test data
15.12
YG_ST_DATA
Name: YG_ST_DATA
Address: 96 (60h)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 YG_ST_DATA
Y-gyro self-test data
15.13
ZG_ST_DATA
Name: ZG_ST_DATA
Address: 97 (61h)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ZG_ST_DATA
Z-gyro self-test data
15.14
TMSTVAL0
Name: TMSTVAL0
Address: 98 (62h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
TMST_VALUE[7:0]
FUNCTION
When TMST_STROBE is programmed, the current value of the internal
counter is latched to this register. Allows the full 20-bit precision of the time
stamp to be read back.
Page 91 of 109
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Revision: 1.2
ICM-42688-P
15.15
TMSTVAL1
Name: TMSTVAL1
Address: 99 (63h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
15.16
TMST_VALUE[15:8]
TMSTVAL2
Name: TMSTVAL2
Address: 100 (64h)
Serial IF: R
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4 3:0 TMST_VALUE[19:16]
15.17
5:2
FUNCTION
Reserved
When TMST_STROBE is programmed, the current value of the internal
counter is latched to this register. Allows the full 20-bit precision of the time
stamp to be read back.
INTF_CONFIG4
Name: INTF_CONFIG4
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x83
Clock Domain: SCLK_UI
BIT NAME
7:2 6
FUNCTION
When TMST_STROBE is programmed, the current value of the internal
counter is latched to this register. Allows the full 20-bit precision of the time
stamp to be read back.
I3C_BUS_MODE
-
1
SPI_AP_4WIRE
0
-
FUNCTION
Reserved
0: Device is on a bus with I2C and I3CSM devices
1: Device is on a bus with I3CSM devices only
Reserved
0: AP interface uses 3-wire SPI mode
1: AP interface uses 4-wire SPI mode (default)
Reserved
Page 92 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
15.18
INTF_CONFIG5
Name: INTF_CONFIG5
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:3 -
2:1
0
15.19
PIN9_FUNCTION
-
FUNCTION
Reserved
Selects among the following functionalities for pin 9
00: INT2
01: FSYNC
10: CLKIN
11: Reserved
Reserved
INTF_CONFIG6
Name: INTF_CONFIG6
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x5F
Clock Domain: SCLK_UI
BIT NAME
7:5 4
I3C_EN
3
I3C_IBI_BYTE_EN
2
I3C_IBI_EN
1
I3C_DDR_EN
0
I3C_SDR_EN
FUNCTION
Reserved
0: I3CSM slave not enabled
1: I3CSM slave enabled
0: I3CSM IBI payload function not enabled
1: I3CSM IBI payload function enabled
0: I3CSM IBI function not enabled
1: I3CSM IBI function enabled
0: I3CSM DDR mode not enabled
1: I3CSM DDR mode enabled
0: I3CSM SDR mode not enabled
1: I3CSM SDR mode enabled
Page 93 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
16 USER BANK 2 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 2.
16.1
ACCEL_CONFIG_STATIC2
Name: ACCEL_CONFIG_STATIC2
Address: 03 (03h)
Serial IF: R/W
Reset value: 0x30
Clock Domain: SCLK_UI
BIT NAME
7
6:1
0
16.2
ACCEL_AAF_DELT
ACCEL_AAF_DIS
ACCEL_CONFIG_STATIC3
Name: ACCEL_CONFIG_STATIC3
Address: 04 (04h)
Serial IF: R/W
Reset value: 0x40
Clock Domain: SCLK_UI
BIT NAME
7:0
16.3
ACCEL_AAF_DELTSQR[7:0]
FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
ACCEL_CONFIG_STATIC4
Name: ACCEL_CONFIG_STATIC4
Address: 05 (05h)
Serial IF: R/W
Reset value: 0x62
Clock Domain: SCLK_UI
BIT NAME
7:4
ACCEL_AAF_BITSHIFT
3:0
ACCEL_AAF_DELTSQR[11:8]
16.4
FUNCTION
Reserved
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
0: Enable accelerometer anti-aliasing filter (default)
1: Disable accelerometer anti-aliasing filter
FUNCTION
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
Controls bandwidth of the accelerometer anti-alias filter
See section 5.2 for details
XA_ST_DATA
Name: XA_ST_DATA
Address: 59 (3Bh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 XA_ST_DATA
X-accel self-test data
Page 94 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
16.5
YA_ST_DATA
Name: YA_ST_DATA
Address: 60 (3Ch)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 YA_ST_DATA
Y-accel self-test data
16.6
ZA_ST_DATA
Name: ZA_ST_DATA
Address: 61 (3Dh)
Serial IF: R/W
Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests)
Clock Domain: SCLK_UI
BIT NAME
FUNCTION
7:0 ZA_ST_DATA
Z-accel self-test data
Page 95 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
17 USER BANK 4 REGISTER MAP – DESCRIPTIONS
This section describes the function and contents of each register within USR Bank 4.
17.1
APEX_CONFIG1
Name: APEX_CONFIG1
Address: 64 (40h)
Serial IF: R/W
Reset value: 0xA2
Clock Domain: SCLK_UI
BIT NAME
7:4
LOW_ENERGY_AMP_TH_SEL
3:0
DMP_POWER_SAVE_TIME_S
EL
FUNCTION
Pedometer Low Energy mode amplitude threshold selection
Use default value 1010b
When the DMP is in power save mode, it is awakened by the WOM and will
wait for a certain duration before going back to sleep. This bitfield
configures this duration.
0000: 0 seconds
0001: 4 seconds
0010: 8 seconds
0011: 12 seconds
0100: 16 seconds
0101: 20 seconds
0110: 24 seconds
0111: 28 seconds
1000: 32 seconds
1001: 36 seconds
1010: 40 seconds
1011: 44 seconds
1100: 48 seconds
1101: 52 seconds
1110: 56 seconds
1111: 60 seconds
Page 96 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
17.2
APEX_CONFIG2
Name: APEX_CONFIG2
Address: 65 (41h)
Serial IF: R/W
Reset value: 0x85
Clock Domain: SCLK_UI
BIT NAME
7:4
PED_AMP_TH_SEL
3:0
PED_STEP_CNT_TH_SEL
FUNCTION
Pedometer amplitude threshold selection
Use default value 1000b
Pedometer step count detection window
Use default value 0101b
0000: 0 steps
0001: 1 step
0010: 2 steps
0011: 3 steps
0100: 4 steps
0101: 5 steps (default)
0110: 6 steps
0111: 7 steps
1000: 8 steps
1001: 9 steps
1010: 10 steps
1011: 11 steps
1100: 12 steps
1101: 13 steps
1110: 14 steps
1111: 15 steps
Page 97 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
17.3
APEX_CONFIG3
Name: APEX_CONFIG3
Address: 66 (42h)
Serial IF: R/W
Reset value: 0x51
Clock Domain: SCLK_UI
BIT NAME
7:5
PED_STEP_DET_TH_SEL
4:2
PED_SB_TIMER_TH_SEL
1:0
PED_HI_EN_TH_SEL
FUNCTION
Pedometer step detection threshold selection
Use default value 010b
000: 0 steps
001: 1 step
010: 2 steps (default)
011: 3 steps
100: 4 steps
101: 5 steps
110: 6 steps
111: 7 steps
Pedometer step buffer timer threshold selection
Use default value 100b
000: 0 samples
001: 1 sample
010: 2 samples
011: 3 samples
100: 4 samples (default)
101: 5 samples
110: 6 samples
111: 7 samples
Pedometer high energy threshold selection
Use default value 01b
Page 98 of 109
Document Number: DS-000347
Revision: 1.2
ICM-42688-P
17.4
APEX_CONFIG4
Name: APEX_CONFIG4
Address: 67 (43h)
Serial IF: R/W
Reset value: 0xA4
Clock Domain: SCLK_UI
BIT NAME
7:6
TILT_WAIT_TIME_SEL
5:3
SLEEP_TIME_OUT
2:0
-
17.5
APEX_CONFIG5
Name: APEX_CONFIG5
Address: 68 (44h)
Serial IF: R/W
Reset value: 0x8C
Clock Domain: SCLK_UI
BIT NAME
7:3 -
2:0
FUNCTION
Configures duration of delay after tilt is detected before interrupt is
triggered
00: 0s
01: 2s
10: 4s (default)
11: 6s
Configures the time out for sleep detection, for Raise to Wake/Sleep
feature
000: 1.28sec
001: 2.56sec
010: 3.84sec
011: 5.12sec
100: 6.40sec
101: 7.68sec
110: 8.96sec
111: 10.24sec
Reserved
MOUNTING_MATRIX
FUNCTION
Reserved
Defines mounting matrix, chip to device frame
000: [ 1 0 0; 0 1 0; 0 0 1]
001: [ 1 0 0; 0 -1 0; 0 0 -1]
010: [-1 0 0; 0 1 0; 0 0 -1]
011: [-1 0 0; 0 -1 0; 0 0 1]
100: [ 0 1 0; 1 0 0; 0 0 -1]
101: [ 0 1 0; -1 0 0; 0 0 1]
110: [ 0 -1 0; 1 0 0; 0 0 1]
111: [ 0 -1 0; -1 0 0; 0 0 -1]
Page 99 of 109
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Revision: 1.2
ICM-42688-P
17.6
APEX_CONFIG6
Name: APEX_CONFIG6
Address: 69 (45h)
Serial IF: R/W
Reset value: 0x5C
Clock Domain: SCLK_UI
BIT NAME
7:3 -
2:0
17.7
SLEEP_GESTURE_DELAY
APEX_CONFIG7
Name: APEX_CONFIG7
Address: 70 (46h)
Serial IF: R/W
Reset value: 0x45
Clock Domain: SCLK_UI
BIT NAME
7:2
TAP_MIN_JERK_THR
1:0
TAP_MAX_PEAK_TOL
17.8
FUNCTION
Reserved
Configures detection window for sleep gesture detection
000: 0.32sec
001: 0.64sec
010: 0.96sec
011: 1.28sec
100: 1.60sec
101: 1.92sec
110: 2.24sec
111: 2.56sec
FUNCTION
Tap Detection minimum jerk threshold
Use default value 010001b
Tap Detection maximum peak tolerance
Use default value 01b
APEX_CONFIG8
Name: APEX_CONFIG8
Address: 71 (47h)
Serial IF: R/W
Reset value: 0x5B
Clock Domain: SCLK_UI
BIT NAME
7
6:5
TAP_TMAX
4:3
TAP_TAVG
2:0
TAP_TMIN
FUNCTION
Reserved
Tap measurement window (number of samples)
Use default value 01b
Tap energy measurement window (number of samples)
Use default value 01b
Single tap window (number of samples)
Use default value 011b
Page 100 of 109
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Revision: 1.2
ICM-42688-P
17.9
APEX_CONFIG9
Name: APEX_CONFIG9
Address: 72 (48h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:1 0
17.10
SENSITIVITY_MODE
ACCEL_WOM_X_THR
Name: ACCEL_WOM_X_THR
Address: 74 (4Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
17.11
WOM_X_TH
17.12
WOM_Y_TH
FUNCTION
Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg
ACCEL_WOM_Z_THR
Name: ACCEL_WOM_Z_THR
Address: 76 (4Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
FUNCTION
Threshold value for the Wake on Motion Interrupt for X-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg
ACCEL_WOM_Y_THR
Name: ACCEL_WOM_Y_THR
Address: 75 (4Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
FUNCTION
Reserved
0: Low power mode at accelerometer ODR 25Hz; High performance mode
at accelerometer ODR ≥ 50Hz
1: Low power and slow walk mode at accelerometer ODR 25Hz; Slow walk
mode at accelerometer ODR ≥ 50Hz
WOM_Z_TH
FUNCTION
Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer
WoM thresholds are expressed in fixed “mg” independent of the selected
Range [0g : 1g]; Resolution 1g/256=~3.9mg
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17.13
INT_SOURCE6
Name: INT_SOURCE6
Address: 77 (4Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
STEP_DET_INT1_EN
4
STEP_CNT_OFL_INT1_EN
3
TILT_DET_INT1_EN
2
WAKE_DET_INT1_EN
1
SLEEP_DET_INT1_EN
0
TAP_DET_INT1_EN
17.14
FUNCTION
Reserved
0: Step detect interrupt not routed to INT1
1: Step detect interrupt routed to INT1
0: Step count overflow interrupt not routed to INT1
1: Step count overflow interrupt routed to INT1
0: Tilt detect interrupt not routed to INT1
1: Tile detect interrupt routed to INT1
0: Wake detect interrupt not routed to INT1
1: Wake detect interrupt routed to INT1
0: Sleep detect interrupt not routed to INT1
1: Sleep detect interrupt routed to INT1
0: Tap detect interrupt not routed to INT1
1: Tap detect interrupt routed to INT1
INT_SOURCE7
Name: INT_SOURCE7
Address: 78 (4Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
STEP_DET_INT2_EN
4
STEP_CNT_OFL_INT2_EN
3
TILT_DET_INT2_EN
2
WAKE_DET_INT2_EN
1
SLEEP_DET_INT2_EN
0
TAP_DET_INT2_EN
FUNCTION
Reserved
0: Step detect interrupt not routed to INT2
1: Step detect interrupt routed to INT2
0: Step count overflow interrupt not routed to INT2
1: Step count overflow interrupt routed to INT2
0: Tilt detect interrupt not routed to INT2
1: Tile detect interrupt routed to INT2
0: Wake detect interrupt not routed to INT2
1: Wake detect interrupt routed to INT2
0: Sleep detect interrupt not routed to INT2
1: Sleep detect interrupt routed to INT2
0: Tap detect interrupt not routed to INT2
1: Tap detect interrupt routed to INT2
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17.15
INT_SOURCE8
Name: INT_SOURCE8
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
FSYNC_IBI_EN
4
PLL_RDY_IBI_EN
3
UI_DRDY_IBI_EN
2
FIFO_THS_IBI_EN
1
FIFO_FULL_IBI_EN
0
AGC_RDY_IBI_EN
17.16
FUNCTION
Reserved
0: FSYNC interrupt not routed to IBI
1: FSYNC interrupt routed to IBI
0: PLL ready interrupt not routed to IBI
1: PLL ready interrupt routed to IBI
0: UI data ready interrupt not routed to IBI
1: UI data ready interrupt routed to IBI
0: FIFO threshold interrupt not routed to IBI
1: FIFO threshold interrupt routed to IBI
0: FIFO full interrupt not routed to IBI
1: FIFO full interrupt routed to IBI
0: AGC ready interrupt not routed to IBI
1: AGC ready interrupt routed to IBI
INT_SOURCE9
Name: INT_SOURCE9
Address: 80 (50h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
I3C_PROTOCOL_ERROR_IBI
7
_EN
6:5 4
SMD_IBI_EN
3
WOM_Z_IBI_EN
2
WOM_Y_IBI_EN
1
WOM_X_IBI_EN
0
-
FUNCTION
0: I3CSM protocol error interrupt not routed to IBI
1: I3CSM protocol error interrupt routed to IBI
Reserved
0: SMD interrupt not routed to IBI
1: SMD interrupt routed to IBI
0: Z-axis WOM interrupt not routed to IBI
1: Z-axis WOM interrupt routed to IBI
0: Y-axis WOM interrupt not routed to IBI
1: Y-axis WOM interrupt routed to IBI
0: X-axis WOM interrupt not routed to IBI
1: X-axis WOM interrupt routed to IBI
Reserved
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17.17
INT_SOURCE10
Name: INT_SOURCE10
Address: 81 (51h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:6 5
STEP_DET_IBI_EN
4
STEP_CNT_OFL_IBI_EN
3
TILT_DET_IBI_EN
2
WAKE_DET_IBI_EN
1
SLEEP_DET_IBI_EN
0
TAP_DET_IBI_EN
17.18
OFFSET_USER0
Name: OFFSET_USER0
Address: 119 (77h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
17.19
FUNCTION
Reserved
0: Step detect interrupt not routed to IBI
1: Step detect interrupt routed to IBI
0: Step count overflow interrupt not routed to IBI
1: Step count overflow interrupt routed to IBI
0: Tilt detect interrupt not routed to IBI
1: Tile detect interrupt routed to IBI
0: Wake detect interrupt not routed to IBI
1: Wake detect interrupt routed to IBI
0: Sleep detect interrupt not routed to IBI
1: Sleep detect interrupt routed to IBI
0: Tap detect interrupt not routed to IBI
1: Tap detect interrupt routed to IBI
GYRO_X_OFFUSER[7:0]
FUNCTION
Lower bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
OFFSET_USER1
Name: OFFSET_USER1
Address: 120 (78h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4
GYRO_Y_OFFUSER[11:8]
3:0
GYRO_X_OFFUSER[11:8]
FUNCTION
Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
Upper bits of X-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
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17.20
OFFSET_USER2
Name: OFFSET_USER2
Address: 121 (79h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
17.21
GYRO_Y_OFFUSER[7:0]
OFFSET_USER3
Name: OFFSET_USER3
Address: 122 (7Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
17.22
GYRO_Z_OFFUSER[7:0]
7:4
ACCEL_X_OFFUSER[11:8]
3:0
GYRO_Z_OFFUSER[11:8]
FUNCTION
Upper bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
OFFSET_USER5
Name: OFFSET_USER5
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
FUNCTION
Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
OFFSET_USER4
Name: OFFSET_USER4
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
17.23
FUNCTION
Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps,
resolution is 1/32 dps.
ACCEL_X_OFFUSER[7:0]
FUNCTION
Lower bits of X-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
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17.24
OFFSET_USER6
Name: OFFSET_USER6
Address: 125 (7Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
17.25
ACCEL_Y_OFFUSER[7:0]
OFFSET_USER7
Name: OFFSET_USER7
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:4
ACCEL_Z_OFFUSER[11:8]
3:0
ACCEL_Y_OFFUSER[11:8]
17.26
FUNCTION
Upper bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
Upper bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
OFFSET_USER8
Name: OFFSET_USER8
Address: 127 (7Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLK_UI
BIT NAME
7:0
FUNCTION
Lower bits of Y-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
ACCEL_Z_OFFUSER[7:0]
FUNCTION
Lower bits of Z-accel offset programmed by user. Max value is ±1g,
resolution is 0.5mg.
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18 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
• Manufacturing Recommendations
o Assembly Guidelines and Recommendations
o PCB Design Guidelines and Recommendations
o MEMS Handling Instructions
o ESD Considerations
o Reflow Specification
o Storage Specifications
o Package Marking Specification
o Tape & Reel Specification
o Reel & Pizza Box Label
o Packaging
o Representative Shipping Carton Label
• Compliance
o Environmental Compliance
o DRC Compliance
o Compliance Declaration Disclaimer
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19 DOCUMENT INFORMATION
19.1
REVISION HISTORY
Revision Date
Revision
Description
11/18/2019
1.0
Initial Release
03/02/2020
1.1
Added product overview page (page 1); Updated Conditions in tables 1 and 2;
Updated SPI timing characteristics specs (tables 6, 7); Updated SPI interface
description (section 9.6)
04/19/2020
1.2
Updated specification notes (tables 1, 2, 3, 4); Updated absolute maximum ratings
(table 8)
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This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use,
or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves
the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes
no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any
claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to,
claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any
patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the
property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or
mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2020 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense
logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective
companies with which they are associated.
©2020 InvenSense. All rights reserved.
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