FS1406 µPOL™
DATASHEET
6A Rated µPOL™ Buck Regulator with Integrated Inductor
and Digital Power System Management
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
µPOL™ package with output inductor included
Small size: 3.3mm x 3.3mm x 1.5mm
Continuous 6A load capability
Plug and play: no external compensation required
Programmable operation using the I2C serial bus
Wide input voltage range: 4.5–16V
Adjustable output voltage: 0.6–2.64V,
±0.5% initial accuracy
Enabled input, programmable under-voltage
lock-out (UVLO) circuit
Open-drain power-good indicator
Built-in protection features
Operating temperature from -40°C to +125°C
Lead-free and halogen-free
Compliant with EU Directives REACH and RoHS 6
Applications
•
•
•
•
•
•
•
Storage applications
Telecom and networking applications
Industrial applications
Server applications
Distributed point-of-load power architectures
Computing peripheral voltage regulation
General DC-DC conversion
Description
The FS1406 is an easy-to-use, fully integrated and
highly efficient micro-point-of-load (µPOL™) voltage
regulator. The on-chip pulse-width modulation
(PWM) controller and integrated MOSFETs, plus
incorporated inductor and capacitors, result in an
extremely compact and accurate regulator. The
low-profile package is suitable for automated
assembly using standard surface-mount equipment.
Developed by a cross-functional engineering team, the
design exemplifies best practice and uses class-leading
technologies. From early in the integrated circuit
design phase, designers worked with application and
packaging engineers to select compatible
technologies and implement them in ways that
reduce compromise. The ability to program aspects
of the FS1406’s operation using the Inter-Integrated
Circuit (I2C) protocol is unique in this class of product.
Developing and optimizing all of these elements
together has yielded the smallest, most efficient
and fully featured 6A µPOL™ currently available.
The built-in protection features include pre-biased
start-up, soft-start protection, over-voltage protection,
thermally compensated over-current protection with
hiccup mode, thermal shut-down with auto-recovery.
Page 1
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Pin configuration
Figure 1
Pin layout (top view)
Figure 2
Pin layout (bottom view)
Pin functions
Pin
Name
Number
1
SDA
2
PG
3
En
4
5
6
7
SCL
VOS
ADDR
VOUT
8, 16
PGnd
9
AGnd
10
VCC
11
VIN
12,13,14,
PVIN
17
15
VSW
Page 2
Description
I2C Data Serial Input/Output line. Pull up to bus voltage with a 4.99kΩ resistor. If unused tie to AGnd.
Power Good status. Open drain of an internal MOSFET.
Pull up to VCC – pin 10 or an external bias voltage (Figure 7) – with a 49.9kΩ resistor.
Enable. Switches the FS1406 on and off. Can be used with two external resistors to set an external
UVLO (Figure 6).
I2C Clock line. Pull up to bus voltage with a 4.99kΩ resistor. If unused, tie to AGnd.
VOUT sense pin. Connect directly to the regulator output (VOUT).
Address. Connect to AGnd through a resistor to program FS1406 address (page 16).
Regulator output voltage. Place output capacitors between this pin and PGnd (pin 8).
Power ground. Serves as a separate ground for the MOSFETs. Connect to the power ground plane in
the application.
Signal ground. Serves as the ground for the internal reference and control circuitry.
Supply voltage. May be an input bias for an external VCC voltage or the output of the internal LDO
regulator.
Input voltage. Input for the internal LDO regulator.
Power input voltage. Input for the MOSFETs.
Test point for internal VSW. Connect to an isolated pad on the PCB.
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Block diagram
Figure 3
FS1406 µPOL™
Typical applications
2.5–16V
5V
Figure 4
Page 3
Single supply applications circuit
Figure 5
PVIN
VIN
SDA
SCL
ADDR
PG
En
VOUT
VOS
VOUT
PGnd
AGnd
Dual supply applications circuit
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Absolute maximum ratings
Warning: Stresses beyond those shown may cause permanent damage to the FS1406.
Note:
Functional operation of the FS1406 is not implied under these or any other conditions beyond those stated in
the FS1406 specification.
Reference
Range
PVIN, VIN, En to PGnd
VCC to PGnd
VOS to AGnd
PG to AGnd
PGnd to AGnd
ESD Classification
Moisture Sensitivity Level
-0.3V to 18V (Note 1, page 9)
-0.3V to 6V (Note 2, page 9)
-0.3V to VCC (Note 2, page 9)
-0.3V to VCC (Note 2, page 9)
-0.3V to +0.3V
2kV (HBM JESD22-A114)
MSL 3 (JEDEC J-STD-020D)
Thermal Information
Range
Junction-to-Ambient Thermal Resistance ƟJA
22.6°C/W
Junction to PCB Thermal Resistance ƟJ-PCB
2.36°C/W
Storage Temperature Range
-55°C to 150°C
Junction Temperature Range
-40°C to 150°C
Note:
ƟJA : FS1406 evaluation board and JEDEC specifications JESD 51-2A
ƟJ-c (bottom) : JEDEC specification JESD 51-8
Page 4
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Order information
Package details
The FS1406 uses a µPOL™ 3.3 mm x 3.3 mm package delivered in tape-and-reel format (Figure 33), with either
250 or 4000 devices on a reel.
Standard part numbers
Output voltages of 0.6V to 2.64V are available.
VOUT
0.60
0.70
0.75
0.80
0.90
1.00
1.05
1.10
1.20
1.80
2.50
2.64
Page 5
Part numbers
250 devices on a reel
4000 devices on a reel
FS1406-0600-AS
FS1406-0600-AL
FS1406-0700-AS
FS1406-0700-AL
FS1406-0750-AS
FS1406-0750-AL
FS1406-0800-AS
FS1406-0800-AL
FS1406-0900-AS
FS1406-0900-AL
FS1406-1000-AS
FS1406-1000-AL
FS1406-1050-AS
FS1406-1050-AL
FS1406-1100-AS
FS1406-1100-AL
FS1406-1200-AS
FS1406-1200-AL
FS1406-1800-AS
FS1406-1800-AL
FS1406-2500-AS
FS1406-2500-AL
FS1406-2640-AS
FS1406-2640-AL
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Recommended operating conditions
Definition
Symbol
Min
Max
Input Voltage Range with External VCC (Note 3, Note 5)
PVIN
2.5
16
Input Voltage Range with Internal LDO (Note 4, Note 5)
PVIN, VIN
4.5
16
Supply Voltage Range (Note 2)
VCC
4.5
5.5
Output Voltage Range
VO
0.6
2.64
Continuous Output Current Range
Operating Junction Temperature
IO
TJ
0
-40
6
125
Units
V
A
°C
Electrical characteristics
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 4.5V < PVIN = VIN < 16V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol
Conditions
Supply Current
VIN Supply Current (Standby)
IIN (STANDBY)
Enable low
VIN Supply Current (Static)
IIN (STATIC)
No switching, En = 2V
En high, VIN = 12V, VOUT = 1.8V,
VIN Supply Current (Dynamic)
IIN (DYN)
FSW=2MHz
Soft-Start
Soft-Start Rate
SSRATE (default)
(Note 7)
Output Voltage
VOUT (default)
Output Voltage Range
VOUT ≤ 1.8V
V (resolution)
VOUT > 1.8V
TJ = 25°C, PVIN = 12V, VOUT = 1.8V
(Note 6)
25°C < TJ < 125°C, PVIN = 12V,
Accuracy
0.6V ≤ VOUT < 1.0V (Note 6)
25°C < TJ < 125°C, PVIN = 12V,
1.0V ≤ VOUT ≤ 2.64V (Note 6)
On-Time Timer Control
On Time
TON
PVIN = 12V, VOUT = 1.8V, FSW=2MHz
Minimum On-Time
TON(MIN)
(Note 7)
Minimum Off-Time
TOFF(MIN)
PVIN = 1.8V, VOUT = 1.8V, FSW=2MHz
Internal Low Drop-Out (LDO) Regulator
5.5V < VIN = 16V, 0 – 20mA
LDO Regulator Output Voltage
VCC
4.5V 2 V,
(open-drain or opencollector) at 2mA sink
current; VDD ≤ 2 V,
VOL = 0.4 V,
VOL = 0.6 V
Fast-mode
Fast-mode Plus
Min
Max
Min
Max
1.8
−0.5
0.7VBUS
0.05VBUS
5.5
0.3VBUS
1.8
−0.5
0.7VBUS
0.05VBUS
5.5
0.3VBUS
0
0.4
0
0.4
0
0.2VBUS
0
0.2VBUS
3
6
-
3
6
-
Unit
V
mA
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over: 4.5V < PVIN = VIN < 16V, 0°C < T < 125°C
Typical values are specified at TA = 25°C
Parameter
Symbol Conditions
(Note 7 for all
parameters)
I2C parameters
Output fall time
Page 8
Fast-mode Plus
Min
Max
Min
Max
20 × (VBUS/5.5 V)
250
20 × (VBUS/5.5
V)
125
TSP
0
50
0
50
II
CI
FSCL
−10
0
10
10
400
−10
0
10
10
1000
0.6
-
0.26
-
TLOW
THIGH
1.3
0.6
-
0.5
0.26
-
TSU;STA
0.6
-
0.26
-
THD;DAT I2C-bus devices
TSU;DAT
0
100
-
0
50
-
TR
20
300
-
120
TF
20 × (VDD/5.5 V)
300
20 × (VDD/5.5 V)
120
TSU;STO
0.6
-
0.26
-
TOF
Pulse width of spikes that
must be suppressed by the
input filter
Input current each I/O pin
Capacitance for each I/O pin
SCL clock frequency
Hold time (repeated) START
condition
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated
START condition
Data hold time
Data set-up time
Rise time of SDA and SCL
signals
Fall time of SDA and SCL
signals
Set-up time for STOP
condition
Bus free time between a
STOP and START condition
Capacitive load for each bus
line
Data valid time
Data valid acknowledge time
Noise margin at the LOW
level
Noise margin at the HIGH
level
SDA timeout
Fast-mode
From VIHmin to VILmax
Unit
ns
THD;STA
After this time, the first
clock pulse is generated
μA
pF
kHz
μs
ns
μs
TBUF
1.3
-
0.5
-
CB
-
400
-
550
pF
TVD;DAT
TVD;ACK
-
0.9
0.9
-
0.45
0.45
μs
0.1VDD
-
0.1VDD
-
0.2VDD
-
0.2VDD
-
VNL
VNH
TTO
For each connected
device, including
hysteresis
V
200
200
μs
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Notes
1 PGnd pin and AGnd pin are connected together
2 Must not exceed 6V
3 VIN is connected to VCC to bypass the internal Low Drop-Out (LDO) regulator
4 VIN is connected to PVIN (for single-rail applications with PVIN=VIN=4.5V-5.5V)
5 Maximum switch node voltage should not exceed 22V
6 Hot and cold temperature performance is assured by correlation using
statistical quality control, but not tested in production; performance at 25°C is
tested and guaranteed in production environment
7 Guaranteed by design but not tested in production
Page 9
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Temperature characteristics
Output Voltage
VIN Supply Current (Dynamic)
Enable Start Threshold
Enable Stop Threshold
VCC Start Threshold
VCC Stop Threshold
Page 10
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
On Time
Switching Frequency
Soft-Start Rate
Current Limit Threshold
Page 11
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Efficiency characteristics
Typical efficiency and power loss at PVIN = 12V
PVIN = 12V, Internal LDO used, IO = 0A-6A, room temperature, no air flow, all losses included
Page 12
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Typical efficiency and power loss at PVIN = 5V
PVIN = VIN = VCC = 5V, IO = 0A-6A, room temperature, no air flow, all losses included
Page 13
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Typical load regulation
PVIN = 12V, internal LDO used, IO = 0A-6A, room temperature, no air flow
PVIN = VIN = VCC = 5V, IO = 0A-6A, room temperature, no air flow, all losses included
Page 14
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Applications information
Overview
The FS1406 is an easy-to-use, fully integrated and
highly efficient DC/DC regulator. Aspects of its
operation, including output voltage and system
optimization parameters, can be programmed
using the I2C protocol. It uses a proprietary
modulator to deliver fast transient responses. The
modulator has internal stability compensation so
that it can be used in a wide range of applications,
with various types of output capacitors, without
loop stability issues.
The I2C bus may be pulled up either to VCC or to a
system I2C bus voltage. The FS1406 offers two
ranges for the I2C bus voltage, defined by the user
register bit Bus_voltage_sel.
Register
0x1A
Bits
[1]
Name/Description
Bus_voltage_sel
0:1.8–2.5V, 1: 3.3–5V
Bias voltage
The FS1406 has an integrated Low Drop-Out (LDO)
regulator, providing the DC bias voltage for the
internal circuitry. The typical LDO regulator output
voltage is 5.2V. For internally biased single-rail
operation, the VIN pin should be connected to the
PVIN pin (Figure 6). If an external bias voltage is
used, the VIN pin should be connected to the VCC
pin to bypass the internal LDO regulator (Figure 7).
Figure 6
Single supply configuration: internal LDO
regulator, adjustable PVIN_UVLO
Figure 7
Using an external bias voltage
The supply voltage (internal or external) rises with
VIN and does not need to be enabled using the En
pin. Consequently, I2C communication can begin as
soon as:
•
VCC_UVLO start threshold is exceeded
•
Memory contents are loaded
•
Initialization is complete
•
Address offset is read
Note:
Page 15
Until initialization is complete, a small
leakage current (≈3.4µA) will flow from the
device into the output. This may significantly
pre-bias the output voltage in applications
with long VIN/VCC rise times. To prevent this,
a small load capable of sinking 3.4µA should
be connected in such applications.
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
I2C base address and offsets
The FS1406 has a user register called
Base_address[7:0] stored in memory that sets its
base I2C address. The default base address is 0x08.
An offset of 0-3 is then defined by connecting the
ADDR pin to the AGnd pin either directly or
through a resistor. An address detector reads the
resistance of the connection at startup and uses it
to set the offset, which is added to the base I2C
address to set the address at which the I2C master
device will communicate with the FS1406.
To select offsets of 0 to 3, connect the pins as follows:
•
•
•
•
0
+1
+2
+3
–
–
–
–
0Ω (short ADDR to AGnd)
10kΩ
20kΩ
>30.1kΩ
Figure 8
Soft-start and target output voltage
The FS1406 has an internal digital soft-start circuit
to control output voltage rise-time and limit current
surge at start-up. When VCC exceeds its start
threshold (VCC_UVLO(START)), the FS1406 exits reset
mode; this initiates loading of the contents of the
non-volatile memory into the working registers and
calculates the address offset as described above.
Once initialization is complete and the Enable (En)
pin has been asserted (Figure 8), the internal
reference soft-starts to the target output voltage
at the rate defined by the user register bit SS_rate.
Register
0x14
Bits
[3]
Name/Description
SS_rate
0:0.5mV/µs (default),
1: 1 mV/µs
Theoretical operational waveforms
during soft-start
Register
0x12
0x13
Bits
[0]
[7:0]
Name/Description
Vout_high_byte
Vout_low_byte
VOUT is set in increments of 5mV for target voltages
up to 1.8V, and 10mV increments for target output
voltages from 1.8V to 2.64V. Use the following
equation to calculate the VOUT code to enter into
Vout_high_byte and Vout_low_byte[7:0]:
𝑉𝑜𝑢𝑡𝑐𝑜𝑑𝑒 =
0.4 × 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
0.005
𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛
𝑉𝑜𝑢𝑡𝑡𝑎𝑟𝑔𝑒𝑡 −
All voltages and resolutions are in Volts.
For example:
To set VOUT =1V (≤1.8V, resolution of 5mV):
During initial start-up, the FS1406 operates with a
minimum of high-drive (HDrv) pulses until the
output voltage increases (see Switching frequency
and minimum values for on-time, off-time on page
18). On-time is increased until VOUT reaches the
target value defined by the user register bit Vout_
high_byte and user register Vout_low_byte[7:0].
Page 16
0.4 × 0.005
0.005
𝑉𝑜𝑢𝑡𝑐𝑜𝑑𝑒 =
= 120
0.005
120 is 078 in hexadecimal, therefore:
1−
Set Vout_high_byte to 0
Set Vout_low_byte to 78 or (01111000)b
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
To set VOUT =2.5V (>1.8V, resolution of10mV):
0.4 × 0.01
0.005 = 170
𝑉𝑜𝑢𝑡𝑐𝑜𝑑𝑒 =
0.01
170 is 0AA in hexadecimal, therefore:
2.5 −
Set Vout_high_byte to 0
Set Vout_low_byte to AA or (10101010)b
Over-current protection (OCP) and over-voltage
protection (OVP) is enabled during soft-start to
protect the FS1406 from short circuits and excess
voltages respectively.
For maximum system accuracy, the recommended
way to set the output voltage is by programming
the user registers with the appropriate code. For
optimum performance when using this approach,
the change in output voltage should not exceed
±20% of the pre-set default output voltage.
However, another option is to combine an FS1406
pre-programmed to 0.6V with a feedback resistor
divider (Figure 9). This gives system designers the
flexibility to design all the power rails in the system
across the output voltage range from 0.6V to 2.5V
using a single part, at the expense of a worst-case
error of no more than an additional -1%.
Figure 9
Page 17
Setting the output voltage with an
external resistor divider
The equation below describes the appropriate
resistor divider selection to set the output voltage
using a FS1406 programmed to 0.6V.
𝑅𝑇𝑂𝑃
𝑅𝐵𝑂𝑇𝑇𝑂𝑀
= 1.745𝑉𝑂𝑈𝑇 − 1.047
It is recommended that system designers place a
capacitor of 4.7pF to 47pF in parallel with RTOP, for
which a value of 40.2kΩ is recommended. The
recommended value for RBOTTOM depends on the
output voltage, as shown in the following table. If
RBOTTOM > 100kΩ, it is recommended to use a lower
RTOP such as 4.02kΩ, with the compensation
capacitor in the 47pF to 470pF range.
VOUT (V)
0.65
0.7
0.72
0.75
0.78
0.8
0.85
0.88
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
RTOP /RBOTTOM
0.08725
0.1745
0.2094
0.26175
0.3141
0.349
0.4363
0.489
0.524
0.611
0.698
0.785
0.873
0.96
1.047
1.135
1.222
1.309
1.397
1.484
1.571
VOUT (V)
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
RTOP /RBOTTOM
1.658
1.745
1.833
1.92
2.008
2.095
2.182
2.27
2.357
2.445
2.532
2.619
2.706
2.794
2.881
2.968
3.056
3.143
3.222
3.318
For output voltages over 1.8V, the output current
and input voltage ranges are restricted by
minimum off-time (the shortest time for which the
FS1406 can be switched off). FS1406-2500 and
FS1406-2640 are recommended for 2.5V and 2.64V
applications respectively.
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Pre-biased start-up
The FS1406 can start up into a pre-charged output
smoothly, without causing oscillations and
disturbances of the output voltage. When it starts
up in this way, the Control and Synchronous
MOSFETs are forced off until the internal Soft-Start
(SS) signal exceeds the sensed output voltage at
the VOS pin. Only then is the first gate signal of the
Control MOSFET generated, followed by complementary turn on of the Synchronous MOSFET. The
Power Good (PG) function is not active until this
point.
Shut-down mechanisms
The FS1406 has two shut-down mechanisms:
•
•
Hard shut-down or decay according to load
Initiated by de-asserting the En pin.
Both drivers switch off and the digital-toanalog converter (DAC) and soft-start are
pulled down instantaneously.
Soft-Stop or controlled ramp down
Initiated by setting user register bit
SoftStopEnable to 1 and user register bit
SoftDisable to 1. The SS signal falls to 0 at the
same rate as it rises during start-up; the drivers
are disabled only when it reaches 0. The output
voltage then follows the SS signal down to 0.
The SoftDisable bit must not be toggled while
the part is enabled and switching. Instead, for
applications requiring soft-stop, this bit must
be set to 1 and, with the En pin asserted, the
SoftStopEnable bit must be toggled to softstart or soft-stop the device.
By default, both the SoftDisable bit and the
SoftStopEnable bit are 0, which means that
soft-stop operation is disabled by default.
Register
0x14
0x1C
Page 18
Bits
[2]
[3]
Name/Description
SoftStopEnable
SoftDisable
Switching frequency and minimum
values for on-time, off-time and PVIN
The switching frequency of the FS1406 depends on
the output voltage. For an output voltage of 1.8V,
the switching frequency is nominally 2MHz.
When the output voltage is set by programming
the user registers, the appropriate switching
frequency is also programmed at the factory.
When the output voltage is set using an external
resistor divider, the switching frequency
automatically adjusts to the appropriate value:
𝑉𝑂𝑈𝑇
0.6
Therefore, with either method, system designers
need not concern themselves with selecting the
switching frequency and have one fewer design
task to manage.
𝐹𝑠𝑤 = 650𝑘𝐻𝑧 ×
When input voltage is high relative to target
output voltage, the Control MOSFET is switched on
for shorter periods. The shortest period for which
it can reliably be switched on is defined by
minimum on-time (TON(MIN)). During start-up, when
the output voltage is very small, the FS1406
operates with minimum on-time.
When input voltage is low relative to target output
voltage, the Control MOSFET is switched on for
longer periods. The shortest period for which it can
be switched off is defined by minimum off-time
(TOFF(MIN)). The Synchronous MOSFET stays on
during this period and its current is detected for
over-current protection. This dictates the
minimum input voltage that can still allow the
device to regulate its output at the target voltage.
Figure 10 shows the minimum input voltage
required for some typical output voltages. This
curve assumes typical efficiency numbers; since it
is affected by efficiency, system designers should
validate the values in their own applications.
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Note:
VIN = VCC = 5V for PVIN < 4.2V
Figure 10 Minimum input voltage requirements
Figure 11 En pin used to monitor other rails
for sequencing purposes
Enable (En) pin
The Enable (En) pin has several functions:
•
•
•
•
It is used to switch the FS1406 on and off. It
has a precise threshold, which is internally
monitored by the UVLO circuit. If it is left
floating, an internal 1MΩ resistor pulls it down
to prevent the FS1406 being switched on
unintentionally.
It can be used to implement a precise input
voltage UVLO. The input of the En pin is
derived from the PVIN voltage by a set of
resistive dividers, REN1 and REN2 (Figure 6).
Users can program the UVLO threshold voltage
by selecting different ratios. This is a useful
feature that stops the FS1406 regulating when
PVIN is lower than the desired voltage.
It can be directly connected to PVIN without
external resistive dividers for some spaceconstrained designs. This is a useful feature for
standalone start-up, when no logic signal is
available to enable the FS1406.
It can be used to monitor other rails for a
specific power sequencing scheme (Figure 11).
Page 19
Figure 12 Start-up: PVIN, VIN and En pins tied together,
PG pin pulled up to an external supply
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
The OCP threshold is defined by the user register
bits OCSet.
Register
0x15
Bits
[2:0]
Name/Description
OCSet
2:8A (default), 1:6A, 0: 4A
The threshold is internally compensated so that it
remains almost constant at different ambient
temperatures.
Figure 13 Start-up: En pin asserted after PVIN and VIN,
When the current exceeds the OCP threshold, the
PG and SS signals are pulled low. The Synchronous
MOSFET remains on until the current falls to 0,
then the FS1406 enters hiccup mode (Figure 14).
Both the Control MOSFET and the Synchronous
MOSFET remain off for the hiccup-blanking time.
After this time, the FS1406 tries to restart. If an
over-current fault is still detected, the preceding
actions are repeated. The FS1406 remains in
hiccup mode until the over-current fault is
remedied.
PG pin pulled up to an external supply
For VOUT to start up as defined by the soft-start rate
requires correct sequencing:
•
•
PVIN must start up before VCC and/or Enable.
PVIN must ramp down only after VCC has
ramped down below its UVLO threshold
and/or Enable has been de-asserted.
Over-current protection (OCP)
Over-current protection (OCP) is provided by
sensing the current through the RDS(on) of the
Synchronous MOSFET. When this current exceeds
the OCP threshold, a fault condition is generated.
This method provides several benefits:
•
•
•
Figure 14 Illustration of OCP in hiccup mode
Provides accurate overcurrent protection
without reducing converter efficiency
(the current sensing is lossless)
Reduces cost by eliminating a current-sense
resistor
Reduces any layout-related noise issues.
Page 20
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Over-voltage protection (OVP)
Over-temperature protection (OTP)
Over-voltage protection (OVP) is provided by
sensing the voltage at the VOS pin. When VOS
exceeds the output OVP threshold for longer than
the output OVP delay (typically 5μs), a fault
condition is generated.
Temperature sensing is provided inside the
FS1406. The OTP threshold is defined by the user
register bits OT_Threshold.
Register
0x19
Bits
[1:0]
Name/Description
OT_Threshold
0:75°C
1: 85°C
2: 125°C
3: 145°C (default)
The OVP threshold is defined by the user register
bits OV_Threshold.
Register
0x17
Bits
[1:0]
Name/Description
OV_Threshold
0:105% of VOUT
1:110% of VOUT
2:115% of VOUT
3:120% of VOUT (default)
The Control MOSFET is switched off immediately
and the PG pin is pulled low. The Synchronous
MOSFET is switched on to discharge the output
capacitor.
The Control MOSFET remains latched off until reset
by cycling either VCC or En. The voltage at the VOS
pin falling below the output OVP threshold (with
5% hysteresis) does not switch on the Control
MOSFET but it does switch off the Synchronous
MOSFET to prevent build-up of negative current.
When the threshold is exceeded, thermal shutdown switches off both MOSFETs and resets the
internal soft-start, but the internal LDO regulator is
still in operation.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20°C hysteresis in the OTP threshold.
Power Good (PG)
Power Good (PG) behavior is defined by the user
register bits PGControl and PG_Threshold.
Register
0x18
Bits
[1:0]
0x14
[0]
Figure 15 shows a timing diagram for over-voltage
protection.
Name/Description
PG_Threshold
0:80% of VOUT
1: 85% of VOUT
2: 90% of VOUT (default)
3: 95% of VOUT
PG_Control
1:Threshold based (default)
0: DAC based
Figure 15 Illustration of latched OVP
Page 21
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
PG_Threshold bit
PGControl bit set to 0
The user register bit PG_Threshold defines the PG
threshold as a percentage of VOUT. Hysteresis of 5%
is applied to this, giving a lower threshold.
Figure 17 shows PG behavior in this situation.
When VOS rises above the upper threshold, the PG
signal is pulled high. When VOS drops below the
lower threshold, the PG signal is pulled low.
PGControl bit set to 1 (default)
Figure 16 shows PG behavior in this situation.
The behavior is the same at start-up and during
normal operation. The PG signal is asserted when:
•
•
•
En and VCC are both above their thresholds
No fault has occurred
(including over-current, over-voltage and
over-temperature)
VOUT is within the target range
(determined by continuously monitoring
whether VOS is above the PG threshold)
In normal operation, the PG signal behaves in the
same way as when the PGControl bit is 1.
At start-up, however, the PG signal is asserted after
soft-start is within 2% of target output voltage, not
when VOS exceeds the upper PG threshold.
For pre-biased start-up, the PG signal is not active
until the first gate signal of the Control MOSFET is
generated.
FS1406 also integrates an additional PMOS in
parallel to the NMOS internally connected to the
PG pin (Figure 3). This PMOS allows the PG signal
to stay at logic low, even if VCC is low and the PG
pin is pulled up to an external voltage not VCC
(Figure 12 and Figure 13).
Figure 17 PG signal when PGControl bit=0
Figure 16 PG signal when PGControl bit=1
Page 22
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Design example
Output voltage and output capacitor
Let us now consider a simple design example, using
the FS1406 for the following design parameters:
The FS1406 is supplied pre-programmed and
factory-trimmed in a closed loop to the target
voltage specified for the part number. As a result,
no external resistor divider is required and resistor
tolerances are eliminated from the error budget.
•
•
•
•
•
•
•
PVIN = VIN = 12V
VOUT = 1.8V
FSW = 2MHz
COUT = 2 x 22μF
CIN = 2 x 22μF
Ripple Voltage = ± 1% * VOUT
ΔVOUT(MAX) = ±3% * VOUT
(for 50% load transient)
The design requires minimal output capacitance to
meet the target output voltage ripple and target
maximum output voltage deviation under load
transient conditions.
For the FS1406, the minimum number of output
capacitors required to achieve target peak-to-peak
VOUT ripple is:
Input capacitor
The input capacitor selected for this design must:
•
•
Handle the peak and root mean square (RMS)
input currents required by the FS1406
Have low equivalent series resistance and
inductance (ESR and ESL) to reduce input
voltage ripple
MLCCs (multi-layer ceramic capacitors) are ideal.
Typically, in 0805 case size, they can handle 2A
RMS current with less than 5°C temperature rise.
For a buck converter operating at duty cycle D and
output current IO, the RMS value of the input
current is:
𝑉𝑂𝑈𝑇
𝑃𝑉𝐼𝑁
where:
•
•
•
•
•
•
•
𝐼𝑅𝑀𝑆 = 𝐼𝑜√𝐷(1 − 𝐷)
In this application, IO = 6A and 𝐷 =
(𝟏 − 𝑫)
𝑬𝑺𝑳 × 𝑭𝑺𝑾 × (𝟏 − 𝑫)𝟐
+ 𝑬𝑺𝑹(𝟏 − 𝑫) +
𝟖𝑪𝑭𝑺𝑾
𝑫
𝑵𝑴𝑰𝑵 = 𝟒. 𝟎𝟗 ×
∆𝑉𝑂𝑈𝑇𝑟𝑖𝑝𝑝𝑙𝑒(𝑝−𝑝)
= 0.15
Therefore, IRMS = 2.14A and we can select two 22μF
16V ceramic capacitors for the input capacitors
(C3216X5R1C226M160AB from TDK).
If the FS1406 is not located close to the 12V power
supply, a bulk capacitor (68–330μF) may be used in
addition to the ceramic capacitors.
NMIN = minimum number of output capacitors
D = duty cycle
C = equivalent capacitance of each output
capacitor
FSW = switching frequency
ESR = equivalent series resistance of each
output capacitor
ESL = equivalent series inductance of each
output capacitor
∆𝑉𝑂𝑈𝑇𝑟𝑖𝑝𝑝𝑙𝑒(𝑝−𝑝)
= target peak-to-peak VOUT ripple
This design uses C2012X5R0J226K125AB from TDK;
this is a 22μF MLCC, 0805 case size, rated at 6.3V.
At 1.8V, accounting for DC bias and AC ripple
derating, it has an equivalent capacitance of 12μF
(C). Equivalent series resistance is 3mΩ (ESR) and
equivalent series inductance is 0.44nH (ESL).
Putting these parameters into the equation gives:
NMIN = 1.27
For VIN, which is the input to the LDO, it is
recommended to use a 1μF capacitor very close to
the pin. The VIN pin should be connected to PVIN
through a 2.7Ω resistor. Together, the 2.7Ω resistor
and 1μF capacitor filter noise on PVIN.
Page 23
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
To meet the maximum voltage deviation ΔVomax
under a ∆𝐼𝑜 load transient, the minimum required
number of output capacitors is:
transient. These waveforms show that the
selection of two 22μF capacitors meets the design
criteria.
𝟎. 𝟐𝟒𝟒 × ∆𝑰𝟐𝒐
∆𝑉𝑜𝑚𝑎𝑥 × 𝐹𝑠𝑤 × 𝐶
It should be noted that even in the absence of a
target VOUT ripple or target maximum voltage
deviation under load transient, at least one 22μF
capacitor is still required in order to ensure stable
operation without excessive jitter.
where:
•
•
•
•
∆𝐼𝑜 = load step
∆𝑉𝑂𝑈𝑇𝑚𝑎𝑥 = target maximum voltage deviation
𝐹𝑠𝑤 = switching frequency
C = equivalent capacitance of each output
capacitor
Again, using C = 12μF, it can be seen that the
minimum number of output capacitors required is
0.4.
In our design intended for space-constrained
applications,
therefore,
we
use
two
C2012X5R0J226K125AB capacitors.
It should be noted here that the calculation for the
minimum number of output capacitors under a
load transient makes some assumptions:
a) No ESR or ESL
b) Converter can saturate its duty cycle instantly
c) No latency
d) Step load (infinite slew rate)
Assumptions (a), (b) and (c) are liberal, whereas (d)
is conservative. Therefore, in a real application,
additional capacitance may be required to meet
transient requirements and should be carefully
considered by the system designer.
The typical application waveforms in Figure 26 and
Figure 27 show the steady state VOUT ripple as well
as the voltage deviation in response to a 50% load
Page 24
Up to six 22μF capacitors may be used in the
design. If more capacitance is required, it is
recommended to use a capacitor with relatively
high ESR (>3mΩ).
Note:
The above discussion applies to designs that
use FS1406-1800 devices with VOUT tied to VOS
and no feedback divider. If an FS1406-0600 is
used to generate 1.8V, with a resistive
voltage divider between VOUT and VOS, the
feedforward capacitor in parallel with the top
resistor will allow greater flexibility in choice
of output capacitance.
Figure 18 shows the minimum required output
capacitance as a function of the output voltage.
For an output voltage of 1V, the minimum
capacitor requirement is dictated by the load
transient specifications (< ±3% VOUT). For output
voltages above 1V, the output voltage ripple
specification dominates (< ±1%).
VCC capacitor selection
FS1406 uses an on-package VCC capacitor to ensure
effective high-frequency bypassing. However,
especially for applications that use an external VCC
supply, it is recommended that system designers
place a 2.2μF/0603/X7R/10V capacitor on the
application board as close as possible to the VCC
pin.
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 18 Minimum output capacitance
Figure 19 Application circuit for a single supply, PVIN=12V, VOUT=1.8V, 6A
Page 25
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Typical operating waveforms
Figure 20 Startup with no load (Ch1:PVIN, Ch2: VOUT, Ch3: PGood, Ch4:VCC, Ch5: Enable)
Figure 21 Startup with 6 A load (Ch1:PVIN, Ch2: VOUT, Ch3: PGood, Ch4:VCC, Ch5: Enable)
Page 26
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 22 Shutdown with Enable de-assertion at 6A load (Ch1:PVIN, Ch2: VOUT, Ch3: PGood, Ch4:VCC, Ch5: Enable)
Figure 23 Soft turn off at no load (Ch1:PVIN, Ch2: VOUT, Ch3: PGood, Ch4:VCC, Ch5: Enable)
Page 27
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 24 Startup with no load (Ch1:PVIN, Ch2: VOUT, Ch3: PGood, Ch4:VCC, Ch5: Enable)
Figure 25 Startup with 6 A load (Ch1:PVIN, Ch2: VOUT, Ch3: PGood, Ch4:VCC, Ch5: Enable)
Page 28
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 26 VO ripple at 0A (Ch8:IO, Ch1: Sw, Ch2: VOUT), Peak-Peak VO ripple=12mV
Figure 27 VO ripple at 6A (Ch8:IO, Ch1: Sw, Ch2: Vout), Peak-Peak VO ripple=15.19mV
Page 29
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 28 Transient response 0A to 3A (Ch6:IO, Ch2: VOUT), peak-peak deviation=62mV
Figure 29 Thermal image at PVIN = 12V, VOUT = 1.8V, IO = 6A,
room temperature, no airflow, FS1406 maximum temperature = 69°C
Page 30
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Layout recommendations
Thermal considerations
FS1406 is a highly integrated device with very few
external components, which simplifies PCB layout.
However, to achieve the best performance, these
general PCB design guidelines should be followed:
The FS1406 has been thermally tested and
modelled in accordance with JEDEC specifications
JESD 51-2A and JESD 51-8. It has been tested using
a 4-layer application PCB, with thermal vias under
the device to assist cooling (for details of the PCB,
refer to the application notes).
•
•
•
•
•
•
•
Bypass capacitors, including input/output
capacitors and the VCC bypass capacitor (if
used), should be placed as close as possible to
the FS1406 pins.
Output voltage should be sensed with a
separated trace directly from the output
capacitor.
Analog ground and power ground are
connected through a single-point connection.
To aid thermal dissipation, the PGnd pad
should be connected to the power ground
plane using vias. Copper-filled vias are
preferred but plated-through-hole vias are
acceptable, provided that they are not filled
with resin or covered with solder mask.
Adequate numbers of vias should be used to
make connections between layers, especially
for the power traces.
To minimize power losses and thermal
dissipation, wide copper polygons should be
used for input and output power connections.
SCL and SDA traces must be at least 10mil
wide, with 20–30mil spacing between them.
The FS1406 has two significant sources of heat:
•
•
The power MOSFET section of the IC
The inductor
The IC is well coupled to the PCB, which provides
its primary cooling path. Although the inductor is
also connected to the PCB, its primary cooling path
is through convection. The cooling process for both
heat sources is ultimately through convection. The
PCB can be seen as a heat-spreader or, to some
degree, a heat-sink.
Figure 30 Heat sources in the FS1406
Page 31
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Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 31 shows the thermal resistances in the
FS1406, where:
•
•
•
ϴJA is the measure of natural convection from
the assembled test sample within a confined
enclosure of approximately 30x30x30cm. The
air is passive within this environment and the
only air movement is due to convection from
the device on test.
ϴJCbottom is the heat flow from the IC to the
bottom of the package, to which it is well
coupled. The testing method adopts the
method outlined in JESD 51-8, where the test
PCB is clamped between cold plates at defined
distances from the device.
ϴJCtop is theoretically the heat flow from the IC
to the top of the package. This is not
representative for the FS1406 for two reasons:
firstly, it is not the primary conduction path of
the IC and, more importantly, the inductor is
positioned directly over the IC. As the inductor
is a heat source, generating a similar amount
of heat to the IC, a meaningful value for
junction-to-case (top) cannot be derived.
The values of the thermal resistances are:
•
•
ϴJA = 22.6°C/W
ϴJCbottom = 2.36°C/W
Although these values indicate how the FS1406
compares with similar point-of-load products
tested using the same conditions and
specifications, they cannot be used to predict
overall thermal performance. For accurate
modeling of the µPOL™’s interaction with its
environment, computational fluid dynamics (CFD)
simulation software is needed to calculate
combined routes of conduction and convection
simultaneously.
Note:
In all tests, airflow has been considered as
passive or static; applications using forced air
may achieve a greater cooling effect.
Figure 31 Thermal resistances of the FS1406
Page 32
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
I2C protocol
S
P
A
N
=
=
=
=
Start bit
Stop bit
Ack
Nack
W
R
Sr
=
=
=
Write bit (‘0’)
Read (‘1’)
Repeated start
White bits
Grey bits
=
=
Issued by master
Sent by slave (FS140x)
Write transaction
1
7
1
1
8
1
8
1
1
S
Slave Address
W
A
Register Address
A
Data Byte
A
P
Read transaction
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
W
A
Register Address
A
Sr
Slave Address
R
A
Data Byte
N
P
Page 33
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Package description
The FS1406 is designed for use with standard surfacemount technology (SMT) population techniques. It
has a positive (raised) footprint, with the pads
being higher than the surrounding substrate.
As a result of these properties, the FS1406 works
extremely well in lead-free environments. The
surface wets easily and the positive footprint
accommodates processing variations.
Note:
Refer to the Design Guidelines for more
information about TDK’s µPOL™ package series,
including important guidance on checking the
compatibility of manufacturing processes such
as cleanable flux systems.
Figure 32 Dimensioned drawings
Page 34
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
Figure 33 Tape and reel pack
Page 35
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
Copyright© 2018–20 TDK Corporation. All rights reserved.
All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
FS1406 µPOL™
REMINDERS FOR USING THESE PRODUCTS
Before using these products, be sure to request the delivery specifications.
SAFETY REMINDERS
Please pay sufficient attention to the warnings for safe designing when using these products.
REMINDER
The products listed on this specification sheet are intended for use in general electric equipment (AV equipment, telecommunication
equipment, home appliances, amusement equipment, computer equipment, personal equipment, office equipment, measurement
equipment, industrial robots) under a normal condition and use condition.
The products are not designed or warranted to meet the requirements of the applications listed below, whose performance and/or
quality require a more stringent level of safety or reliability, or whose failure, malfunction or trouble could cause serious damage to
sociality, person or property. Please understand that we are not responsible for any damage or liability caused by use of the products
in any of the applications below or for any other use exceeding the range or conditions set forth in this specification sheet.
1.
Aerospace/Aviation equipment
2.
Transportation equipment (cars, electric trains, ships, etc.)
3.
Medical equipment
4.
Power-generation control equipment
5.
Atomic energy related equipment
6.
Seabed equipment
7.
Transportation control equipment
8.
Public Information-processing equipment
9.
Military equipment
10.
Electric heating apparatus, burning equipment
11.
Disaster prevention/crime prevention equipment
12.
Safety equipment
13.
Other applications that are not considered general-purpose applications
When using this product in general-purpose application, you are kindly requested to take into consideration securing protection
circuit/ equipment or providing backup circuits, etc., to ensure higher safety.
This product is subject to a license from Power One, Inc. related to digital power technology patents
owned by Power One, Inc. Power One, Inc. technology is protected by patents including:
AU
3287379M 3287437AA 3290643AA 3291357AA
CN
10371856C 10452610C 10458656C 10459360C 10465848C 1069332A 11124619A 11346682A
1685299A 1685459A 1685582A 1685583A 1698023A 1802619A
EP
1561156A1 1561268A2 1576710A1 1576711A1 1604254A4 1604264A4 1714369A2 1745536A4
1769382A4 1899789A2 1984801A2
US
20040246754 2004090219A1 2004093533A1 2004123164A1 2004123167A1 2004178780A1
2004179382A1 20050200344 20050223252 2005209373A1 20060061214 2006015619A1
20060174145 20070226526 20070234095 20070240000 20080052551 20080072080 20080186006
6741099 6788036 6936999 6949916 7000125 7049798 7069021 7080265 7249267 7266709 7315156
7372682 7373527 7394445 7456617 7459892 7493504 7526660
WO 04044718A1 04045042A3 04045042C1 04062061A1 04062062A1 04070780A3 04084390A3
04084391A3 05079227A3 05081771A3 06019569A3 2007001584A3 2007094935A3
Page 36
Rev 3.6, May 31, 2023
Patent Protected: US 9,729,059 B1; US 10,193,442 B2
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All registered trademarks and trademarks are the property of their respective owners.
Data and specifications subject to change without notice.
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