ICM-20649 Datasheet
World’s First Wide-Range 6-Axis MEMS MotionTracking™ Device for Sports and
High Impact Applications
APPLICATIONS
GENERAL DESCRIPTION
Many of today’s wearable and sports solutions, which analyze
the motion of a user’s golf or tennis swings, soccer ball kicks,
or basketball activities, require higher than currently available
±2000 dps (degrees per second) FSR for gyroscope and ±16g
FSR for accelerometer to better insure that critical data is not
lost at the point of high impact or high speed rotation. The
ICM-20649 6-axis inertial sensor offers the smallest size,
lowest profile and lowest power in conjunction with industry
leading high FSR.
With an extended FSR range of ±4000 dps for gyroscope and
±30g for accelerometer, the ICM-20649 enables precise
analysis of contact sports applications providing continuous
motion sensor data before, during and after impact providing
more accurate feedback
The ICM-20649 is the world’s first wide-range 6-axis
MotionTracking device for Sports and other High Impact
applications. It is available in a 3x3x0.9 mm 24-pin QFN
package.
ORDERING INFORMATION
PART
TEMP RANGE
ICM-20649†
−40°C to +85°C
PACKAGE
24-Pin QFN
†Denotes RoHS and Green-Compliant Package
BLOCK DIAGRAM
•
•
•
Sports
Wearable Sensors
High Impact Applications
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
3-Axis gyroscope with programmable FSR of
±500 dps, ±100 dps, ±2000 dps, and ±4000 dps
3-Axis accelerometer with programmable FSR of
±4g, ±8g, ±16g, and ±30g
User-programmable interrupts
Wake-on-motion interrupt for low power operation
of applications processor
4kB FIFO buffer enables the applications processor
to read the data in bursts
On-Chip 16-bit ADCs and Programmable Filters
DMP Enabled:
o SMD, Step Count, Step Detect, Activity
Classifier, RV, GRV
o Calibration of accel/gyro/compass
Host interface: 7 MHz SPI or 400 kHz I2C
Digital-output temperature sensor
VDD operating range of 1.71V to 3.6V
MEMS structure hermetically sealed and bonded at
wafer level
RoHS and Green compliant
TYPICAL OPERATING CIRCUIT
RESV
INT2
19
20
nCS
AUX_DA
21
22
SDA / SDI
18
2
17 NC
16 NC
NC
3
NC
4
15 NC
NC
5
14 NC
NC
6
13 VDD
11
12
INT1
FSYNC
REGOUT 10
9
SDO / AD0
VDDIO
8
ICM-20649
7
InvenSense Inc. reserves the right to change specifications and
information herein without notice unless the product is in mass
production and the datasheet has been designated by InvenSense
in writing as subject to a specified Product / Process Change
Notification Method regulation.
23
24
1
NC
C3, 0.1 µ F
Motion Analysis Pod Architecture
GND
NC
AUX_CL
1.8 – 3.3VDC
SCL / SCLK
nCS
SCLK
SDI
C1, 0.1 mF
SDO
InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
invensense.tdk.com
Document Number: DS-000192
Revision: 1.1
Revision Date: 07/01/2021
1.8 – 3.3VDC
C2, 0.1 mF
ICM-20649
TABLE OF CONTENTS
GENERAL DESCRIPTION........................................................................................................................................ 1
ORDERING INFORMATION ................................................................................................................................... 1
APPLICATIONS ...................................................................................................................................................... 1
FEATURES ............................................................................................................................................................. 1
TYPICAL OPERATING CIRCUIT .............................................................................................................................. 1
1
2
3
Introduction ....................................................................................................................................................... 10
1.1
Purpose and Scope .................................................................................................................................. 10
1.2
Product Overview.................................................................................................................................... 10
Features ............................................................................................................................................................. 11
2.1
Gyroscope Features ................................................................................................................................ 11
2.2
Accelerometer Features .......................................................................................................................... 11
2.3
DMP Features .......................................................................................................................................... 11
2.4
Additional Features ................................................................................................................................. 11
Electrical Characteristics .................................................................................................................................... 12
3.1
Gyroscope Specifications ........................................................................................................................ 12
3.2
Accelerometer Specifications.................................................................................................................. 13
3.3
Electrical Specifications ........................................................................................................................... 14
D.C. Electrical Characteristics .................................................................................................................. 14
A.C. Electrical Characteristics .................................................................................................................. 15
Other Electrical Specifications ................................................................................................................ 16
4
3.4
I2C Timing Characterization ..................................................................................................................... 17
3.5
SPI Timing Characterization .................................................................................................................... 18
3.6
Absolute Maximum Ratings .................................................................................................................... 19
Applications Information ................................................................................................................................... 20
4.1
Pin Out Diagram and Signal Description ................................................................................................. 20
4.2
Typical Operating Circuit ......................................................................................................................... 21
4.3
Bill of Materials for External Components .............................................................................................. 21
4.4
Block Diagram ......................................................................................................................................... 22
4.5
Overview ................................................................................................................................................. 22
4.6
Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 23
4.7
Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning......................................... 23
4.8
Digital Motion Processor ......................................................................................................................... 23
4.9
Primary I2C and SPI Serial Communications Interfaces ........................................................................... 23
ICM-20649 Solution Using I2C Interface .................................................................................................. 23
ICM-20649 Solution Using SPI Interface ................................................................................................. 25
4.10
Auxiliary I2C Serial Interface................................................................................................................ 26
4.11
Auxiliary I2C Bus Modes of Operation: ................................................................................................ 26
4.12
Self-Test .............................................................................................................................................. 26
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4.13
Clocking............................................................................................................................................... 26
4.14
Sensor Data Registers ......................................................................................................................... 27
4.15
FIFO ..................................................................................................................................................... 27
4.16
FSYNC .................................................................................................................................................. 27
4.17
Interrupts ............................................................................................................................................ 27
4.18
Digital-Output Temperature Sensor ................................................................................................... 27
4.19
Bias and LDOs ..................................................................................................................................... 27
4.20
Charge Pump ...................................................................................................................................... 27
4.21
Power Modes ...................................................................................................................................... 27
5
Programmable Interrupts .................................................................................................................................. 29
6
Digital Interface ................................................................................................................................................. 30
7
8
6.1
I2C and SPI Serial Interfaces .................................................................................................................... 30
6.2
I2C Interface............................................................................................................................................. 30
6.3
I2C Communications Protocol ................................................................................................................. 31
6.4
I2C Terms ................................................................................................................................................. 33
6.5
SPI Interface ............................................................................................................................................ 33
Register Map ...................................................................................................................................................... 35
7.1
User Bank 0 Register Map: ...................................................................................................................... 35
7.2
User Bank 1 Register Map: ...................................................................................................................... 36
7.3
User Bank 2 Register Map: ...................................................................................................................... 36
7.4
User Bank 3 Register Map: ...................................................................................................................... 37
Register Descriptions ......................................................................................................................................... 38
8.1
USR Bank 0 Register Map ........................................................................................................................ 38
WHO_AM_I ............................................................................................................................................. 38
USER_CTRL .............................................................................................................................................. 38
LP_CONFIG .............................................................................................................................................. 39
PWR_MGMT_1........................................................................................................................................ 39
PWR_MGMT_2........................................................................................................................................ 40
INT_PIN_CFG ........................................................................................................................................... 40
INT_ENABLE ............................................................................................................................................ 41
INT_ENABLE_1 ........................................................................................................................................ 41
INT_ENABLE_2 ........................................................................................................................................ 41
INT_ENABLE_3 .................................................................................................................................... 42
I2C_MST_STATUS ............................................................................................................................... 42
INT_STATUS ........................................................................................................................................ 42
12.1.13 INT_STATUS_1 ....................................................................................................................... 43
INT_STATUS_2 .................................................................................................................................... 43
INT_STATUS_3 .................................................................................................................................... 43
DELAY_TIMEH ..................................................................................................................................... 43
DELAY_TIMEL ...................................................................................................................................... 44
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ACCEL_XOUT_H .................................................................................................................................. 44
ACCEL_XOUT_L ................................................................................................................................... 44
ACCEL_YOUT_H .................................................................................................................................. 44
ACCEL_YOUT_L ................................................................................................................................... 45
ACCEL_ZOUT_H................................................................................................................................... 45
ACCEL_ZOUT_L ................................................................................................................................... 45
GYRO_XOUT_H ................................................................................................................................... 45
GYRO_XOUT_L .................................................................................................................................... 46
GYRO_YOUT_H ................................................................................................................................... 46
GYRO_YOUT_L .................................................................................................................................... 46
GYRO_ZOUT_H ................................................................................................................................... 46
GYRO_ZOUT_L .................................................................................................................................... 47
TEMP_OUT_H ..................................................................................................................................... 47
TEMP_OUT_L ...................................................................................................................................... 47
EXT_SLV_SENS_DATA_00 ................................................................................................................... 47
EXT_SLV_SENS_DATA_01 ................................................................................................................... 48
EXT_SLV_SENS_DATA_02 ................................................................................................................... 48
EXT_SLV_SENS_DATA_03 ................................................................................................................... 48
EXT_SLV_SENS_DATA_04 ................................................................................................................... 48
EXT_SLV_SENS_DATA_05 ................................................................................................................... 49
EXT_SLV_SENS_DATA_06 ................................................................................................................... 49
EXT_SLV_SENS_DATA_07 ................................................................................................................... 49
EXT_SLV_SENS_DATA_08 ................................................................................................................... 49
EXT_SLV_SENS_DATA_09 ................................................................................................................... 50
EXT_SLV_SENS_DATA_10 ................................................................................................................... 50
EXT_SLV_SENS_DATA_11 ................................................................................................................... 50
EXT_SLV_SENS_DATA_12 ................................................................................................................... 50
EXT_SLV_SENS_DATA_13 ................................................................................................................... 51
EXT_SLV_SENS_DATA_14 ................................................................................................................... 51
EXT_SLV_SENS_DATA_15 ................................................................................................................... 51
EXT_SLV_SENS_DATA_16 ................................................................................................................... 51
EXT_SLV_SENS_DATA_17 ................................................................................................................... 52
EXT_SLV_SENS_DATA_18 ................................................................................................................... 52
EXT_SLV_SENS_DATA_19 ................................................................................................................... 52
EXT_SLV_SENS_DATA_20 ................................................................................................................... 52
EXT_SLV_SENS_DATA_21 ................................................................................................................... 53
EXT_SLV_SENS_DATA_22 ................................................................................................................... 53
EXT_SLV_SENS_DATA_23 ................................................................................................................... 53
FIFO_EN_1 .......................................................................................................................................... 54
FIFO_EN_2 .......................................................................................................................................... 54
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FIFO_RST ............................................................................................................................................. 55
FIFO_MODE ........................................................................................................................................ 55
FIFO_COUNTH..................................................................................................................................... 55
FIFO_COUNTL ..................................................................................................................................... 55
FIFO_R_W ........................................................................................................................................... 56
DATA_RDY_STATUS ............................................................................................................................ 56
FIFO_CFG ............................................................................................................................................ 56
REG_BANK_SEL ................................................................................................................................... 56
8.2
USR Bank 1 Register Map ........................................................................................................................ 57
SELF_TEST_X_GYRO ................................................................................................................................ 57
SELF_TEST_Y_GYRO ................................................................................................................................ 57
SELF_TEST_Z_GYRO................................................................................................................................. 57
SELF_TEST_X_ACCEL ............................................................................................................................... 57
SELF_TEST_Y_ACCEL................................................................................................................................ 58
SELF_TEST_Z_ACCEL ................................................................................................................................ 58
XA_OFFS_H.............................................................................................................................................. 58
XA_OFFS_L .............................................................................................................................................. 58
YA_OFFS_H .............................................................................................................................................. 58
YA_OFFS_L .......................................................................................................................................... 59
ZA_OFFS_H ......................................................................................................................................... 59
ZA_OFFS_L .......................................................................................................................................... 59
TIMEBASE_CORRECTION_PLL ............................................................................................................. 59
REG_BANK_SEL ................................................................................................................................... 60
8.3
USR Bank 2 Register Map ........................................................................................................................ 61
GYRO_SMPLRT_DIV................................................................................................................................. 61
GYRO_CONFIG_1 ..................................................................................................................................... 61
GYRO_CONFIG_2 ..................................................................................................................................... 62
XG_OFFS_USRH ....................................................................................................................................... 63
XG_OFFS_USRL ........................................................................................................................................ 64
YG_OFFS_USRH ....................................................................................................................................... 64
YG_OFFS_USRL ........................................................................................................................................ 64
ZG_OFFS_USRH ....................................................................................................................................... 64
ZG_OFFS_USRL ........................................................................................................................................ 64
ODR_ALIGN_EN .................................................................................................................................. 65
ACCEL_SMPLRT_DIV_1 ....................................................................................................................... 65
ACCEL_SMPLRT_DIV_2 ....................................................................................................................... 65
ACCEL_INTEL_CTRL ............................................................................................................................. 65
ACCEL_WOM_THR .............................................................................................................................. 66
ACCEL_CONFIG ................................................................................................................................... 66
ACCEL_CONFIG_2 ............................................................................................................................... 67
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FSYNC_CONFIG ................................................................................................................................... 69
TEMP_CONFIG .................................................................................................................................... 69
MOD_CTRL_USR ................................................................................................................................. 70
REG_BANK_SEL ................................................................................................................................... 70
8.4
USR Bank 3 Register Map ........................................................................................................................ 71
I2C_MST_ODR_CONFIG .......................................................................................................................... 71
I2C_MST_CTRL ........................................................................................................................................ 71
I2C_MST_DELAY_CTRL ............................................................................................................................ 71
I2C_SLV0_ADDR ...................................................................................................................................... 72
I2C_SLV0_REG ......................................................................................................................................... 72
I2C_SLV0_CTRL ........................................................................................................................................ 72
I2C_SLV0_DO........................................................................................................................................... 73
I2C_SLV1_ADDR ...................................................................................................................................... 73
I2C_SLV1_REG ......................................................................................................................................... 73
I2C_SLV1_CTRL ................................................................................................................................... 74
SLV1_DO ............................................................................................................................................. 74
I2C_SLV2_ADDR .................................................................................................................................. 75
I2C_SLV2_REG ..................................................................................................................................... 75
I2C_SLV2_CTRL ................................................................................................................................... 75
I2C_SLV2_DO ...................................................................................................................................... 76
I2C_SLV3_ADDR .................................................................................................................................. 76
I2C_SLV3_REG ..................................................................................................................................... 76
I2C_SLV3_CTRL ................................................................................................................................... 77
I2C_SLV3_DO ...................................................................................................................................... 77
I2C_SLV4_ADDR .................................................................................................................................. 78
I2C_SLV4_REG ..................................................................................................................................... 78
I2C_SLV4_CTRL ................................................................................................................................... 78
I2C_SLV4_DO ...................................................................................................................................... 78
I2C_SLV4_DI ........................................................................................................................................ 79
REG_BANK_SEL ................................................................................................................................... 79
9
10
Use Notes ........................................................................................................................................................... 80
9.1
Gyroscope Mode Transition .................................................................................................................... 80
9.2
Power Management 1 Register Setting .................................................................................................. 80
9.3
DMP Memory Access .............................................................................................................................. 80
9.4
Time Base Correction .............................................................................................................................. 80
9.5
I2C Master Clock Frequency .................................................................................................................... 81
9.6
Clocking ................................................................................................................................................... 81
9.7
LP_EN Bit-Field Usage ............................................................................................................................. 82
9.8
Register Access Using SPI Interface ......................................................................................................... 82
Orientation of Axes ............................................................................................................................................ 83
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11
Package Dimensions .......................................................................................................................................... 84
12
Part Number Part Markings ............................................................................................................................... 86
13
References ......................................................................................................................................................... 87
14
Revision History ................................................................................................................................................. 88
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LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram ............................................................................................................................................................. 17
Figure 2. SPI Bus Timing Diagram............................................................................................................................................................. 18
Figure 3. Pin out Diagram for ICM-20649 3.0x3.0x0.9 mm QFN .............................................................................................................. 20
Figure 4. ICM-20649 Application Schematic (a) I2C operation (b) SPI operation ..................................................................................... 21
Figure 5. ICM-20649 Block Diagram......................................................................................................................................................... 22
Figure 6. ICM-20649 Solution Using I2C Interface .................................................................................................................................... 24
Figure 7. ICM-20649 Solution Using SPI Interface ................................................................................................................................... 25
Figure 8. START and STOP Conditions ...................................................................................................................................................... 31
Figure 9. Acknowledge on the I2C Bus ..................................................................................................................................................... 31
Figure 10. Complete I2C Data Transfer ..................................................................................................................................................... 32
Figure 11. Typical SPI Master / Slave Configuration ................................................................................................................................ 34
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................................... 83
Figure 13. Package Dimensions................................................................................................................................................................ 84
Figure 14. Part Number Package Markings .............................................................................................................................................. 86
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LIST OF TABLES
Table 1. Gyroscope Specifications ........................................................................................................................................................... 12
Table 2. Accelerometer Specifications ..................................................................................................................................................... 13
Table 3. D.C. Electrical Characteristics ..................................................................................................................................................... 14
Table 4. A.C. Electrical Characteristics ..................................................................................................................................................... 16
Table 5. Other Electrical Specifications .................................................................................................................................................... 16
Table 6. I2C Timing Characteristics ........................................................................................................................................................... 17
Table 7. SPI Timing Characteristics (7 MHz) ............................................................................................................................................. 18
Table 8. Absolute Maximum Ratings ....................................................................................................................................................... 19
Table 9. Signal Descriptions ..................................................................................................................................................................... 20
Table 10. Bill of Materials ........................................................................................................................................................................ 21
Table 11. Power Modes for ICM-20649 ................................................................................................................................................... 28
Table 12. Table of Interrupt Sources ........................................................................................................................................................ 29
Table 13. Serial Interface ......................................................................................................................................................................... 30
Table 14. I2C Terms .................................................................................................................................................................................. 33
Table 15. Configuration............................................................................................................................................................................ 62
Table 16. Gyroscope Filter Bandwidths (Low-Power Mode) ................................................................................................................... 63
Table 17. Accelerometer Configuration ................................................................................................................................................... 67
Table 18. Accelerometer Configuration 2 ................................................................................................................................................ 68
Table 19. I2C Master Clock Frequency ..................................................................................................................................................... 81
Table 20. Package Dimensions ................................................................................................................................................................. 85
Table 21. Part Number Package Markings ............................................................................................................................................... 86
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1 INTRODUCTION
1.1
PURPOSE AND SCOPE
This document is a preliminary product specification, providing a description, specifications, and design related information on the
ICM-20649 MotionTracking device.
Final specifications are available via our sales contacts. For references to register map and descriptions of individual registers, please
refer to the ICM-20649 Register Map and Register Descriptions sections.
1.2
PRODUCT OVERVIEW
The ICM-20649 is a MotionTracking device that combines a 3-axis gyroscope, 3-axis accelerometer, and a Digital Motion Processor™
(DMP) all in a small 3.0x3.0x0.9mm QFN package. The device supports the following features:
•
•
•
•
Android Lollipop support
FIFO of size 4kB (FIFO size will vary depending on DMP feature-set)
Runtime Calibration
Enhanced FSYNC functionality to improve timing for applications like EIS
ICM-20649 devices, with their 6-axis integration, on-chip DMP, and run-time calibration firmware, enable manufacturers to
eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal
motion performance for consumers.
The gyroscope has a programmable full-scale range up to ±4000 dps. The accelerometer has a user-programmable accelerometer
full-scale range up to ±30g. Factory-calibrated initial sensitivity of both sensors reduces production-line calibration requirements.
Other key features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable
interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate digital IO supply,
VDDIO from 1.71V to 3.6V.
Communication with all registers of the device is performed using I2C at up to 100 kHz (standard-mode) or up to 400 kHz (fastmode), or SPI at up to 7 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
3.0x3.0x0.9 mm (24-pin QFN), to provide a very small yet high-performance, low-cost package. The device provides high robustness
by supporting 10,000g shock reliability.
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2 FEATURES
2.1
GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-20649 includes the following features:
•
•
•
•
2.2
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±500 dps,
±1000 dps, ±2000 dps, and ±4000 dps and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Factory calibrated sensitivity scale factor
Self-test
ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-20649 includes the following features:
•
•
•
•
2.3
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±4g, ±8g, ±16g, and ±30g and
integrated 16-bit ADCs
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
DMP FEATURES
The DMP in ICM-20649 includes the following capabilities:
•
•
•
•
•
•
2.4
Offloads computation of motion processing algorithms from the host processor. The DMP can be used to minimize power,
simplify timing, simplify the software architecture, and save valuable MIPS on the host processor for use in applications.
Optimized for Android Lollipop for low power features (AP suspended) including SMD, Step Count, Step Detect, Activity
Classification, Rotation Vector, and Gaming Rotation Vector
Optimized for Android Lollipop batching, both while the AP is active and suspended. The DMP will also batch data from
externally connected sensors such as a compass, or pressure sensor.
The DMP enables ultra-low power run-time and background calibration of the accelerometer, gyroscope, and compass,
maintaining optimal performance of the sensor data for both physical and virtual sensors generated through sensor fusion.
This enables the best user experience for all sensor enabled applications for the lifetime of the device.
DMP features simplify the software architecture resulting in quicker time to market.
DMP features are OS, Platform, and Architecture independent, supporting virtually any AP, MCU, or other embedded
architecture.
ADDITIONAL FEATURES
The ICM-20649 includes the following additional features:
•
•
•
•
•
•
I2C at up to 100 kHz (standard-mode) or up to 400 kHz (fast-mode) or SPI at up to 7 MHz for communication with registers
Auxiliary master I2C bus for reading data from external sensors (e.g. magnetometer)
Digital-output temperature sensor
10,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
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3 ELECTRICAL CHARACTERISTICS
3.1
GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
Note: All specifications apply to Standard (Duty-Cycled) Mode and Low-Noise Mode, unless noted otherwise.
PARAMETER
Full-Scale Range
Gyroscope ADC Word Length
Sensitivity Scale Factor
Sensitivity Scale Factor Tolerance
Sensitivity Scale Factor Variation Over
Temperature
Nonlinearity
Cross-Axis Sensitivity
CONDITIONS
GYROSCOPE SENSITIVITY
GYRO_FS_SEL = 0
GYRO_FS_SEL = 1
GYRO_FS_SEL = 2
GYRO_FS_SEL = 3
GYRO_FS_SEL = 0
GYRO_FS_SEL = 1
GYRO_FS_SEL = 2
GYRO_FS_SEL = 3
25°C
-40°C to +85°C
Best fit straight line; 25°C
MIN
TYP
UNITS
NOTES
±500
±1000
±2000
±4000
16
65.5
32.8
16.4
8.2
±0.5
±2
dps
dps
dps
dps
bits
LSB/(dps)
LSB/(dps)
LSB/(dps)
LSB/(dps)
%
%
1
1
1
1
1
1
1
1
1
3
2
±0.1
±2
%
%
2, 4
2, 4
dps
dps/°C
3
2
3
3
1, 4
2, 4
562.5
dps/√Hz
kHz
Hz
ms
Hz
1.125k
Hz
ZERO-RATE OUTPUT (ZRO)
25°C (Component-level)
±5
-40°C to +85°C
±0.05
GYROSCOPE NOISE PERFORMANCE (GYRO_FS_SEL=0)
Noise Spectral Density
Based on Noise Bandwidth = 10 Hz
0.0175
GYROSCOPE MECHANICAL FREQUENCIES
25
27
LOW PASS FILTER RESPONSE
Programmable Range
5.7
GYROSCOPE START-UP TIME
From Full-Chip Sleep mode
35
Standard (duty-cycled) Mode
4.4
Low-Noise Mode
GYRO_FCHOICE = 1;
4.4
OUTPUT DATA RATE
GYRO_DLPFCFG = x
Low-Noise Mode
GYRO_FCHOICE = 0;
GYRO_DLPFCFG = x
MAX
Initial ZRO Tolerance
ZRO Variation Over Temperature
29
197
1
9k
Hz
Table 1. Gyroscope Specifications
Notes:
1.
2.
3.
4.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Tested in production.
Low-noise mode specification.
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3.2
ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
Note: All specifications apply to Standard (Duty-Cycled) Mode and Low-Noise Mode, unless noted otherwise.
PARAMETER
Full-Scale Range
ADC Word Length
Sensitivity Scale Factor
Initial Tolerance
Sensitivity Change vs. Temperature
Nonlinearity
Cross-Axis Sensitivity
Initial Tolerance
Zero-G Level Change vs. Temperature
Noise Spectral Density
LOW PASS FILTER RESPONSE
INTELLIGENCE FUNCTION
INCREMENT
ACCELEROMETER STARTUP TIME
OUTPUT DATA RATE
CONDITIONS
ACCELEROMETER SENSITIVITY
ACCEL_FS = 0
ACCEL_FS = 1
ACCEL_FS = 2
ACCEL_FS = 3
Output in two’s complement format
ACCEL_FS = 0
ACCEL_FS = 1
ACCEL_FS = 2
ACCEL_FS = 3
Component-level
-40°C to +85°C ACCEL_FS=0
Best Fit Straight Line
MIN
Component-level, all axes
0°C to +85°C
ACCELEROMETER NOISE PERFORMANCE
Based on Noise Bandwidth = 10 Hz
Programmable Range
5.7
From Sleep mode
From Cold Start, 1ms VDD ramp
Low-Power Mode
Low-Noise Mode
ACCEL_FCHOICE = 1;
ACCEL_DLPFCFG = x
Low-Noise Mode
ACCEL_FCHOICE = 0;
ACCEL_DLPFCFG = x
TYP
MAX
UNITS
NOTES
±4
±8
±16
±30
16
8,192
4,096
2,048
1,024
±0.5
±0.026
±0.5
±2
g
g
g
g
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
%/ºC
%
%
1
1
1
1
1
1
1
1
1
3
2
2, 4
2, 4
±65
±0.80
mg
mg/°C
3
2
µg/√Hz
Hz
1, 4
32
mg/LSB
1
20
30
2, 4
2, 4
285
246
0.27
562.5
ms
ms
Hz
4.5
1.125k
Hz
1
4.5k
Hz
Table 2. Accelerometer Specifications
Notes:
1.
2.
3.
4.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Tested in production.
Low-noise mode specification.
Document Number: DS-000192
Revision: 1.1
3
Page 13 of 89
ICM-20649
3.3
ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
VDD
VDDIO
MIN
TYP
MAX
UNITS
NOTES
1.71
1.71
1.8
1.8
3.6
3.6
V
V
1
1
SUPPLY CURRENTS
Gyroscope Only
(DMP & Accelerometer disabled)
Accelerometer Only
(DMP & Gyroscope disabled)
Gyroscope + Accelerometer
(DMP disabled)
Gyroscope Only
(DMP & Accelerometer disabled)
Accelerometer Only
(DMP & Gyroscope disabled)
Gyroscope + Accelerometer
(DMP disabled)
Full-Chip Sleep Mode
Specified Temperature Range
Low-Noise Mode
2.67
mA
2
Low-Noise Mode
760
µA
2
Low-Noise Mode
3.21
mA
2
1.23
mA
2, 3
68.9
µA
2, 3
1.27
mA
2, 3
8
µA
2
°C
1
Low-Power Mode, 102.3 Hz update rate, 1x
averaging filter
Low-Power Mode, 102.3 Hz update rate, 1x
averaging filter
Low-Power Mode, 102.3 Hz update rate,
1x averaging filter
TEMPERATURE RANGE
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
Table 3. D.C. Electrical Characteristics
Notes:
1.
2.
3.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
The 102.3 Hz ODR value shown here is an example; please see the section below for the full list of ODRs supported and corresponding current values.
Document Number: DS-000192
Revision: 1.1
Page 14 of 89
ICM-20649
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
100
ms
1
85
°C
LSB/°C
LSB
1
100
100
ms
ms
1
1
0.3*VDDIO
V
V
pF
1
SUPPLIES
Supply Ramp Time (TRAMP)
Operating Range
Sensitivity
Room Temp Offset
Supply Ramp Time (TRAMP)
Start-up time for register read/write
I2C ADDRESS
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT1, INT Low-Level Output Voltage
Output Leakage Current
tINT, INT Pulse Width
Monotonic ramp. Ramp
0.01
20
rate is 10% to 90% of the
final value.
TEMPERATURE SENSOR
Ambient
-40
Untrimmed
333.87
21°C
0
Power-On RESET
Valid power-on RESET
0.01
20
From power-up
11
AD0 = 0
1101000
AD0 = 1
1101001
DIGITAL INPUTS (FSYNC, AD0, SCLK, SDI, CS)
0.7*VDDIO
< 10
DIGITAL OUTPUT (SDO, INT)
0.9*VDDIO
RLOAD = 1 MΩ;
RLOAD = 1 MΩ;
OPEN = 1, 0.3 mA sink
Current
OPEN = 1
LATCH_INT_EN = 0
Vhys, Hysteresis
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
VIL, LOW-Level Input Voltage
VIH, HIGH-Level Input Voltage
Vhys, Hysteresis
VOL1, LOW-Level Output Voltage
VOL3, LOW-Level Output Voltage
IOL, LOW-Level Output Current
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
Clock Frequency Initial Tolerance
Document Number: DS-000192
Revision: 1.1
100
50
I2C I/O (SCL, SDA)
-0.5 V
0.7*VDDIO
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
V
V
V
0.1*VDDIO
0.1
nA
µs
0.3*VDDIO
VDDIO +
0.5 V
V
V
0.1*VDDIO
3 mA sink current
VOL = 0.4 V
VOL = 0.6 V
Cb bus capacitance in pf
0
V
V
mA
mA
nA
0.4
3
6
100
20+0.1 Cb
AUXILLIARY I/O (AUX_CL, AUX_DA)
-0.5 V
0.7* VDDIO
250
ns
0.3*VDDIO
VDDIO +
0.5 V
V
V
0.1* VDDIO
VDDIO > 2 V; 1 mA sink
current
VDDIO < 2 V; 1 mA sink
current
VOL = 0.4 V
VOL = 0.6 V
Cb bus capacitance in pF
0
0.4
V
V
0
0.2* VDDIO
V
250
mA
mA
nA
ns
3
6
100
20+0.1Cb
INTERNAL CLOCK SOURCE
Accelerometer Only Mode
-5
Gyroscope or 6-Axis Mode
WITHOUT Timebase
-9
Correction
Gyroscope or 6-Axis Mode
-1
WITH Timebase Correction
1
+5
%
1
1
1
1
+9
%
+1
Page 15 of 89
ICM-20649
PARAMETER
Frequency Variation over
Temperature
CONDITIONS
Accelerometer Only Mode
Gyroscope or 6-Axis Mode
MIN
-10
TYP
MAX
+10
±1
UNITS
%
%
NOTES
1
1
Table 4. A.C. Electrical Characteristics
Notes:
1.
Derived from validation or characterization of parts, not guaranteed in production.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETER
SPI Operating Frequency, All
Registers Read/Write
I2C Operating Frequency
CONDITIONS
SERIAL INTERFACE
MIN
Low Speed Characterization
High Speed Characterization
All registers, Fast-mode
All registers, Standard-mode
TYP
MAX
100
±10%
7 ±10%
Units
kHz
400
100
MHz
kHz
kHz
Table 5. Other Electrical Specifications
Document Number: DS-000192
Revision: 1.1
Page 16 of 89
Notes
ICM-20649
3.4
I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
PARAMETERS
I2C TIMING
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold
Time
tLOW, SCL Low Period
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup
Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
CONDITIONS
I2C FAST-MODE
MIN
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
MAX
UNITS
NOTES
400
0.6
kHz
µs
1, 2
1, 2
1.3
0.6
0.6
µs
µs
µs
1, 2
1, 2
1, 2
0
100
20+0.1Cb
20+0.1Cb
0.6
µs
ns
ns
ns
µs
1, 2
1, 2
1, 2
1, 2
1, 2
µs
1, 2
pF
µs
µs
1, 2
1, 2
1, 2
tBUF, Bus Free Time Between STOP and
START Condition
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time
TYPICAL
300
300
1.3
< 400
0.9
0.9
Table 6. I2C Timing Characteristics
Notes:
1.
2.
Timing Characteristics apply to both Primary and Auxiliary I2C Bus.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
tf
SDA
tSU.DAT
tr
70%
30%
70%
30%
continued below at
tf
SCL
tr
70%
30%
S
tHD.STA
tVD.DAT
70%
30%
tHD.DAT
1/fSCL
tLOW
1st clock cycle
9th clock cycle
tHIGH
tBUF
SDA
70%
30%
A
tSU.STA
tHD.STA
SCL
70%
30%
Sr
tSU.STO
tVD.ACK
9th clock cycle
P
S
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000192
Revision: 1.1
Page 17 of 89
A
ICM-20649
3.5
SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted.
Parameters
SPI TIMING
fSCLK, SCLK Clock Frequency
Conditions
Min
Typical
Max
Units
7
MHz
tLOW, SCLK Low Period
64
ns
tHIGH, SCLK High Period
64
ns
tSU.CS, CS Setup Time
8
ns
tHD.CS, CS Hold Time
500
ns
5
ns
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
7
tVD.SDO, SDO Valid Time
Cload = 20 pF
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
Cload = 20 pF
Notes
ns
59
ns
50
ns
ns
6
Table 7. SPI Timing Characteristics (7 MHz)
Note:
1.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
CS
70%
30%
tFall
tSU;CS
SCLK
tHIGH
70%
30%
tLOW
tHD;SDI
LSB IN
MSB IN
tVD;SDO
SDO
tHD;CS
70%
30%
tSU;SDI
SDI
tRise
1/fCLK
MSB OUT
tDIS;SDO
tHD;SDO
70%
30%
LSB OUT
Figure 2. SPI Bus Timing Diagram
Document Number: DS-000192
Revision: 1.1
Page 18 of 89
ICM-20649
3.6
ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
Parameter
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
Input Voltage Level (AUX_DA, AD0, FSYNC, INT, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Protection
Latch-up
Rating
-0.5V to 4V
-0.5V to 4V
-0.5V to 2V
-0.5V to VDD + 0.5V
10,000g for 0.2 ms
-40°C to +105°C
-40°C to +125°C
2 kV (HBM);
200V (MM)
JEDEC Class II (2),125°C
±100 mA
Table 8. Absolute Maximum Ratings
Document Number: DS-000192
Revision: 1.1
Page 19 of 89
ICM-20649
4 APPLICATIONS INFORMATION
4.1
PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
7
8
9
10
11
12
13
18
19
20
21
22
23
24
1 – 6, 14 - 17
PIN NAME
AUX_CL
VDDIO
AD0 / SDO
REGOUT
FSYNC
INT1
VDD
GND
INT2
RESV
AUX_DA
nCS
SCL / SCLK
SDA / SDI
NC
PIN DESCRIPTION
I2C Master serial clock, for connecting to external sensors.
Digital I/O supply voltage.
I2C Slave Address LSB (AD0); SPI serial data output (SDO).
Regulator filter capacitor connection.
Frame synchronization digital input. Connect to GND if unused.
Interrupt 1.
Power supply voltage.
Power supply ground.
Interrupt 2.
Reserved. Connect to GND.
I2C master serial data, for connecting to external sensors.
Chip select (SPI mode only).
I2C serial clock (SCL); SPI serial clock (SCLK).
I2C serial data (SDA); SPI serial data input (SDI).
No Connect pins. Do not connect.
SDA / SDI
SCL / SCLK
nCS
AUX_DA
RESV
INT2
24
23
22
21
20
19
Table 9. Signal Descriptions
NC
1
18 GND
NC
2
17 NC
NC
3
NC
4
15 NC
NC
5
14 NC
NC
6
13 VDD
16 NC
7
8
9
10
11
12
AUX_CL
VDDIO
SDO / AD0
REGOUT
FSYNC
INT1
ICM-20649
Figure 3. Pin out Diagram for ICM-20649 3.0x3.0x0.9 mm QFN
Document Number: DS-000192
Revision: 1.1
Page 20 of 89
ICM-20649
TYPICAL OPERATING CIRCUIT
1
18
NC
2
17 NC
RESV
INT2
19
20
21
AUX_DA
nCS
22
23
SDA / SDI
24
INT2
RESV
20
21
nCS
AUX_DA
22
SDA / SDI
SCL / SCLK
23
24
19
GND
NC
GND
NC
1
18
NC
2
17 NC
NC
3
16 NC
NC
3
NC
4
15 NC
NC
4
15 NC
NC
5
14 NC
NC
5
14 NC
NC
6
13 VDD
NC
6
13 VDD
C3, 0.1 µ F
AD0
12
1.8 – 3.3VDC
C2, 0.1 mF
INT1
11
FSYNC
9
REGOUT 10
SDO / AD0
1.8 – 3.3VDC
8
7
C2, 0.1 mF
C1, 0.1 mF
C3, 0.1 µ F
16 NC
ICM-20649
VDDIO
12
1.8 – 3.3VDC
INT1
11
FSYNC
REGOUT 10
9
SDO / AD0
8
VDDIO
7
ICM-20649
AUX_CL
1.8 – 3.3VDC
SCLK
SDI
SCL / SCLK
nCS
VDDIO
SCL
SDA
AUX_CL
4.2
C1, 0.1 mF
SDO
(a)
(b)
Figure 4. ICM-20649 Application Schematic (a) I2C operation (b) SPI operation
4.3
BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component
Label
Specification
Quantity
Regulator Filter Capacitor
C1
Ceramic, X7R, 0.1 µF ±10%
1
VDD Bypass Capacitor
C2
Ceramic, X7R, 0.1 µF ±10%
1
VDDIO Bypass Capacitor
C3
Ceramic, X7R, 0.1 µF ±10%
1
Table 10. Bill of Materials
Document Number: DS-000192
Revision: 1.1
Page 21 of 89
ICM-20649
4.4
BLOCK DIAGRAM
ICM-20649
INT1
Self
test
X Accel
ADC
Self
test
Y Accel
ADC
INT2
Interrupt
Status
Register
nCS
Slave I2C and
SPI Serial
Interface
FIFO
AD0 / SDO
SCL / SCLK
SDA / SDI
Z Accel
ADC
Self
test
X Gyro
ADC
Self
test
Y Gyro
Self
test
Z Gyro
Temp Sensor
Signal Conditioning
Self
test
User & Config
Registers
Serial
Interface
Bypass
Mux
Master I2C
Serial
Interface
Sensor
Registers
AUX_CL
AUX_DA
FSYNC
ADC
Digital Motion
Processor
(DMP)
ADC
ADC
Bias & LDOs
Charge
Pump
VDD
GND
REGOUT
Figure 5. ICM-20649 Block Diagram
4.5
OVERVIEW
The ICM-20649 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Digital Motion Processor (DMP) engine
Primary I2C and SPI serial communications interfaces
Auxiliary I2C serial interface
Self-Test
Clocking
Sensor Data Registers
FIFO
FSYNC
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Power Modes
Document Number: DS-000192
Revision: 1.1
Page 22 of 89
ICM-20649
4.6
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20649 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.
When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff.
The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage
is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro
sensors may be digitally programmed to ±500, ±1000, ±2000, or ±4000 degrees per second (dps).
4.7
THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20649’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The ICM-20649’s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full scale range of the digital output can be adjusted to ±4g, ±8g, ±16g, or ±30g.
4.8
DIGITAL MOTION PROCESSOR
The embedded Digital Motion Processor (DMP) within the ICM-20649 offloads computation of motion processing algorithms from
the host processor. The DMP acquires data from accelerometers, gyroscopes, and additional third party sensors such as
magnetometers, and processes the data. The resulting data can be read from the FIFO. The DMP has access to the external pins,
which can be used for generating interrupts.
The purpose of the DMP is to offload both timing requirements and processing power from the host processor. Typically, motion
processing algorithms should be run at a high rate, often around 200 Hz, in order to provide accurate results with low latency. This is
required even if the application updates at a much lower rate; for example, a low power user interface may update as slowly as 5 Hz,
but the motion processing should still run at 200 Hz. The DMP can be used to minimize power, simplify timing, simplify the software
architecture, and save valuable MIPS on the host processor for use in applications.
The DMP is optimized for Android Lollipop support.
4.9
PRIMARY I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The ICM-20649 communicates to a system processor using either a SPI or an I2C serial interface. The
ICM-20649 always acts as a slave when communicating to the system processor. The LSB of the of the I2C slave address is set by pin
1 (AD0).
ICM-20649 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the ICM-20649. In addition, the ICM-20649 is an I2C master to the optional
external compass sensor. The ICM-20649 has limited capabilities as an I2C Master, and depends on the system processor to manage
the initial configuration of any auxiliary sensors. The ICM-20649 has an interface bypass multiplexer, which connects the system
processor I2C bus pins 23 and 24 (SCL and SDA) directly to the auxiliary sensor I2C bus pins 7 and 21 (AUX_CL and AUX_DA).
Once the auxiliary sensors have been configured by the system processor, the interface bypass multiplexer should be disabled so
that the ICM-20649 auxiliary I2C master can take control of the sensor I2C bus and gather data from the auxiliary sensors.
Document Number: DS-000192
Revision: 1.1
Page 23 of 89
ICM-20649
Interrupt
Status
Register
I2C Processor Bus: for reading all
sensor data from MPU and for
configuring external sensors (i.e.
compass in this example)
INT1
INT2
ICM-20649
AD0
Slave I2C
or SPI
Serial
Interface
VDD or GND
SCL
SCL
SDA/SDI
SDA
System
Processor
FIFO
Sensor I2C Bus: for
configuring and reading
from external sensors
User & Config
Registers
Optional
Sensor
Master I2C
Serial
Interface
Sensor
Register
Interface
Bypass
Mux
AUX_CL
SCL
AUX_DA
SDA
Compass
Factory
Calibration
Digital
Motion
Processor
(DMP)
Interface bypass mux allows
direct configuration of
compass by system processor
Bias & LDOs
VDD
GND
REGOUT
Figure 6. ICM-20649 Solution Using I2C Interface
Document Number: DS-000192
Revision: 1.1
Page 24 of 89
ICM-20649
ICM-20649 Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the ICM-20649. Pins 9, 22, 23, and 24 are used to support the SDO, nCS, SCLK,
and SDI signals for SPI communications. Because these SPI pins are shared with the I 2C slave pins (9, 23 and 24), the system
processor cannot access the auxiliary I2C bus through the interface bypass multiplexer, which connects the processor I 2C interface
pins to the sensor I2C interface pins. Since the ICM-20649 has limited capabilities as an I2C Master, and depends on the system
processor to manage the initial configuration of any auxiliary sensors, another method must be used for programming the sensors
on the auxiliary sensor I2C bus pins 7 and 21 (AUX_CL and AUX_DA).
When using SPI communications between the ICM-20649 and the system processor, configuration of devices on the auxiliary I2C
sensor bus can be achieved by using I2C Slaves 0-4 to perform read and write transactions on any device and register on the auxiliary
I2C bus. The I2C Slave 4 interface can be used to perform only single byte read and write transactions. Once the external sensors have
been configured, the ICM-20649 can perform single or multi-byte reads using the sensor I2C bus. The read results from the Slave 0-3
controllers can be written to the FIFO buffer as well as to the external sensor registers.
For more information regarding the control of the ICM-20649’s auxiliary I2C interface, please refer to the
ICM-20649 Register Map and Register Descriptions sections.
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU and external sensors
Interrupt
Status
Register
INT1
INT2
ICM-20649
Slave I2C
or SPI
Serial
Interface
nCS
nCS
SDO
SDI
SCLK
SCLK
SDI
System
Processor
SDO
FIFO
Sensor I2C Bus: for
configuring and
reading data from
external sensors
Config
Register
Optional
Sensor
Master I2C
Serial
Interface
Sensor
Register
Interface
Bypass
Mux
AUX_CL
SCL
AUX_DA
SDA
Compass
Factory
Calibration
Digital
Motion
Processor
(DMP)
I2C Master performs
read and write
transactions on
Sensor I2C bus.
Bias & LDOs
VDD
GND
REGOUT
Figure 7. ICM-20649 Solution Using SPI Interface
Document Number: DS-000192
Revision: 1.1
Page 25 of 89
ICM-20649
4.10 AUXILIARY I2C SERIAL INTERFACE
The ICM-20649 has an auxiliary I2C bus for communicating to an off-chip 3-Axis digital output magnetometer or other sensors. This
bus has two operating modes:
•
•
I2C Master Mode: The ICM-20649 acts as a master to any external sensors connected to the auxiliary I2C bus
Pass-Through Mode: The ICM-20649 directly connects the primary and auxiliary I2C buses together, allowing the system
processor to directly communicate with any external sensors.
4.11 AUXILIARY I2C BUS MODES OF OPERATION:
I2C Master Mode: Allows the ICM-20649 to directly access the data registers of external digital sensors, such as a magnetometer. In
this mode, the ICM-20649 directly obtains data from auxiliary sensors without intervention from the system applications processor.
For example, in I2C Master mode, the ICM-20649 can be configured to perform burst reads, returning the following data from a
magnetometer:
•
•
•
X magnetometer data (2 bytes)
Y magnetometer data (2 bytes)
Z magnetometer data (2 bytes)
The I2C Master can be configured to read up to 24 bytes from up to 4 auxiliary sensors. A fifth sensor can be configured to work
single byte read/write mode.
Pass-Through Mode: Allows an external system processor to act as master and directly communicate to the external sensors
connected to the auxiliary I2C bus pins (AUX_DA and AUX_CL). In this mode, the auxiliary I2C bus control logic (3rd party sensor
interface block) of the ICM-20649 is disabled, and the auxiliary I2C pins AUX_CL and AUX_DA (pins 7 and 21) are connected to the
main I2C bus (Pins 23 and 24) through analog switches internally. Pass-Through mode is useful for configuring the external sensors.
4.12 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITHOUT SELF-TEST ENABLED
The self-test response for each gyroscope axis is defined in the gyroscope specification table, while that for each accelerometer axis
is defined in the accelerometer specification table.
When the value of the self-test response is within the specified min/max limits, the part has passed self-test. When the self-test
response exceeds the min/max values, the part is deemed to have failed self-test. It is recommended to use InvenSense MotionApps
software for executing self-test.
4.13 CLOCKING
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope oscillator as the
reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for optimum sensor performance
and power consumption will be automatically selected based on the power mode. Specifically, the internal relaxation oscillator will
be selected when operating in accelerometer only mode, while the PLL will be selected whenever gyroscope is on, which includes
gyroscope and 6-axis modes.
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ICM-20649
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted that the
internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation oscillator is trimmed to
have a consistent operating frequency at room temperature, while the PLL clock frequency varies from part to part. The PLL
frequency deviation from the nominal value in percentage is captured in register TIMEBASE_CORRECTION_PLL (detailed in section
12.5), and users can factor it in during distance and angle calculations to not sacrifice accuracy. Other than that, PLL has better
frequency stability and lower frequency variation over temperature than the internal relaxation oscillator.
4.14 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyro, accelerometer, auxiliary sensor, and temperature measurement data. They are
read-only registers, and are accessed via the serial interface. Data from these registers may be read anytime.
4.15 FIFO
The ICM-20649 contains a FIFO of size 4kB (FIFO size will vary depending on DMP feature-set) that is accessible via the Serial
Interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyro data,
accelerometer data, temperature readings, auxiliary sensor readings, and FSYNC input.
A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads. The
interrupt function may be used to determine when new data is available.
For further information regarding the FIFO, please refer to the ICM-20649 Register Map and Register Descriptions sections.
4.16 FSYNC
The FSYNC pin can be used from an external interrupt source to wake up the device from sleep. It is particularly useful in EIS
applications to synchronize the gyroscope ODR with external inputs from an imaging sensor. Connecting the VSYNC or HSYNC pin of
the image sensor subsystem to FSYNC on ICM-20649 allows timing synchronization between the two otherwise unconnected
subsystems.
An FSYNC_ODR delay time register is used to capture the delay between an FSYNC pulse and the very next gyroscope data ready
pulse.
4.17 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pins
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Section 5 provides a summary of interrupt
sources. The ICM-20649 includes two interrupt pins, INT1 and INT2. Certain DMP-based interrupts are mapped to INT2 while all
other interrupts are mapped to INT1. The interrupt status can be read from the Interrupt Status register.
For further information regarding interrupts, please refer to the ICM-20649 Register Map and Register Descriptions sections.
4.18 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-20649 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
4.19 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-20649. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
4.20 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillators.
4.21 POWER MODES
The following table lists the user-accessible power modes for ICM-20649.
MODE
1
NAME
Sleep Mode
Document Number: DS-000192
Revision: 1.1
GYRO
Off
ACCEL
Off
DMP
Off
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ICM-20649
MODE
2
3
NAME
Accelerometer Mode
Gyroscope Mode
4
6-Axis Mode
5
DMP only mode
GYRO
Off
Low-Noise or DutyCycled
Low-Noise or DutyCycled
Off
ACCEL
Low-Noise or Duty-Cycled
Off
DMP
Duty-Cycled or Off
Duty-Cycled or Off
Low-Noise or Duty-Cycled
Duty-Cycled or Off
Off
Duty-Cycled
Table 11. Power Modes for ICM-20649
Note: The standard mode of gyroscope and accelerometer operation is duty-cycled.
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Revision: 1.1
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ICM-20649
5 PROGRAMMABLE INTERRUPTS
The ICM-20649 has a programmable interrupt system which can generate an interrupt signal on the INT pins. Status flags indicate
the source of an interrupt. Interrupt sources may be enabled and disabled individually. The following table lists the interrupt sources
and which interrupt may propagate to which pin.
INTERRUPT SOURCE
DMP Interrupt
Wake on Motion Interrupt
PLL RDY Interrupt
I2C Master Interrupt
Raw Data Ready Interrupt
INTERRUPT PIN
INT1/INT2
INT1
INT1
INT1
INT1
FIFO Overflow Interrupt
INT1
FIFO Watermark Interrupt
INT1
Table 12. Table of Interrupt Sources
For information regarding interrupt registers, please refer to the ICM-20649 Register Map and Register Descriptions sections.
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Revision: 1.1
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ICM-20649
6 DIGITAL INTERFACE
6.1
I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20649 can be accessed using either I2C at 400 kHz or SPI at
7 MHz. SPI operates in four-wire mode.
Pin Number
9
Pin Name
AD0 / SDO
I2C
Pin Description
Slave Address LSB (AD0); SPI serial data output (SDO)
22
23
24
nCS
SCL / SCLK
SDA / SDI
Chip select (SPI mode only)
I2C serial clock (SCL); SPI serial clock (SCLK)
I2C serial data (SDA); SPI serial data input (SDI)
Table 13. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration
bit. Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register
Read/Write” in section 3.3.1.
For further information regarding the I2C_IF_DIS bit, please refer to the ICM-20649 Register Map and Register Descriptions sections.
6.2
I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bidirectional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-20649 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20649 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level
on pin AD0. This allows two ICM-20649s to be connected to the same I2C bus. When used in this configuration, the address of the
one of the devices should be b1101000 (pin AD0 is logic low) and the address of the other should be b1101001 (pin AD0 is logic
high).
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6.3
I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see Figure 8).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to Figure 9).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
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ICM-20649
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1–7
8
9
1–7
8
1–7
9
8
9
S
P
START ADDRESS
condition
R/W
ACK
DATA
ACK
DATA
ACK
STOP
condition
Figure 10. Complete I2C Data Transfer
To write the internal ICM-20649 registers, the master transmits the start condition (S), followed by the I 2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the ICM-20649 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the ICM-20649 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM20649 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master
S
AD+W
Slave
RA
ACK
DATA
ACK
P
ACK
Burst Write Sequence
Master
S
AD+W
Slave
RA
ACK
DATA
ACK
DATA
ACK
P
ACK
To read the internal ICM-20649 registers,
the master sends a start condition, followed by the I 2C address and a write bit, and then the register address that is going to be read.
Upon receiving the ACK signal from the
ICM-20649, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-20649 sends an ACK
signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition
is defined such that the SDA line remains high at the 9th clock cycle. The following figures show single and two-byte read sequences.
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Revision: 1.1
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ICM-20649
Single-Byte Read Sequence
Master
S
AD+W
Slave
RA
ACK
S
AD+R
NACK
ACK
ACK
P
DATA
Burst Read Sequence
Master
S
AD+W
Slave
RA
ACK
S
AD+R
ACK
ACK
ACK
DATA
NACK
P
DATA
6.4 I2C TERMS
SIGNAL
S
AD
W
R
ACK
NACK
RA
DATA
P
DESCRIPTION
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-20649 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 14. I2C Terms
6.5
SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20649 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1.
2.
3.
4.
5.
Data is delivered MSB first and LSB last
Data is latched on the rising edge of SCLK
Data should be transitioned on the falling edge of SCLK
The maximum frequency of SCLK is 7 MHz
SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiplebyte Read/Writes, data is two or more bytes:
SPI Address format
MSB
R/W
A6
A5
A4
A3
A2
A1
LSB
A0
D6
D5
D4
D3
D2
D1
LSB
D0
SPI Data format
MSB
D7
6.
Supports Single or Burst Read/Writes.
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ICM-20649
SCLK
SDI
SDO
SPI Master
/CS1
SPI Slave 1
/CS
/CS2
SCLK
SDI
SDO
/CS
SPI Slave 2
Figure 11. Typical SPI Master / Slave Configuration
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ICM-20649
7 REGISTER MAP
The following table lists the register map for the ICM-20649, for user banks 0, 1, 2, 3.
7.1
USER BANK 0 REGISTER MAP:
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
00
0
WHO_AM_I
R
03
3
USER_CTRL
R/W
05
5
LP_CONFIG
R/W
06
6
PWR_MGMT_1
R/W
07
7
PWR_MGMT_2
R/W
Bit7
Bit6
Bit5
Bit4
DMP_EN
FIFO_EN
I2C_MST_EN
I2C_IF_DIS
I2C_MST_CY
CLE
ACCEL_CYCLE
GYRO_CYCLE
SLEEP
LP_EN
-
INT1_OPEN
INT1_LATCH_
INT_EN
Bit3
Bit1
Bit0
SRAM_RST
I2C_MST_RST
-
WHO_AM_I[7:0]
DEVICE_RESE
T
-
15
INT_PIN_CFG
R/W
INT1_ACTL
10
16
INT_ENABLE
R/W
REG_WOF_E
N
11
17
INT_ENABLE_1
R/W
INT2_ACTL
12
18
INT_ENABLE_2
R/W
-
13
19
INT_ENABLE_3
R/W
PASS_THROU
GH
DMP_RST
TEMP_DIS
CLKSEL[2:0]
DISABLE_ACCEL
0F
-
I2C_MST_STATUS
R/C
19
25
INT_STATUS
R/C
1A
26
INT_STATUS_1
R/C
1B
27
INT_STATUS_2
R/C
-
1C
28
INT_STATUS_3
R/C
-
28
40
DELAY_TIMEH
R
DMP_INT2_E
N
DISABLE_GYRO
ACTL_FSYNC
FSYNC_INT_
MODE_EN
BYPASS_EN
-
WOM_INT_E
N
PLL_RDY_EN
DMP_INT1_E
N
I2C_MST_INT
_EN
RAW_DATA_
0_RDY_EN
FIFO_OVERFLOW_EN[4:0]
FIFO_WM_EN[4:0]
I2C_SLV4_DO
NE
23
INT_ANYRD_
2CLEAR
INT2_LATCH_
EN
INT2_OPEN
17
I2C_LOST_AR
B
I2C_SLV4_NA
CK
-
I2C_SLV3_NA
CK
I2C_SLV2_NA
CK
I2C_SLV1_NA
CK
I2C_SLV0_NA
CK
WOM_INT
PLL_RDY_INT
DMP_INT1
I2C_MST_INT
RAW_DATA_
0_RDY_INT
FIFO_OVERFLOW_INT[4:0]
FIFO_WM_INT[4:0]
DELAY_TIMEH[7:0]
29
41
DELAY_TIMEL
R
DELAY_TIMEL[7:0]
2D
45
ACCEL_XOUT_H
R
ACCEL_XOUT_H[7:0]
2E
46
ACCEL_XOUT_L
R
ACCEL_XOUT_L[7:0]
2F
47
ACCEL_YOUT_H
R
ACCEL_YOUT_H[7:0]
30
48
ACCEL_YOUT_L
R
ACCEL_YOUT_L[7:0]
31
49
ACCEL_ZOUT_H
R
ACCEL_ZOUT_H[7:0]
32
50
ACCEL_ZOUT_L
R
ACCEL_ZOUT_L[7:0]
33
51
GYRO_XOUT_H
R
GYRO_XOUT_H[7:0]
34
52
GYRO_XOUT_L
R
GYRO_XOUT_L[7:0]
35
53
GYRO_YOUT_H
R
GYRO_YOUT_H[7:0]
36
54
GYRO_YOUT_L
R
GYRO_YOUT_L[7:0]
37
55
GYRO_ZOUT_H
R
GYRO_ZOUT_H[7:0]
38
56
GYRO_ZOUT_L
R
GYRO_ZOUT_L[7:0]
39
57
TEMP_OUT_H
R
TEMP_OUT_H[7:0]
3A
58
TEMP_OUT_L
R
TEMP_OUT_L[7:0]
3B
59
EXT_SLV_SENS_DATA_00
R
EXT_SLV_SENS_DATA_00[7:0]
3C
60
EXT_SLV_SENS_DATA_01
R
EXT_SLV_SENS_DATA_01[7:0]
3D
61
EXT_SLV_SENS_DATA_02
R
EXT_SLV_SENS_DATA_02[7:0]
3E
62
EXT_SLV_SENS_DATA_03
R
EXT_SLV_SENS_DATA_03[7:0]
3F
63
EXT_SLV_SENS_DATA_04
R
EXT_SLV_SENS_DATA_04[7:0]
40
64
EXT_SLV_SENS_DATA_05
R
EXT_SLV_SENS_DATA_05[7:0]
41
65
EXT_SLV_SENS_DATA_06
R
EXT_SLV_SENS_DATA_06[7:0]
42
66
EXT_SLV_SENS_DATA_07
R
EXT_SLV_SENS_DATA_07[7:0]
43
67
EXT_SLV_SENS_DATA_08
R
EXT_SLV_SENS_DATA_08[7:0]
44
68
EXT_SLV_SENS_DATA_09
R
EXT_SLV_SENS_DATA_09[7:0]
45
69
EXT_SLV_SENS_DATA_10
R
EXT_SLV_SENS_DATA_10[7:0]
46
70
EXT_SLV_SENS_DATA_11
R
EXT_SLV_SENS_DATA_11[7:0]
47
71
EXT_SLV_SENS_DATA_12
R
EXT_SLV_SENS_DATA_12[7:0]
48
72
EXT_SLV_SENS_DATA_13
R
EXT_SLV_SENS_DATA_13[7:0]
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Revision: 1.1
Bit2
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ICM-20649
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SLV_3_FIFO_
EN
SLV_2_FIFO_
EN
SLV_1_FIFO_
EN
SLV_0_FIFO_
EN
GYRO_Z_FIF
O_EN
GYRO_Y_FIF
O_EN
GYRO_X_FIF
O_EN
TEMP_FIFO_
EN
49
73
EXT_SLV_SENS_DATA_14
R
EXT_SLV_SENS_DATA_14[7:0]
4A
74
EXT_SLV_SENS_DATA_15
R
EXT_SLV_SENS_DATA_15[7:0]
4B
75
EXT_SLV_SENS_DATA_16
R
EXT_SLV_SENS_DATA_16[7:0]
4C
76
EXT_SLV_SENS_DATA_17
R
EXT_SLV_SENS_DATA_17[7:0]
4D
77
EXT_SLV_SENS_DATA_18
R
EXT_SLV_SENS_DATA_18[7:0]
4E
78
EXT_SLV_SENS_DATA_19
R
EXT_SLV_SENS_DATA_19[7:0]
4F
79
EXT_SLV_SENS_DATA_20
R
EXT_SLV_SENS_DATA_20[7:0]
50
80
EXT_SLV_SENS_DATA_21
R
EXT_SLV_SENS_DATA_21[7:0]
51
81
EXT_SLV_SENS_DATA_22
R
EXT_SLV_SENS_DATA_22[7:0]
52
82
EXT_SLV_SENS_DATA_23
R
EXT_SLV_SENS_DATA_23[7:0]
66
102
FIFO_EN_1
R/W
67
103
FIFO_EN_2
R/W
-
68
104
FIFO_RST
R/W
-
FIFO_RESET[4:0]
69
105
FIFO_MODE
R/W
-
FIFO_MODE[4:0]
70
112
FIFO_COUNTH
R
-
71
113
FIFO_COUNTL
R
72
114
FIFO_R_W
R/W
74
116
DATA_RDY_STATUS
R/C
76
7F
118
FIFO_CFG
R/W
127
REG_BANK_SEL
R/W
7.2
Addr
(Hex)
ACCEL_FIFO_
EN
FIFO_CNT[12:8]
FIFO_CNT[7:0]
FIFO_R_W[7:0]
WOF_STATU
S
-
RAW_DATA_RDY[3:0]
-
-
FIFO_CFG
USER_BANK[1:0]
-
USER BANK 1 REGISTER MAP:
Addr
(Dec.)
Register Name
Serial
I/F
Bit7
Bit6
02
2
SELF_TEST_X_GYRO
R/W
XG_ST_DATA[7:0]
03
3
SELF_TEST_Y_GYRO
R/W
YG_ST_DATA[7:0]
04
4
SELF_TEST_Z_GYRO
R/W
ZG_ST_DATA[7:0]
0E
14
SELF_TEST_X_ACCEL
R/W
XA_ST_DATA[7:0]
0F
15
SELF_TEST_Y_ACCEL
R/W
YA_ST_DATA[7:0]
10
16
SELF_TEST_Z_ACCEL
R/W
ZA_ST_DATA[7:0]
14
20
XA_OFFS_H
R/W
XA_OFFS[14:7]
15
21
XA_OFFS_L
R/W
XA_OFFS[6:0]
17
23
YA_OFFS_H
R/W
YA_OFFS[14:7]
18
24
YA_OFFS_L
R/W
YA_OFFS[6:0]
1A
26
ZA_OFFS_H
R/W
ZA_OFFS[14:7]
1B
27
ZA_OFFS_L
R/W
ZA_OFFS[6:0]
28
40
TIMEBASE_CORRECTION_PL
L
R/W
TBC_PLL[7:0]
7F
127
REG_BANK_SEL
R/W
-
7.3
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
USER_BANK[1:0]
-
USER BANK 2 REGISTER MAP:
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
00
0
GYRO_SMPLRT_DIV
R/W
01
1
GYRO_CONFIG_1
R/W
-
02
2
GYRO_CONFIG_2
R/W
-
03
3
XG_OFFS_USRH
R/W
04
4
XG_OFFS_USRL
R/W
X_OFFS_USER[7:0]
05
5
YG_OFFS_USRH
R/W
Y_OFFS_USER[15:8]
06
6
YG_OFFS_USRL
R/W
Y_OFFS_USER[7:0]
07
7
ZG_OFFS_USRH
R/W
Z_OFFS_USER[15:8]
08
8
ZG_OFFS_USRL
R/W
Z_OFFS_USER[7:0]
Document Number: DS-000192
Revision: 1.1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
GYRO_SMPLRT_DIV[7:0]
GYRO_DLPFCFG[2:0]
XGYRO_CTEN
YGYRO_CTEN
GYRO_FS_SEL[1:0]
ZGYRO_CTEN
GYRO_AVGCFG[2:0]
X_OFFS_USER[15:8]
Page 36 of 89
GYRO_FCHOI
CE
ICM-20649
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
09
9
ODR_ALIGN_EN
R/W
10
16
ACCEL_SMPLRT_DIV_1
R/W
11
17
ACCEL_SMPLRT_DIV_2
R/W
12
18
ACCEL_INTEL_CTRL
R/W
13
19
ACCEL_WOM_THR
R/W
14
20
ACCEL_CONFIG
R/W
15
21
ACCEL_CONFIG_2
R/W
52
82
FSYNC_CONFIG
R/W
53
83
TEMP_CONFIG
R/W
54
84
MOD_CTRL_USR
R/W
7F
127
REG_BANK_SEL
R/W
7.4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ODR_ALIGN_
EN
-
ACCEL_SMPLRT_DIV[11:8]
ACCEL_SMPLRT_DIV[7:0]
ACCEL_INTEL
_EN
-
ACCEL_INTEL
_MODE_INT
WOM_THRESHOLD[7:0]
-
ACCEL_DLPFCFG[2:0]
AX_ST_EN_R
EG
DELAY_TIME
_EN
WOF_DEGLIT
CH_EN
-
ACCEL_FCHOI
CE
ACCEL_FS_SEL[1:0]
AY_ST_EN_R
EG
WOF_EDGE_I
NT
AZ_ST_EN_R
EG
DEC3_CFG[1:0]
EXT_SYNC_SET[3:0]
-
TEMP_DLPFCFG[2:0]
REG_LP_DMP
_EN
-
USER_BANK[1:0]
-
USER BANK 3 REGISTER MAP:
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
00
0
I2C_MST_ODR_CONFIG
R/W
Bit7
01
1
I2C_MST_CTRL
R/W
02
2
I2C_MST_DELAY_CTRL
R/W
DELAY_ES_S
HADOW
03
3
I2C_SLV0_ADDR
R/W
I2C_SLV0_RN
W
04
4
I2C_SLV0_REG
R/W
05
5
I2C_SLV0_CTRL
R/W
06
6
I2C_SLV0_DO
R/W
7
I2C_SLV1_ADDR
R/W
08
8
I2C_SLV1_REG
R/W
09
9
I2C_SLV1_CTRL
R/W
0A
10
I2C_SLV1_DO
R/W
0B
11
I2C_SLV2_ADDR
R/W
0C
12
I2C_SLV2_REG
R/W
0D
13
I2C_SLV2_CTRL
R/W
0E
14
I2C_SLV2_DO
R/W
0F
15
I2C_SLV3_ADDR
R/W
10
16
I2C_SLV3_REG
R/W
11
17
I2C_SLV3_CTRL
R/W
12
18
I2C_SLV3_DO
R/W
13
19
I2C_SLV4_ADDR
R/W
14
20
I2C_SLV4_REG
R/W
15
21
I2C_SLV4_CTRL
R/W
16
22
I2C_SLV4_DO
R/W
17
23
I2C_SLV4_DI
R
7F
127
REG_BANK_SEL
R/W
Document Number: DS-000192
Revision: 1.1
Bit5
Bit4
Bit3
MULT_MST_
EN
07
Bit6
Bit2
Bit1
I2C_MST_ODR_CONFIG[3:0]
-
I2C_MST_P_
NSR
-
I2C_SLV4_DE
LAY_EN
I2C_MST_CLK[3:0]
I2C_SLV3_DE
LAY_EN
I2C_SLV2_DE
LAY_EN
I2C_SLV1_DE
LAY_EN
I2C_ID_0[6:0]
I2C_SLV0_REG[7:0]
I2C_SLV0_BY
TE_SW
I2C_SLV0_EN
I2C_SLV0_RE
G_DIS
I2C_SLV0_GR
P
I2C_SLV0_LENG[3:0]
I2C_SLV0_DO[7:0]
I2C_SLV1_RN
W
I2C_ID_1[6:0]
I2C_SLV1_REG[7:0]
I2C_SLV1_BY
TE_SW
I2C_SLV1_EN
I2C_SLV1_RE
G_DIS
I2C_SLV1_GR
P
I2C_SLV1_LENG[3:0]
I2C_SLV1_DO[7:0]
I2C_SLV2_RN
W
I2C_ID_2[6:0]
I2C_SLV2_REG[7:0]
I2C_SLV2_BY
TE_SW
I2C_SLV2_EN
I2C_SLV2_RE
G_DIS
I2C_SLV2_GR
P
I2C_SLV2_LENG[3:0]
I2C_SLV2_DO[7:0]
I2C_SLV3_RN
W
I2C_ID_3[6:0]
I2C_SLV3_REG[7:0]
I2C_SLV3_BY
TE_SW
I2C_SLV3_EN
I2C_SLV3_RE
G_DIS
I2C_SLV3_GR
P
I2C_SLV3_LENG[3:0]
I2C_SLV3_DO[7:0]
I2C_SLV4_RN
W
I2C_ID_4[6:0]
I2C_SLV4_REG[7:0]
I2C_SLV4_BY
TE_SW
I2C_SLV4_EN
I2C_SLV4_RE
G_DIS
I2C_SLV4_DLY[4:0]
I2C_SLV4_DO[7:0]
I2C_SLV4_DI[7:0]
-
Bit0
USER_BANK[1:0]
-
Page 37 of 89
I2C_SLV0_DE
LAY_EN
ICM-20649
8 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the ICM-20649.
Note: The device will come up in sleep mode upon power-up.
8.1
USR BANK 0 REGISTER MAP
WHO_AM_I
Name: WHO_AM_I
Address: 0 (00h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0xE1
BIT
7:0
NAME
WHO_AM_I[7:0]
FUNCTION
Register to indicate to user which device is being accessed.
The value for ICM-20649 is 0xE1
USER_CTRL
Name: USER_CTRL
Address: 3 (03h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7
DMP_EN
NAME
6
FIFO_EN
5
I2C_MST_EN
4
3
I2C_IF_DIS
DMP_RST
2
SRAM_RST
1
I2C_MST_RST
FUNCTION
1 – Enables DMP features.
0 – DMP features are disabled after the current processing round has completed.
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
To disable FIFO writes by DMA, use FIFO_EN register.
To disable possible FIFO writes from DMP, disable the DMP.
1 – Enable the I2C Master I/F module; pins ES_DA and ES_SCL are isolated from pins
SDA/SDI and SCL/ SCLK.
0 – Disable I2C Master I/F module; pins ES_DA and ES_SCL are logically driven by pins
SDA/SDI and SCL/ SCLK.
1 – Reset I2C Slave module and put the serial interface in SPI mode only.
1 – Reset DMP module. Reset is asynchronous. This bit auto clears after one clock cycle of
the internal 20 MHz clock.
1 – Reset SRAM module. Reset is asynchronous. This bit auto clears after one clock cycle of
the internal 20 MHz clock.
1 – Reset I2C Master module. Reset is asynchronous. This bit auto clears after one clock
cycle of the internal 20 MHz clock.
Note: This bit should only be set when the I2C master has hung. If this bit is set during an active I2C
master transaction, the I2C slave will hang, which will require the host to reset the slave.
0
-
Document Number: DS-000192
Revision: 1.1
Reserved.
Page 38 of 89
ICM-20649
LP_CONFIG
Name: LP_CONFIG
Address: 5 (05h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x40
BIT
7
6
NAME
I2C_MST_CYCLE
5
ACCEL_CYCLE
4
GYRO_CYCLE
3:0
-
FUNCTION
Reserved.
1 - Operate I2C master in duty cycled mode. ODR is determined by
I2C_MST_ODR_CONFIG register.
0 – Disable I2C master duty cycled mode.
1 – Operate ACCEL in duty cycled mode. ODR is determined by ACCEL_SMPLRT_DIV
register.
0 – Disable ACCEL duty cycled mode.
1 – Operate GYRO in duty cycled mode. ODR is determined by GYRO_SMPLRT_DIV
register.
0 – Disable GYRO duty cycled mode.
Reserved.
PWR_MGMT_1
Name: PWR_MGMT_1
Address: 6 (06h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x41
BIT
NAME
FUNCTION
7
DEVICE_RESET
6
SLEEP
5
LP_EN
4
3
2:0
TEMP_DIS
CLKSEL[2:0]
1 – Reset the internal registers and restores the default settings. Write a 1 to set the reset;
the bit will auto clear.
When set, the chip is set to sleep mode (in sleep mode all analog is powered off).
Clearing the bit wakes the chip from sleep mode.
The LP_EN only affects the digital circuitry, it helps to reduce the digital current when sensors
are in LP mode. Please note that the sensors themselves are set in LP mode by the
LP_CONFIG register settings. Sensors in LP mode, and use of LP_EN bit together help to
reduce overall current. The bit settings are:
1: Turn on low power feature.
0: Turn off low power feature.
LP_EN has no effect when the sensors are in low-noise mode.
Reserved.
When set to 1, this bit disables the temperature sensor.
Document Number: DS-000192
Revision: 1.1
Code
Clock Source
0
Internal 20 MHz oscillator
1-5
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
6
Internal 20 MHz oscillator
7
Stops the clock and keeps timing generator in reset
Note: CLKSEL[2:0] should be set to 1~5 to achieve full gyroscope performance.
Page 39 of 89
ICM-20649
PWR_MGMT_2
Name: PWR_MGMT_2
Address: 7 (07h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:6
5:3
NAME
DISABLE_ACCEL
2:0
DISABLE_GYRO
FUNCTION
Reserved.
Only the following values are applicable:
111 – Accelerometer (all axes) disabled.
000 – Accelerometer (all axes) on.
Only the following values are applicable:
111 – Gyroscope (all axes) disabled.
000 – Gyroscope (all axes) on.
INT_PIN_CFG
Name: INT_PIN_CFG
Address: 15 (0Fh)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7
INT1_ACTL
NAME
6
INT1_OPEN
5
INT1_LATCH__EN
4
INT_ANYRD_2CLEAR
3
ACTL_FSYNC
2
FSYNC_INT_MODE_EN
1
BYPASS_EN
0
-
Document Number: DS-000192
Revision: 1.1
FUNCTION
1 – The logic level for INT1 pin is active low.
0 – The logic level for INT1 pin is active high.
1 – INT1 pin is configured as open drain.
0 – INT1 pin is configured as push-pull.
1 – INT1 pin level held until interrupt status is cleared.
0 – INT1 pin indicates interrupt pulse is width 50 µs.
1 – Interrupt status in INT_STATUS is cleared (set to 0) if any read operation is
performed.
0 – Interrupt status in INT_STATUS is cleared (set to 0) only by reading INT_STATUS
register.
This bit only affects the interrupt status bits that are contained in the register
INT_STATUS, and the corresponding hardware interrupt.
This bit does not affect the interrupt status bits that are contained in registers
INT_STATUS_1, INT_STATUS_2, INT_STATUS_3, and the corresponding hardware
interrupt.
1 – The logic level for the FSYNC pin as an interrupt to the ICM-20649 is active low.
0 – The logic level for the FSYNC pin as an interrupt to the ICM-20649 is active high.
1 – This enables the FSYNC pin to be used as an interrupt. A transition to the active
level described by the ACTL_FSYNC bit will cause an interrupt. The status of the
interrupt is read in the I2C Master Status register PASS_THROUGH bit.
0 – This disables the FSYNC pin from causing an interrupt.
When asserted, the I2C_MASTER interface pins (ES_CL and ES_DA) will go into
‘bypass mode’ when the I2C master interface is disabled.
Reserved.
Page 40 of 89
ICM-20649
INT_ENABLE
Name: INT_ENABLE
Address: 16 (10h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
REG_WOF_EN
6:5
4
DMP_INT2_EN
3
WOM_INT_EN
2
PLL_RDY_EN
1
DMP_INT1_EN
0
I2C_MST_INT_EN
FUNCTION
1 – Enable wake on FSYNC interrupt
0 – Function is disabled.
Reserved
1 – Enable DMP interrupt to propagate to interrupt pin 2.
0 – Function is disabled.
1 – Enable interrupt for wake on motion to propagate to interrupt pin 1.
0 – Function is disabled.
1 – Enable PLL RDY interrupt (PLL RDY means PLL is running and in use as the
clock source for the system) to propagate to interrupt pin 1.
0 – Function is disabled.
1 – Enable DMP interrupt to propagate to interrupt pin 1.
0 – Function is disabled.
1 – Enable I2C master interrupt to propagate to interrupt pin 1.
0 – Function is disabled.
INT_ENABLE_1
Name: INT_ENABLE_1
Address: 17 (11h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7
INT2_ACTL
NAME
6
INT2_OPEN
5
INT2_LATCH_EN
4:1
0
RAW_DATA_0_RDY_EN
FUNCTION
1 – The logic level for INT2 pin is active low.
0 – The logic level for INT2 pin is active high.
1 – INT2 pin is configured as open drain.
0 – INT2 pin is configured as push-pull.
1 – INT2 pin level held until interrupt status is cleared.
0 – INT2 pin indicates interrupt pulse is width 50 µs.
Reserved.
1 – Enable raw data ready interrupt from any sensor to propagate to interrupt pin 1.
0 – Function is disabled.
INT_ENABLE_2
Name: INT_ENABLE_2
Address: 18 (12h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_OVERFLOW_EN[4:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
1 – Enable interrupt for FIFO overflow to propagate to interrupt pin 1.
0 – Function is disabled.
Page 41 of 89
ICM-20649
INT_ENABLE_3
Name: INT_ENABLE_3
Address: 19 (13h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_WM_EN[4:0]
FUNCTION
Reserved.
1 – Enable interrupt for FIFO watermark to propagate to interrupt pin 1.
0 – Function is disabled.
I2C_MST_STATUS
Name: I2C_MST_STATUS
Address: 23 (17h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
7
NAME
PASS_THROUGH
6
I2C_SLV4_DONE
5
I2C_LOST_ARB
4
I2C_SLV4_NACK
3
I2C_SLV3_NACK
2
I2C_SLV2_NACK
1
I2C_SLV1_NACK
0
I2C_SLV0_NACK
FUNCTION
Status of FSYNC interrupt – used as a way to pass an external interrupt through this
chip to the host. If enabled in the INT_PIN_CFG register by asserting bit
FSYNC_INT_MODE_EN, this will cause an interrupt. A read of this register clears all
status bits in this register.
Asserted when I2C slave 4’s transfer is complete, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted, and if the
SLV4_DONE_INT_EN bit is asserted in the I2C_SLV4_CTRL register.
Asserted when I2C slave loses arbitration of the I2C bus, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
Asserted when slave 4 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 3 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 2 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 1 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 0 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
INT_STATUS
Name: INT_STATUS
Address: 25 (19h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
7:4
3
2
1
0
NAME
WOM_INT
PLL_RDY_INT
DMP_INT1
I2C_MST_INT
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
1 – Wake on motion interrupt occurred.
1 – Indicates that the PLL has been enabled and is ready (delay of 4 ms ensures lock).
1 – Indicates the DMP has generated INT1 interrupt.
1 - Indicates I2C master has generated an interrupt.
Page 42 of 89
ICM-20649
12.1.13 INT_STATUS_1
Name: INT_STATUS_1
Address: 26 (1Ah)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7:1
0
RAW_DATA_0_RDY_INT
FUNCTION
Reserved.
1 – Sensor Register Raw Data, from all sensors, is updated and ready to be
read.
INT_STATUS_2
Name: INT_STATUS_2
Address: 27 (1Bh)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_OVERFLOW_INT[4:0]
FUNCTION
Reserved.
1 – FIFO Overflow interrupt occurred.
INT_STATUS_3
Name: INT_STATUS_3
Address: 28 (1Ch)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_WM_INT[4:0]
FUNCTION
Reserved.
1 – Watermark interrupt for FIFO occurred.
DELAY_TIMEH
Name: DELAY_TIMEH
Address: 40 (28h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
DELAY_TIMEH[7:0]
FUNCTION
High-byte of delay time between FSYNC event and the 1st gyro ODR event (after the
FSYNC event).
Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next
update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take
the next update due to an FSYNC event.
Document Number: DS-000192
Revision: 1.1
Page 43 of 89
ICM-20649
DELAY_TIMEL
Name: DELAY_TIMEL
Address: 41 (29h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
DELAY_TIMEL[7:0]
FUNCTION
Low-byte of delay time between FSYNC event and the 1st gyro ODR event (after the
FSYNC event).
Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next
update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take
the next update due to an FSYNC event.
Delay time in µs = (DELAY_TIMEH * 256 + DELAY_TIMEL) * 0.9645
ACCEL_XOUT_H
Name: ACCEL_XOUT_H
Address: 45 (2Dh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_XOUT_H[7:0]
FUNCTION
High Byte of Accelerometer X-axis data.
ACCEL_XOUT_L
Name: ACCEL_XOUT_L
Address: 46 (2Eh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_XOUT_L[7:0]
FUNCTION
Low Byte of Accelerometer X-axis data.
To convert the output of the accelerometer to acceleration measurement use the
formula below:
X_acceleration = ACCEL_XOUT/Accel_Sensitivity
ACCEL_YOUT_H
Name: ACCEL_YOUT_H
Address: 47 (2Fh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_YOUT_H[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
High Byte of Accelerometer Y-axis data.
Page 44 of 89
ICM-20649
ACCEL_YOUT_L
Name: ACCEL_YOUT_L
Address: 48 (30h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_YOUT_L[7:0]
FUNCTION
Low Byte of Accelerometer Y-axis data
To convert the output of the accelerometer to acceleration measurement use the
formula below:
Y_acceleration = ACCEL_YOUT/Accel_Sensitivity
ACCEL_ZOUT_H
Name: ACCEL_ZOUT_H
Address: 49 (31h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_ZOUT_H[7:0]
FUNCTION
High Byte of Accelerometer Z-axis data.
ACCEL_ZOUT_L
Name: ACCEL_ZOUT_L
Address: 50 (32h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_ZOUT_L[7:0]
FUNCTION
Low Byte of Accelerometer Z-axis data.
To convert the output of the accelerometer to acceleration measurement use the
formula below:
Z_acceleration = ACCEL_ZOUT/Accel_Sensitivity
GYRO_XOUT_H
Name: GYRO_XOUT_H
Address: 51 (33h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
GYRO_XOUT_H[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
High Byte of Gyroscope X-axis data.
Page 45 of 89
ICM-20649
GYRO_XOUT_L
Name: GYRO_XOUT_L
Address: 52 (34h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
GYRO_XOUT_L[7:0]
FUNCTION
Low Byte of Gyroscope X-axis data.
To convert the output of the gyroscope to angular rate measurement use the
formula below:
X_angular_rate = GYRO_XOUT/Gyro_Sensitivity
GYRO_YOUT_H
Name: GYRO_YOUT_H
Address: 53 (35h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
GYRO_YOUT_H[7:0]
FUNCTION
High Byte of Gyroscope Y-axis data.
GYRO_YOUT_L
Name: GYRO_YOUT_L
Address: 54 (36h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
GYRO_YOUT_L[7:0]
FUNCTION
Low Byte of Gyroscope Y-axis data.
To convert the output of the gyroscope to angular rate measurement use the
formula below:
Y_angular_rate = GYRO_YOUT/Gyro_Sensitivity
GYRO_ZOUT_H
Name: GYRO_ZOUT_H
Address: 55 (37h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
GYRO_ZOUT_H[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
High Byte of Gyroscope Z-axis data.
Page 46 of 89
ICM-20649
GYRO_ZOUT_L
Name: GYRO_ZOUT_L
Address: 56 (38h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
GYRO_ZOUT_L[7:0]
FUNCTION
Low Byte of Gyroscope Z-axis data.
To convert the output of the gyroscope to angular rate measurement use the
formula below:
Z_angular_rate = GYRO_ZOUT/Gyro_Sensitivity
TEMP_OUT_H
Name: TEMP_OUT_H
Address: 57 (39h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
TEMP_OUT_H[7:0]
FUNCTION
High Byte of Temp sensor data.
TEMP_OUT_L
Name: TEMP_OUT_L
Address: 58 (3Ah)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
TEMP_OUT_L[7:0]
FUNCTION
Low Byte of Temp sensor data.
To convert the output of the temperature sensor to degrees C use the following
formula:
TEMP_degC = ((TEMP_OUT – RoomTemp_Offset)/Temp_Sensitivity) + 21degC
EXT_SLV_SENS_DATA_00
Name: EXT_SLV_SENS_DATA_00
Address: 59 (3Bh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_00[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 47 of 89
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EXT_SLV_SENS_DATA_01
Name: EXT_SLV_SENS_DATA_01
Address: 60 (3Ch)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_01[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_02
Name: EXT_SLV_SENS_DATA_02
Address: 61 (3Dh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_02[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_03
Name: EXT_SLV_SENS_DATA_03
Address: 62 (3Eh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_03[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_04
Name: EXT_SLV_SENS_DATA_04
Address: 63 (3Fh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_04[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 48 of 89
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EXT_SLV_SENS_DATA_05
Name: EXT_SLV_SENS_DATA_05
Address: 64 (40h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_05[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_06
Name: EXT_SLV_SENS_DATA_06
Address: 65 (41h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_06[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_07
Name: EXT_SLV_SENS_DATA_07
Address: 66 (42h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_07[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_08
Name: EXT_SLV_SENS_DATA_08
Address: 67 (43h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_08[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 49 of 89
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EXT_SLV_SENS_DATA_09
Name: EXT_SLV_SENS_DATA_09
Address: 68 (44h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_09[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_10
Name: EXT_SLV_SENS_DATA_10
Address: 69 (45h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_10[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_11
Name: EXT_SLV_SENS_DATA_11
Address: 70 (46h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
FUNCTION
7:0
EXT_SLV_SENS_DATA_11[7:0]
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_12
Name: EXT_SLV_SENS_DATA_12
Address: 71 (47h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_12[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 50 of 89
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EXT_SLV_SENS_DATA_13
Name: EXT_SLV_SENS_DATA_13
Address: 72 (48h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_13[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
EXT_SLV_SENS_DATA_14
Name: EXT_SLV_SENS_DATA_14
Address: 73 (49h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_14[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_15
Name: EXT_SLV_SENS_DATA_15
Address: 74 (4Ah)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_15[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_16
Name: EXT_SLV_SENS_DATA_16
Address: 75 (4Bh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_16[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 51 of 89
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EXT_SLV_SENS_DATA_17
Name: EXT_SLV_SENS_DATA_17
Address: 76 (4Ch)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_17[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_18
Name: EXT_SLV_SENS_DATA_18
Address: 77 (4Dh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_18[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_19
Name: EXT_SLV_SENS_DATA_19
Address: 78 (4Eh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_19[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_20
Name: EXT_SLV_SENS_DATA_20
Address: 79 (4Fh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_20[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
Page 52 of 89
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EXT_SLV_SENS_DATA_21
Name: EXT_SLV_SENS_DATA_21
Address: 80 (50h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_21[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_22
Name: EXT_SLV_SENS_DATA_22
Address: 81 (51h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
EXT_SLV_SENS_DATA_22[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface.
The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(04)_REG, and I2C_SLV(0-4)_CTRL registers.
EXT_SLV_SENS_DATA_23
Name: EXT_SLV_SENS_DATA_23
Address: 82 (52h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
FUNCTION
7:0
EXT_SLV_SENS_DATA_23[7:0]
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG,
and I2C_SLV(0-4)_CTRL registers.
Document Number: DS-000192
Revision: 1.1
Page 53 of 89
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FIFO_EN_1
Name: FIFO_EN_1
Address: 102 (66h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:4
3
NAME
SLV_3_FIFO_EN
2
SLV_2_FIFO_EN
1
SLV_1_FIFO_EN
0
SLV_0_FIFO_EN
FUNCTION
Reserved.
1 – Write EXT_SENS_DATA registers associated to SLV_3 (as determined by
I2C_SLV2_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write EXT_SENS_DATA registers associated to SLV_2 (as determined by
I2C_SLV0_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write EXT_SENS_DATA registers associated to SLV_1 (as determined by
I2C_SLV0_CTRL and I2C_SLV1_CTRL) to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write EXT_SENS_DATA registers associated to SLV_0 (as determined by
I2C_SLV0_CTRL) to the FIFO at the sample rate.
0 – Function is disabled.
FIFO_EN_2
Name: FIFO_EN_2
Address: 103 (67h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:5
4
NAME
ACCEL_FIFO_EN
3
GYRO_Z_FIFO_EN
2
GYRO_Y_FIFO_EN
1
GYRO_X_FIFO_EN
0
TEMP_FIFO_EN
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,
ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate.
0– Function is disabled.
Page 54 of 89
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FIFO_RST
Name: FIFO_RST
Address: 104 (68h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_RESET[4:0]
FUNCTION
Reserved.
S/W FIFO reset. Assert and hold to set FIFO size to 0. Assert and de-assert to reset
FIFO.
FIFO_MODE
Name: FIFO_MODE
Address: 105 (69h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_MODE[4:0]
FUNCTION
Reserved.
0 - Stream
1 - Snapshot
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO,
replacing the oldest data.
FIFO_COUNTH
Name: FIFO_COUNTH
Address: 112 (70h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:5
4:0
NAME
FIFO_CNT[12:8]
FUNCTION
Reserved.
High Bits, count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
FIFO_COUNTL
Name: FIFO_COUNTL
Address: 113 (71h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
FIFO_CNT[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Low bits, count indicates the number of written bytes in the FIFO.
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FIFO_R_W
Name: FIFO_R_W
Address: 114 (72h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
FIFO_R_W[7:0]
FUNCTION
Reading from or writing to this register actually reads/writes the FIFO. For example,
to write a byte to the FIFO, write the desired byte value to FIFO_R_W[7:0]. To read a
byte from the FIFO, perform a register read operation and access the result in
FIFO_R_W[7:0].
DATA_RDY_STATUS
Name: DATA_RDY_STATUS
Address: 116 (74h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
7
6:4
3:0
NAME
WOF_STATUS
RAW_DATA_RDY[3:0]
FUNCTION
Wake on FSYNC interrupt status. Cleared on read.
Reserved.
Data from sensors is copied to FIFO or SRAM.
Set when sequence controller kicks off on a sensor data load. Only bit 0 is relevant in
a single FIFO configuration. Cleared on read.
FIFO_CFG
Name: FIFO_CFG
Address: 118 (76h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:1
0
NAME
FIFO_CFG
FUNCTION
Reserved.
This bit should be set to 1 if interrupt status for each sensor is required.
REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type: ALL
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
7:6
5:4
NAME
USER_BANK[1:0]
3:0
-
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK.
0: Select USER BANK 0
1: Select USER BANK 1
2: Select USER BANK 2
3: Select USER BANK 3
Reserved.
Page 56 of 89
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8.2
USR BANK 1 REGISTER MAP
SELF_TEST_X_GYRO
Name: SELF_TEST_X_GYRO
Address: 2 (02h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
XG_ST_DATA[7:0]
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against subsequent self-test
outputs performed by the end user.
SELF_TEST_Y_GYRO
Name: SELF_TEST_Y_GYRO
Address: 3 (03h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
YG_ST_DATA[7:0]
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against subsequent self-test
outputs performed by the end user.
SELF_TEST_Z_GYRO
Name: SELF_TEST_Z_GYRO
Address: 4 (04h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
ZG_ST_DATA[7:0]
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against subsequent self-test
outputs performed by the end user.
SELF_TEST_X_ACCEL
Name: SELF_TEST_X_ACCEL
Address: 14 (0Eh)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
XA_ST_DATA[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Contains self-test data for the X Accelerometer.
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SELF_TEST_Y_ACCEL
Name: SELF_TEST_Y_ACCEL
Address: 15 (0Fh)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
YA_ST_DATA[7:0]
FUNCTION
Contains self-test data for the Y Accelerometer.
SELF_TEST_Z_ACCEL
Name: SELF_TEST_Z_ACCEL
Address: 16 (10h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
ZA_ST_DATA[7:0]
FUNCTION
Contains self-test data for the Z Accelerometer.
XA_OFFS_H
Name: XA_OFFS_H
Address: 20 (14h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
7:0
NAME
XA_OFFS[14:7]
FUNCTION
Upper bits of the X accelerometer offset cancellation.
XA_OFFS_L
Name: XA_OFFS_L
Address: 21 (15h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
7:1
0
NAME
XA_OFFS[6:0]
-
FUNCTION
Lower bits of the X accelerometer offset cancellation.
Reserved.
YA_OFFS_H
Name: YA_OFFS_H
Address: 23 (17h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
7:0
NAME
YA_OFFS[14:7]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Upper bits of the Y accelerometer offset cancellation.
Page 58 of 89
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YA_OFFS_L
Name: YA_OFFS_L
Address: 24 (18h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
7:1
0
NAME
YA_OFFS[6:0]
-
FUNCTION
Lower bits of the Y accelerometer offset cancellation.
Reserved.
ZA_OFFS_H
Name: ZA_OFFS_H
Address: 26 (1Ah)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
7:0
NAME
ZA_OFFS[14:7]
FUNCTION
Upper bits of the Z accelerometer offset cancellation.
ZA_OFFS_L
Name: ZA_OFFS_L
Address: 27 (1Bh)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
7:1
0
NAME
ZA_OFFS[6:0]
-
FUNCTION
Lower bits of the Z accelerometer offset cancellation.
Reserved.
TIMEBASE_CORRECTION_PLL
Name: TIMEBASE_CORRECTION_PLL
Address: 40 (28h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
TBC_PLL[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
System PLL clock period error (signed, [-10%, +10%]).
Page 59 of 89
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REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type:
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
7:6
5:4
NAME
USER_BANK[1:0]
3:0
-
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK
0: Select USER BANK 0
1: Select USER BANK 1
2: Select USER BANK 2
3: Select USER BANK 3
Reserved.
Page 60 of 89
ICM-20649
8.3
USR BANK 2 REGISTER MAP
GYRO_SMPLRT_DIV
Name: GYRO_SMPLRT_DIV
Address: 0 (00h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
GYRO_SMPLRT_DIV[7:0]
FUNCTION
Gyro sample rate divider. Divides the internal sample rate to generate the sample
rate that controls sensor data output rate, FIFO sample rate, and DMP sequence
rate.
Note: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0),
and (0 < DLPF_CFG < 7).
ODR is computed as follows:
1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])
GYRO_CONFIG_1
Name: GYRO_CONFIG_1
Address: 1 (01h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x01
BIT
7:6
5:3
2:1
NAME
GYRO_DLPFCFG[2:0]
GYRO_FS_SEL[1:0]
0
GYRO_FCHOICE
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Gyro low pass filter configuration as shown in Table 15.
Gyro Full Scale Select:
00 = ±500 dps
01= ±1000 dps
10 = ±2000 dps
11 = ±4000 dps
0 – Bypass gyro DLPF.
1 – Enable gyro DLPF.
Page 61 of 89
ICM-20649
The gyroscope DLPF is configured by GYRO_DLPFCFG, when GYRO_FCHOICE = 1. The gyroscope data is filtered according to the value
of GYRO_DLPFCFG and GYRO_FCHOICE as shown in Table 15.
Output
GYRO_FCHOICE
GYRO_DLPFCFG
0
x
3dB BW
[Hz]
12106
NBW [Hz]
Rate [Hz]
12316
1
0
196.6
229.8
1
1
151.8
187.6
1
2
119.5
154.3
1
3
51.2
73.3
1
4
23.9
35.9
1
5
11.6
17.8
1
6
5.7
8.9
1
7
361.4
376.5
9000
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz
where GYRO_SMPLRT_DIV is 0, 1, 2,…255
Table 15. Configuration
GYRO_CONFIG_2
Name: GYRO_CONFIG_2
Address: 2 (02h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:6
5
4
3
2:0
NAME
XGYRO_CTEN
YGYRO_CTEN
ZGYRO_CTEN
GYRO_AVGCFG[2:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
X Gyro self-test enable.
Y Gyro self-test enable.
Z Gyro self-test enable.
Averaging filter configuration settings for low-power mode.
0: 1x averaging
1: 2x averaging
2: 4x averaging
3: 8x averaging
4: 16x averaging
5: 32x averaging
6: 64x averaging
7: 128x averaging
Page 62 of 89
ICM-20649
Table 16 lists the gyroscope filter bandwidths available in the low-power mode of operation. In the low-power mode of operation,
the gyroscope is duty-cycled.
Averages
1x
2x
4x
8x
16x
32x
64x
128x
GYRO_FCHOICE
1
1
1
1
1
1
1
1
GYRO_AVGCFG
0
1
2
3
4
5
6
7
Ton [ms]
1.15
1.59
2.48
4.26
7.82
14.93
29.15
57.59
NBW [Hz]
773.5
469.8
257.8
134.8
68.9
34.8
17.5
8.8
RMS Noise
[dps-rms] TYP
(based on gyroscope
noise: 0.0175dps/Hz)
0.49
0.38
0.28
0.20
0.15
0.10
0.07
0.05
GYRO_SMPLRT_DIV
ODR [Hz]
Current Consumption [mA] TYP
255
4.4
1.04
1.05
1.05
1.06
1.09
1.14
1.24
1.45
64
17.3
1.07
1.08
1.10
1.15
1.25
1.45
1.85
N/A
63
17.6
1.07
1.08
1.11
1.16
1.26
1.46
1.87
32
34.1
1.10
1.12
1.17
1.27
1.47
1.86
31
35.2
1.10
1.13
1.18
1.28
1.48
1.89
22
48.9
1.13
1.16
1.23
1.37
1.66
2.22
16
66.2
1.16
1.21
1.30
1.49
1.88
15
70.3
1.17
1.22
1.32
1.52
1.93
10
102.3
1.23
1.30
1.45
1.74
2.34
8
125.0
1.27
1.36
1.54
1.90
7
140.6
1.30
1.40
1.60
2.01
5
187.5
1.38
1.52
1.79
2.33
4
225.0
1.45
1.62
1.94
3
281.3
1.56
1.76
2.17
2
375.0
1.74
2.00
1
562.5
2.09
N/A
N/A
N/A
N/A
N/A
N/A
Table 16. Gyroscope Filter Bandwidths (Low-Power Mode)
Note: Ton is the ON time for motion measurement when the gyroscope is in duty cycle mode.
XG_OFFS_USRH
Name: XG_OFFS_USRH
Address: 3 (03h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
X_OFFS_USER[15:8]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Upper byte of X gyro offset cancellation.
Page 63 of 89
ICM-20649
XG_OFFS_USRL
Name: XG_OFFS_USRL
Address: 4 (04h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
X_OFFS_USER[7:0]
FUNCTION
Lower byte of X gyro offset cancellation.
YG_OFFS_USRH
Name: YG_OFFS_USRH
Address: 5 (05h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
Y_OFFS_USER[15:8]
FUNCTION
Upper byte of Y gyro offset cancellation.
YG_OFFS_USRL
Name: YG_OFFS_USRL
Address: 6 (06h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
Y_OFFS_USER[7:0]
FUNCTION
Lower byte of Y gyro offset cancellation.
ZG_OFFS_USRH
Name: ZG_OFFS_USRH
Address: 7 (07h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
Z_OFFS_USER[15:8]
FUNCTION
Upper byte of Z gyro offset cancellation.
ZG_OFFS_USRL
Name: ZG_OFFS_USRL
Address: 8 (08h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
Z_OFFS_USER[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Lower byte of Z gyro offset cancellation.
Page 64 of 89
ICM-20649
ODR_ALIGN_EN
Name: ODR_ALIGN_EN
Address: 9 (09h)
Type: USR2
Bank: 2
OTP: No
Serial IF: R/W
Reset Value: 0x00
BIT
7:1
0
NAME
ODR_ALIGN_EN
FUNCTION
Reserved.
0: Disables ODR start-time alignment.
1: Enables ODR start-time alignment when any of the following registers is written
(with the same value or with different values): GYRO_SMPLRT_DIV,
ACCEL_SMPLRT_DIV_1, ACCEL_SMPLRT_DIV_2, I2C_MST_ODR_CONFIG
ACCEL_SMPLRT_DIV_1
Name: ACCEL_SMPLRT_DIV_1
Address: 16 (10h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:4
3:0
NAME
ACCEL_SMPLRT_DIV[11:8]
FUNCTION
Reserved.
MSB for ACCEL sample rate div.
ACCEL_SMPLRT_DIV_2
Name: ACCEL_SMPLRT_DIV_2
Address: 17 (11h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
ACCEL_SMPLRT_DIV[7:0]
FUNCTION
LSB for ACCEL sample rate div.
ODR is computed as follows:
1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0])
ACCEL_INTEL_CTRL
Name: ACCEL_INTEL_CTRL
Address: 18 (12h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:2
1
0
NAME
ACCEL_INTEL_EN
ACCEL_INTEL_MODE_INT
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Enable the WOM logic.
Selects WOM algorithm.
1- Compare the current sample with the previous sample.
0 - Initial sample is stored, all future samples are compared to the initial
sample
Page 65 of 89
ICM-20649
ACCEL_WOM_THR
Name: ACCEL_WOM_THR
Address: 19 (13h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
WOM_THRESHOLD[7:0]
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for ACCEL
x/y/z axes. LSB = 4 mg. Range is 0 mg to 1020 mg
ACCEL_CONFIG
Name: ACCEL_CONFIG
Address: 20 (14h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x01
BIT
7:6
5:3
2:1
NAME
ACCEL_DLPFCFG[2:0]
ACCEL_FS_SEL[1:0]
0
ACCEL_FCHOICE
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Accelerometer low pass filter configuration as shown in Table 17.
Accelerometer Full Scale Select:
00: ±4g
01: ±8g
10: ±16g
11: ±30g
0 - Bypass accel DLPF.
1 - Enable accel DLPF.
Page 66 of 89
ICM-20649
Output
ACCEL_FCHOICE
ACCEL_DLPFCFG
0
x
3dB
BW
[Hz]
1209
NBW [Hz]
Rate [Hz]
1248
1
0
246.0
265.0
1
1
246.0
265.0
1
2
111.4
136.0
1
3
50.4
68.8
1
4
23.9
34.4
1
5
11.5
17.0
1
6
5.7
8.3
1
7
473
499
4500
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
Table 17. Accelerometer Configuration
The data rate out of the DLPF filter block can be further reduced by a factor of 1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0]) where
ACCEL_SMPLRT_DIV is a 12-bit integer.
ACCEL_CONFIG_2
Name: ACCEL_CONFIG_2
Address: 21 (15h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:5
4
3
2
1:0
NAME
AX_ST_EN_REG
AY_ST_EN_REG
AZ_ST_EN_REG
DEC3_CFG[1:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
X Accel self-test enable.
Y Accel self-test enable.
Z Accel self-test enable.
Controls the number of samples averaged in the accelerometer decimator:
0: Average 1 or 4 samples depending on ACCEL_FCHOICE (see table below)
1 - Average 8 samples.
2 - Average 16 samples.
3 - Average 32 samples.
Page 67 of 89
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Table 18 lists the accelerometer filter bandwidths available in the low-power mode of operation. In the low-power mode of
operation, the accelerometer is duty-cycled.
Averages
1x
4x
8x
16x
32x
ACCEL_FCHOICE
0
1
1
1
1
ACCEL_DLPFCFG
x
7
7
7
7
DEC3_CFG
0
0
1
2
3
Ton (ms)
0.821
1.488
2.377
4.154
7.71
NBW (Hz)
1237.5
496.8
264.8
136.5
69.2
RMS Noise
[mg-rms] TYP
(based on accelerometer
noise: 285µg/Hz)
10.0
6.4
4.6
3.3
2.4
ACCEL_SMPLRT_DIV
ODR [Hz]
4095
0.27
6.2
6.3
6.5
6.9
7.6
2044
0.55
6.3
6.6
7.0
7.7
9.2
1022
1.1
6.7
7.2
8.0
9.4
12.3
513
2.2
7.3
8.4
9.9
12.8
18.6
255
4.4
8.7
10.9
13.8
19.7
31.4
127
8.8
11.4
15.8
21.6
33.3
56.7
63
17.6
16.8
25.6
37.3
60.7
107.5
31
35.2
27.6
45.2
68.6
115.3
208.9
22
48.9
36.1
60.5
93.0
158.1
288.3
15
70.3
49.2
84.3
131.1
224.7
411.9
10
102.3
68.9
119.9
188.0
324.1
596.3
7
140.6
92.4
162.7
256.3
443.3
N/A
5
187.5
121.2
214.9
3
281.3
178.9
319.3
1
562.5
351.7
Current Consumption [mA] TYP
N/A
N/A
Table 18. Accelerometer Configuration 2
Note: Ton is the ON time for motion measurement when the accelerometer is in duty cycle mode.
Document Number: DS-000192
Revision: 1.1
Page 68 of 89
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FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 82 (52h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
DELAY_TIME_EN
6
5
4
WOF_DEGLITCH_EN
WOF_EDGE_INT
3:0
EXT_SYNC_SET[3:0]
FUNCTION
0 - Disables delay time measurement between FSYNC event and the first ODR event
(after FSYNC event).
1 - Enables delay time measurement between FSYNC event and the first ODR event
(after FSYNC event).
Reserved.
Enables digital deglitching of FSYNC input for Wake on FSYNC.
0 - FSYNC is a level interrupt for Wake on FSYNC.
1 - FSYNC is an edge interrupt for Wake on FSYNC.
ACTL_FSYNC is used to set the polarity of the interrupt.
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET FSYNC bit location.
0 - Function disabled
1 - TEMP_OUT_L[0]
2 - GYRO_XOUT_L[0]
3 - GYRO_YOUT_L[0]
4 - GYRO_ZOUT_L[0]
5 - ACCEL_XOUT_L[0]
6 - ACCEL_YOUT_L[0]
7 - ACCEL_ZOUT_L[0]
TEMP_CONFIG
Name: TEMP_CONFIG
Address: 83 (53h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
FUNCTION
2:0
TEMP_DLPFCFG[2:0]
Low pass filter configuration for temperature sensor as shown in the table below:
TEMP_DLPCFG
Temp Sensor
NBW (Hz)
0
1
2
3
4
5
6
7
Document Number: DS-000192
Revision: 1.1
7932.0
217.9
123.5
65.9
34.1
17.3
8.8
7932.0
Rate (kHz)
9
1.125
1.125
1.125
1.125
1.125
Rate (kHz)
9
Page 69 of 89
ICM-20649
MOD_CTRL_USR
Name: MOD_CTRL_USR
Address: 84 (54h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x03
BIT
7:1
0
NAME
REG_LP_DMP_EN
FUNCTION
Reserved.
Enable turning on DMP in Low Power Accelerometer mode.
REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
7:6
5:4
NAME
USER_BANK[1:0]
3:0
-
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK.
0 - Select USER BANK 0
1 - Select USER BANK 1
2 - Select USER BANK 2
3 - Select USER BANK 3
Reserved.
Page 70 of 89
ICM-20649
8.4
USR BANK 3 REGISTER MAP
I2C_MST_ODR_CONFIG
Name: I2C_MST_ODR_CONFIG
Address: 0 (00h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:4
3:0
NAME
I2C_MST_ODR_CONFIG[3:0]
FUNCTION
Reserved.
ODR configuration for external sensor when gyroscope and accelerometer are
disabled. ODR is computed as follows:
1 -1 kHz/(2^((odr_config[3:0])) )
When gyroscope is enabled, all sensors (including I2C_MASTER) use the gyroscope
ODR. If gyroscope is disabled then all sensors (including I2C_MASTER) use the
accelerometer ODR.
I2C_MST_CTRL
Name: I2C_MST_CTRL
Address: 1 (01h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
MULT_MST_EN
6:5
4
I2C_MST_P_NSR
3:0
I2C_MST_CLK[3:0]
FUNCTION
Enables multi-master capability. When disabled, clocking to the I2C_MST_IF can be
disabled when not in use and the logic to detect lost arbitration is disabled.
Reserved.
This bit controls the I2C Master’s transition from one slave read to the next slave
read.
0 - There is a restart between reads.
1 - There is a stop between reads.
Sets I2C master clock frequency as shown in Table 19.
I2C_MST_DELAY_CTRL
Name: I2C_MST_DELAY_CTRL
Address: 2 (02h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
6:5
4
NAME
DELAY_ES_SHADOW
I2C_SLV4_DELAY_EN
3
I2C_SLV3_DELAY_EN
2
I2C_SLV2_DELAY_EN
1
I2C_SLV1_DELAY_EN
0
I2C_SLV0_DELAY_EN
Document Number: DS-000192
Revision: 1.1
FUNCTION
Delays shadowing of external sensor data until all data is received.
Reserved.
When enabled, slave 4 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 3 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 2 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 1 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 0 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
Page 71 of 89
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I2C_SLV0_ADDR
Name: I2C_SLV0_ADDR
Address: 3 (03h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV0_RNW
6:0
I2C_ID_0[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 0.
I2C_SLV0_REG
Name: I2C_SLV0_REG
Address: 4 (04h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV0_REG[7:0]
FUNCTION
I2C slave 0 register address from where to begin data transfer.
I2C_SLV0_CTRL
Name: I2C_SLV0_CTRL
Address: 5 (05h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV0_EN
6
I2C_SLV0_BYTE_SW
5
I2C_SLV0_REG_DIS
4
I2C_SLV0_GRP
3:0
I2C_SLV0_LENG[3:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register, which is always EXT_SENS_DATA_00 for I2C slave 0.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV0_REG[0] = 1, or if the last byte
read has a register address LSB = 0.
For example, if I2C_SLV0_REG = 0x1, and I2C_SLV0_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_00,
2) The second and third bytes will be read and swapped, so the data read from address
0x2 will be stored at EXT_SENS_DATA_02, and the data read from address 0x3 will be
stored at EXT_SENS_DATA_01,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_03
0 – No swapping occurs; bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or write
data
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc.., or if
the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group).
1 indicates slave register addresses 1 and 2 are grouped together (even numbered
register ends the group). This allows byte swapping of registers that are grouped
starting at any address.
Number of bytes to be read from I2C slave 0.
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ICM-20649
I2C_SLV0_DO
Name: I2C_SLV0_DO
Address: 6 (06h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV0_DO[7:0]
FUNCTION
Data out when slave 0 is set to write.
I2C_SLV1_ADDR
Name: I2C_SLV1_ADDR
Address: 7 (07h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV1_RNW
6:0
I2C_ID_1[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 1.
I2C_SLV1_REG
Name: I2C_SLV1_REG
Address: 8 (08h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV1_REG[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
I2C slave 1 register address from where to begin data transfer.
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ICM-20649
I2C_SLV1_CTRL
Name: I2C_SLV1_CTRL
Address: 9 (09h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV1_EN
6
I2C_SLV1_BYTE_SW
5
I2C_SLV1_REG_DIS
4
I2C_SLV1_GRP
3:0
I2C_SLV1_LENG[3:0]
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register as determined by I2C_SLV0_EN and
I2C_SLV0_LENG.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV1_REG[0] = 1, or if the last byte
read has a register address LSB = 0.
For example, if I2C_SLV0_EN = 0x1, and I2C_SLV0_LENG = 0x3 (to show swap has to
do with I2C slave address not EXT_SENS_DATA address), and if I2C_SLV1_REG = 0x1,
and I2C_SLV1_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_03 (slave
0’s data will be in EXT_SENS_DATA_00, EXT_SENS_DATA_01, and
EXT_SENS_DATA_02),
2) The second and third bytes will be read and swapped, so the data read from
address 0x2 will be stored at EXT_SENS_DATA_04, and the data read from address
0x3 will be stored at EXT_SENS_DATA_05,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_06
0 – No swapping occurs; bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or
write data
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc., or
if the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
Number of bytes to be read from I2C slave 1.
SLV1_DO
Name: I2C_SLV1_DO
Address: 10 (0Ah)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV1_DO[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Data out when slave 1 is set to write.
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I2C_SLV2_ADDR
Name: I2C_SLV2_ADDR
Address: 11 (0Bh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV2_RNW
6:0
I2C_ID_2[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 2.
I2C_SLV2_REG
Name: I2C_SLV2_REG
Address: 12 (0Ch)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV2_REG[7:0]
FUNCTION
I2C slave 2 register address from where to begin data transfer.
I2C_SLV2_CTRL
Name: I2C_SLV2_CTRL
Address: 13 (0Dh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV2_EN
6
I2C_SLV2_BYTE_SW
5
I2C_SLV2_REG_DIS
4
I2C_SLV2_GRP
3:0
I2C_SLV2_LENG[3:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register as determined by I2C_SLV0_EN, I2C_SLV0_LENG,
I2C_SLV1_EN and I2C_SLV1_LENG.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV2_REG[0] = 1, or if the last byte
read has a register address LSB = 0.
See I2C_SLV1_CTRL for an example.
0 – No swapping occurs; bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or
write data
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
Number of bytes to be read from I2C slave 2.
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I2C_SLV2_DO
Name: I2C_SLV2_DO
Address: 14 (0Eh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV2_DO[7:0]
FUNCTION
Data out when slave 2 is set to write.
I2C_SLV3_ADDR
Name: I2C_SLV3_ADDR
Address: 15 (0Fh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV3_RNW
6:0
I2C_ID_3[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 3.
I2C_SLV3_REG
Name: I2C_SLV3_REG
Address: 16 (10h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV3_REG[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
I2C slave 3 register address from where to begin data transfer.
Page 76 of 89
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I2C_SLV3_CTRL
Name: I2C_SLV3_CTRL
Address: 17 (11h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV3_EN
6
I2C_SLV3_BYTE_SW
5
I2C_SLV3_REG_DIS
4
I2C_SLV3_GRP
3:0
I2C_SLV3_LENG[3:0]
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register as determined by I2C_SLV0_EN, I2C_SLV0_LENG,
I2C_SLV1_EN, I2C_SLV1_LENG, I2C_SLV2_EN and I2C_SLV2_LENG.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV3_REG[0] = 1, or if the last byte
read has a register address LSB = 0.
See I2C_SLV1_CTRL for an example.
0 – No swapping occurs, bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or
write data
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc., or
if the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group).
1 indicates slave register addresses 1 and 2 are grouped together (even numbered
register ends the group). This allows byte swapping of registers that are grouped
starting at any address.
Number of bytes to be read from I2C slave 3.
I2C_SLV3_DO
Name: I2C_SLV3_DO
Address: 18 (12h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV3_DO[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Data out when slave 3 is set to write.
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I2C_SLV4_ADDR
Name: I2C_SLV4_ADDR
Address: 19 (13h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV4_RNW
6:0
I2C_ID_4[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 4.
Note: The I2C Slave 4 interface can be used to perform only single byte read and write transactions.
I2C_SLV4_REG
Name: I2C_SLV4_REG
Address: 20 (14h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV4_REG[7:0]
FUNCTION
I2C slave 4 register address from where to begin data transfer.
I2C_SLV4_CTRL
Name: I2C_SLV4_CTRL
Address: 21 (15h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7
NAME
I2C_SLV4_EN
6
I2C_SLV4_INT_EN
5
I2C_SLV4_REG_DIS
4:0
I2C_SLV4_DLY[4:0]
FUNCTION
1 – Enable data transfer with this slave at the sample rate. If read command, store
data in I2C_SLV4_DI register, if write command, write data stored in I2C_SLV4_DO
register. Bit is cleared when a single transfer is complete. Be sure to write
I2C_SLV4_DO first
0 – Function is disabled for this slave.
1 – Enables the completion of the I2C slave 4 data transfer to cause an interrupt.
0 – Completion of the I2C slave 4 data transfer will not cause an interrupt.
When set, the transaction does not write a register value, it will only read data, or
write data.
When enabled via the I2C_MST_DELAY_CTRL, those slaves will only be enabled
every1/(1+I2C_SLV4_DLY) samples as determined by I2C_MST_ODR_CONFIG
I2C_SLV4_DO
Name: I2C_SLV4_DO
Address: 22 (16h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV4_DO[7:0]
Document Number: DS-000192
Revision: 1.1
FUNCTION
Data out when slave 4 is set to write.
Page 78 of 89
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I2C_SLV4_DI
Name: I2C_SLV4_DI
Address: 23 (17h)
Type: USR3
Bank: 3
Serial IF: R
Reset Value: 0x00
BIT
7:0
NAME
I2C_SLV4_DI[7:0]
FUNCTION
Data read from I2C Slave 4.
REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type:
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
7:6
5:4
NAME
USER_BANK[1:0]
3:0
-
Document Number: DS-000192
Revision: 1.1
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK:
0 - Select USER BANK 0
1 - Select USER BANK 1
2 - Select USER BANK 2
3 - Select USER BANK 3
Reserved.
Page 79 of 89
ICM-20649
9 USE NOTES
9.1
GYROSCOPE MODE TRANSITION
When gyroscope is transitioning from standard to low-noise mode, several unsettled output samples will be observed at the
gyroscope output due to filter switching and settling. The number of unsettled gyroscope output samples depends on the filter and
ODR settings.
9.2
POWER MANAGEMENT 1 REGISTER SETTING
CLKSEL[2:0] has to be set to 001 to achieve the datasheet performance.
9.3
DMP MEMORY ACCESS
Reading/writing DMP memory and FIFO through I2C in a multithreaded environment can cause wrong data being read. To avoid the
issue, one may use SPI instead of I2C, or use I2C with mutexes.
9.4
TIME BASE CORRECTION
The system clock frequency at room temperature in gyroscope mode and 6-Axis mode varies from part to part, and the clock rates
specified in datasheet are the nominal values. The percentage of frequency deviation from the nominal values for each part is logged
in register TIMEBASE_CORRECTION_PLL, and the range of the code is ±10% with each LSB representing a step of 0.079%. For
example, if on one part TIMEBASE_CORRECTION_PLL = 0x0C = d’12, it means the clock frequency in gyroscope mode and 6-Axis
mode is ~0.94% faster than the nominal value.
When operating in accelerometer-only mode, the system clock frequency at room temperature is the nominal frequency over parts,
and it is independent of the value stored in TIMEBASE_CORRECTION_PLL register.
Document Number: DS-000192
Revision: 1.1
Page 80 of 89
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9.5
I2C MASTER CLOCK FREQUENCY
I2C master clock frequency can be set by register I2C_MST_CLK as shown in the table below. Due to temperature variation and part
to part variation of system clock frequency in different power modes, I2C_MST_CLK should be set such that in all conditions the
clock frequency will not exceed what a slave device can support. To achieve a targeted clock frequency of 400 kHz, MAX, it is
recommended to set I2C_MST_CLK = 7 (345.6 kHz / 46.67% duty cycle).
I2C_MST_CLK
Nominal CLK Frequency [kHz]
Duty Cycle
0
370.29
50.00%
1
-
-
2
370.29
50.00%
3
432.00
50.00%
4
370.29
42.86%
5
370.29
50.00%
6
345.60
40.00%
7
345.60
46.67%
8
304.94
47.06%
9
432.00
50.00%
10
432.00
41.67%
11
432.00
41.67%
12
471.27
45.45%
13
432.00
50.00%
14
345.60
46.67%
15
345.60
46.67%
Table 19. I2C Master Clock Frequency
9.6
CLOCKING
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope oscillator as the
reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for optimum sensor performance
and power consumption will be automatically selected based on the power mode. Specifically, the internal relaxation oscillator will
be selected when operating in accelerometer only mode, while the PLL will be selected whenever gyroscope is on, which includes
gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted that the
internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation oscillator is trimmed to
have a consistent operating frequency at room temperature, while the PLL clock frequency varies from part to part. The PLL
frequency deviation from the nominal value in percentage is captured in register TIMEBASE_CORRECTION_PLL, and users can factor
it in during distance and angle calculations to not sacrifice accuracy. Other than that, PLL has better frequency stability and lower
frequency variation over temperature than the internal relaxation oscillator.
Document Number: DS-000192
Revision: 1.1
Page 81 of 89
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9.7
LP_EN BIT-FIELD USAGE
The LP_EN bit-field (User Bank 0, PWR_MGMT_1 register, bit [5] helps to reduce the digital current. The recommended setting for
this bit-field is 1 to achieve the lowest possible current. However, when LP_EN is set to 1, user may not be able to write to the
following registers. If it is desired to write to registers in this list, it is recommended to first set LP_EN=0, write the desired
register(s), then set LP_EN=1 again:
•
•
•
•
9.8
USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE, FIFO_COUNTH,
FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
USER BANK 1: All registers except REG_BANK_SEL
USER BANK 2: All registers except REG_BANK_SEL
USER BANK 3: All registers except REG_BANK_SEL
REGISTER ACCESS USING SPI INTERFACE
Using the SPI interface, when the AP/user disables the gyroscope sensor (User Bank 0, PWR_MGMT_2 register, bits [2:0]=111) as
part of a sequence of register read or write commands, the AP/user will be required to subsequently wait 22µs prior to any of the
following operations:
(1) Writing to any of the following registers:
•
•
•
•
USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE, FIFO_COUNTH,
FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
USER BANK 1: All registers except REG_BANK_SEL
USER BANK 2: All registers except REG_BANK_SEL
USER BANK 3: All registers except REG_BANK_SEL
(2) Reading data from FIFO
(3) Reading from memory
Document Number: DS-000192
Revision: 1.1
Page 82 of 89
ICM-20649
10 ORIENTATION OF AXES
Figure 12 shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure.
+Z
+Y
+Z
IC
M20
+Y
64
9
+X
+X
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation
Document Number: DS-000192
Revision: 1.1
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11 PACKAGE DIMENSIONS
This section provides package dimensions for the device. Information for the 24 Lead QFN 3.0x3.0x0.9 package is below.
Figure 13. Package Dimensions
Document Number: DS-000192
Revision: 1.1
Page 84 of 89
ICM-20649
Total Thickness
Stand Off
Mold Thickness
L/F Thickness
Lead Width
Body Size
Lead Pitch
EP Size
Lead Length
Mold Flatness
Coplanarity
Lead Offset
Exposed Pad Offset
SYMBOL
A
A1
A2
A3
b
D
E
e
J
K
L
S
R
H
P
bbb
ccc
ddd
eee
MIN.
0.85
0.00
--0.203 REF
0.15
2.90
2.90
0.40 BSC
1.65
1.49
0.25
0.25 REF
0.075
0.12 REF
0.22 REF
0.10
0.075
0.10
0.10
NOM.
0.90
0.02
0.70
MAX.
0.95
0.05
---
0.20
3.00
3.00
0.25
3.10
3.10
1.70
1.54
0.30
1.75
1.59
0.35
---
---
Table 20. Package Dimensions
Document Number: DS-000192
Revision: 1.1
Page 85 of 89
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12 PART NUMBER PART MARKINGS
The part number part markings for ICM-20649 devices are summarized below:
PART NUMBER
ICM-20649
PART NUMBER PART MARKING
IC2649
Table 21. Part Number Package Markings
TOP VIEW
Part Number
Lot Traceability Code
IC2649
XXXXXX
YYWW
Y Y = Year Code
W W = Work Week
Figure 14. Part Number Package Markings
Document Number: DS-000192
Revision: 1.1
Page 86 of 89
ICM-20649
13 REFERENCES
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
•
•
Manufacturing Recommendations
o Assembly Guidelines and Recommendations
o PCB Design Guidelines and Recommendations
o MEMS Handling Instructions
o ESD Considerations
o Reflow Specification
o Storage Specifications
o Package Marking Specification
o Tape & Reel Specification
o Reel & Pizza Box Label
o Packaging
o Representative Shipping Carton Label
Compliance
o Environmental Compliance
o DRC Compliance
o Compliance Declaration Disclaimer
Document Number: DS-000192
Revision: 1.1
Page 87 of 89
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14 REVISION HISTORY
Revision Date
Revision
Description
03/25/2016
0.1
Initial Release
06/13/2016
0.2
Updated Section 3
07/22/2016
0.3
Updated Sections 3, 12
12/13/2016
1.0
Updated Sections 3, 6, 12
07/01/2021
1.1
Updated FIFO size information (Cover Page, Sections 1.2, 4.15)
Document Number: DS-000192
Revision: 1.1
Page 88 of 89
ICM-20649
This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by TDK
InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without
notice. TDK InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance,
without prior notice. TDK InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document.
TDK InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services
detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property
rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any
patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the
property of their respective companies. TDK InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional
or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2020—2021 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the
InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the
respective companies with which they are associated.
©2020—2021 InvenSense. All rights reserved.
Document Number: DS-000192
Revision: 1.1
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