ICM-20948
World’s Lowest Power 9-Axis MEMS MotionTracking™ Device
GENERAL DESCRIPTION
APPLICATIONS
The ICM-20948 is the world’s lowest power 9-axis
MotionTracking device that is ideally suited for Smartphones,
Tablets, Wearable Sensors, and IoT applications.
ICM-20948 supports an auxiliary I2C interface to external
sensors, on-chip 16-bit ADCs, programmable digital filters, an
embedded temperature sensor, and programmable
interrupts. The device features an operating voltage range
down to 1.71V. Communication ports include I2C and high
speed SPI at 7 MHz.
Note: ICM-20948 VDDIO range is 1.71V to 1.95V, different
than the MPU-9250 9-axis device.
ORDERING INFORMATION
•
•
•
•
•
•
•
•
•
•
TYPICAL OPERATING CIRCUIT
RESV
RESV
19
20
21
24
BLOCK DIAGRAM
AUX_DA
nCS
SCLK
SDI
22
GND
NC
1
18
NC
2
17 NC
16 NC
NC
3
NC
4
NC
5
14 NC
NC
6
13 VDD
ICM-20948
1.71 – 1.95VDC
C3, 0.1 µ F
12
11
1.71 – 3.6VDC
C2, 0.1 µF
INT1
AUX_CL
7
15 NC
FSYNC
24-Pin QFN
9
−40°C to +85°C
REGOUT 10
ICM-20948†
SDO / AD0
PACKAGE
SCL / SCLK
TEMP RANGE
nCS
PART
†Denotes RoHS and Green-Compliant Package
•
Lowest Power 9-Axis Device at 2.5 mW
3-Axis Gyroscope with Programmable FSR of
±250 dps, ±500 dps, ±1000 dps, and ±2000 dps
3-Axis Accelerometer with Programmable FSR of
±2g, ±4g, ±8g, and ±16g
3-Axis Compass with a wide range to ±4900 µT
Onboard Digital Motion Processor (DMP)
Android support
Auxiliary I2C interface for external sensors
On-Chip 16-bit ADCs and Programmable Filters
7 MHz SPI or 400 kHz Fast Mode I²C
Digital-output temperature sensor
VDD operating range of 1.71V to 3.6V
MEMS structure hermetically sealed and bonded at
wafer level
RoHS and Green compliant
8
•
•
•
SDA / SDI
•
FEATURES
23
•
3-axis gyroscope, 3-axis accelerometer, 3-axis
compass, and a Digital Motion Processor™ (DMPTM)
in a 3 mm x 3 mm x 1 mm (24-pin QFN) package
DMP offloads computation of motion processing
algorithms from the host processor, improving
system power performance
Software drivers are fully compliant with Google’s
latest Android release
EIS FSYNC support
Smartphones and Tablets
Wearable Sensors
IoT Applications
VDDIO
•
•
•
•
C1, 0.1 µF
SDO
InvenSense reserves the right to change the detail
specifications as may be required to permit
improvements in the design of its products.
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
www.invensense.com
Document Number: DS-000189
Revision: 1.3
Release Date: 06/02/2017
ICM-20948
TABLE OF CONTENTS
GENERAL DESCRIPTION ......................................................................................................................................................... 1
ORDERING INFORMATION ..................................................................................................................................................... 1
BLOCK DIAGRAM ................................................................................................................................................................. 1
APPLICATIONS..................................................................................................................................................................... 1
FEATURES .......................................................................................................................................................................... 1
TYPICAL OPERATING CIRCUIT ................................................................................................................................................. 1
1
GENERAL DESCRIPTION ........................................................................................................................................ 9
1.1
1.2
1.3
2
FEATURES .......................................................................................................................................................... 10
2.1
2.2
2.3
2.4
2.5
3
PURPOSE AND SCOPE ............................................................................................................................................... 9
PRODUCT OVERVIEW ............................................................................................................................................... 9
APPLICATIONS ......................................................................................................................................................... 9
GYROSCOPE FEATURES ........................................................................................................................................... 10
ACCELEROMETER FEATURES..................................................................................................................................... 10
MAGNETOMETER FEATURES .................................................................................................................................... 10
DMP FEATURES .................................................................................................................................................... 10
ADDITIONAL FEATURES ........................................................................................................................................... 10
ELECTRICAL CHARACTERISTICS ........................................................................................................................... 11
3.1
GYROSCOPE SPECIFICATIONS.................................................................................................................................... 11
3.2
ACCELEROMETER SPECIFICATIONS ............................................................................................................................. 12
3.3
MAGNETOMETER SPECIFICATIONS ............................................................................................................................ 13
3.4
ELECTRICAL SPECIFICATIONS..................................................................................................................................... 13
D.C. Electrical Characteristics ................................................................................................................................... 13
A.C. Electrical Characteristics ................................................................................................................................... 14
Other Electrical Specifications .................................................................................................................................. 15
3.5
I2C TIMING CHARACTERIZATION ............................................................................................................................... 16
3.6
SPI TIMING CHARACTERIZATION ............................................................................................................................... 17
3.7
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 18
4
APPLICATIONS INFORMATION ........................................................................................................................... 19
4.1
PIN OUT DIAGRAM AND SIGNAL DESCRIPTION ............................................................................................................ 19
4.2
TYPICAL OPERATING CIRCUIT ................................................................................................................................... 20
4.3
BILL OF MATERIALS FOR EXTERNAL COMPONENTS ....................................................................................................... 20
4.4
EXPOSED DIE PAD PRECAUTIONS .............................................................................................................................. 20
4.5
BLOCK DIAGRAM ................................................................................................................................................... 21
4.6
OVERVIEW ........................................................................................................................................................... 21
4.7
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING ............................................................ 22
4.8
THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING...................................................... 22
4.9
THREE-AXIS MEMS MAGNETOMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING ..................................................... 22
4.10 DIGITAL MOTION PROCESSOR .................................................................................................................................. 22
4.11 PRIMARY I2C AND SPI SERIAL COMMUNICATIONS INTERFACES ....................................................................................... 22
ICM-20948 Solution Using I2C Interface.................................................................................................................... 22
ICM-20948 Solution Using SPI Interface ................................................................................................................... 23
4.12 AUXILIARY I2C SERIAL INTERFACE .............................................................................................................................. 24
4.13 SELF-TEST ............................................................................................................................................................ 24
4.14 CLOCKING ............................................................................................................................................................ 25
4.15 SENSOR DATA REGISTERS ........................................................................................................................................ 25
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4.16
4.17
4.18
4.19
4.20
4.21
4.22
FIFO ................................................................................................................................................................... 25
FSYNC ................................................................................................................................................................ 25
INTERRUPTS.......................................................................................................................................................... 25
DIGITAL-OUTPUT TEMPERATURE SENSOR................................................................................................................... 26
BIAS AND LDOS .................................................................................................................................................... 26
CHARGE PUMP...................................................................................................................................................... 26
POWER MODES..................................................................................................................................................... 26
5
PROGRAMMABLE INTERRUPTS .......................................................................................................................... 27
6
DIGITAL INTERFACE ............................................................................................................................................ 28
6.1
6.2
6.3
6.4
6.5
7
REGISTER MAP FOR GYROSCOPE AND ACCELEROMETER ................................................................................... 32
7.1
7.2
7.3
7.4
8
I2C AND SPI SERIAL INTERFACES ............................................................................................................................... 28
I2C INTERFACE ...................................................................................................................................................... 28
I2C COMMUNICATIONS PROTOCOL ........................................................................................................................... 28
I2C TERMS ........................................................................................................................................................... 30
SPI INTERFACE ...................................................................................................................................................... 31
USER BANK 0 REGISTER MAP .................................................................................................................................. 32
USER BANK 1 REGISTER MAP .................................................................................................................................. 33
USER BANK 2 REGISTER MAP .................................................................................................................................. 34
USER BANK 3 REGISTER MAP .................................................................................................................................. 34
USER BANK 0 REGISTER DESCRIPTIONS .............................................................................................................. 36
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
WHO_AM_I ....................................................................................................................................................... 36
USER_CTRL ........................................................................................................................................................ 36
LP_CONFIG ........................................................................................................................................................ 37
PWR_MGMT_1 ................................................................................................................................................. 37
PWR_MGMT_2 ................................................................................................................................................. 38
INT_PIN_CFG .................................................................................................................................................... 38
INT_ENABLE ...................................................................................................................................................... 39
INT_ENABLE_1 .................................................................................................................................................. 39
INT_ENABLE_2 .................................................................................................................................................. 39
INT_ENABLE_3 .................................................................................................................................................. 40
I2C_MST_STATUS ............................................................................................................................................. 40
INT_STATUS ...................................................................................................................................................... 40
INT_STATUS_1 .................................................................................................................................................. 41
INT_STATUS_2 .................................................................................................................................................. 41
INT_STATUS_3 .................................................................................................................................................. 41
DELAY_TIMEH ................................................................................................................................................... 41
DELAY_TIMEL .................................................................................................................................................... 42
ACCEL_XOUT_H ................................................................................................................................................ 42
ACCEL_XOUT_L ................................................................................................................................................. 42
ACCEL_YOUT_H ................................................................................................................................................ 42
ACCEL_YOUT_L ................................................................................................................................................. 43
ACCEL_ZOUT_H ................................................................................................................................................ 43
ACCEL_ZOUT_L ................................................................................................................................................. 43
GYRO_XOUT_H ................................................................................................................................................. 43
GYRO_XOUT_L .................................................................................................................................................. 44
GYRO_YOUT_H ................................................................................................................................................. 44
GYRO_YOUT_L .................................................................................................................................................. 44
GYRO_ZOUT_H ................................................................................................................................................. 44
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8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
8.55
8.56
8.57
8.58
8.59
8.60
8.61
8.62
8.63
8.64
8.65
9
GYRO_ZOUT_L .................................................................................................................................................. 45
TEMP_OUT_H ................................................................................................................................................... 45
TEMP_OUT_L .................................................................................................................................................... 45
EXT_SLV_SENS_DATA_00 ................................................................................................................................. 45
EXT_SLV_SENS_DATA_01 ................................................................................................................................. 46
EXT_SLV_SENS_DATA_02 ................................................................................................................................. 46
EXT_SLV_SENS_DATA_03 ................................................................................................................................. 46
EXT_SLV_SENS_DATA_04 ................................................................................................................................. 46
EXT_SLV_SENS_DATA_05 ................................................................................................................................. 47
EXT_SLV_SENS_DATA_06 ................................................................................................................................. 47
EXT_SLV_SENS_DATA_07 ................................................................................................................................. 47
EXT_SLV_SENS_DATA_08 ................................................................................................................................. 47
EXT_SLV_SENS_DATA_09 ................................................................................................................................. 48
EXT_SLV_SENS_DATA_10 ................................................................................................................................. 48
EXT_SLV_SENS_DATA_11 ................................................................................................................................. 48
EXT_SLV_SENS_DATA_12 ................................................................................................................................. 48
EXT_SLV_SENS_DATA_13 ................................................................................................................................. 49
EXT_SLV_SENS_DATA_14 ................................................................................................................................. 49
EXT_SLV_SENS_DATA_15 ................................................................................................................................. 49
EXT_SLV_SENS_DATA_16 ................................................................................................................................. 49
EXT_SLV_SENS_DATA_17 ................................................................................................................................. 50
EXT_SLV_SENS_DATA_18 ................................................................................................................................. 50
EXT_SLV_SENS_DATA_19 ................................................................................................................................. 50
EXT_SLV_SENS_DATA_20 ................................................................................................................................. 50
EXT_SLV_SENS_DATA_21 ................................................................................................................................. 51
EXT_SLV_SENS_DATA_22 ................................................................................................................................. 51
EXT_SLV_SENS_DATA_23 ................................................................................................................................. 51
FIFO_EN_1 ........................................................................................................................................................ 52
FIFO_EN_2 ........................................................................................................................................................ 52
FIFO_RST ........................................................................................................................................................... 53
FIFO_MODE ...................................................................................................................................................... 53
FIFO_COUNTH .................................................................................................................................................. 53
FIFO_COUNTL ................................................................................................................................................... 53
FIFO_R_W ......................................................................................................................................................... 54
DATA_RDY_STATUS .......................................................................................................................................... 54
FIFO_CFG .......................................................................................................................................................... 54
REG_BANK_SEL ................................................................................................................................................. 54
USR BANK 1 REGISTER DESCRIPTIONS ................................................................................................................ 55
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
SELF_TEST_X_GYRO .......................................................................................................................................... 55
SELF_TEST_Y_GYRO .......................................................................................................................................... 55
SELF_TEST_Z_GYRO .......................................................................................................................................... 55
SELF_TEST_X_ACCEL ......................................................................................................................................... 55
SELF_TEST_Y_ACCEL ......................................................................................................................................... 56
SELF_TEST_Z_ACCEL ......................................................................................................................................... 56
XA_OFFS_H ....................................................................................................................................................... 56
XA_OFFS_L ........................................................................................................................................................ 56
YA_OFFS_H ....................................................................................................................................................... 56
YA_OFFS_L ........................................................................................................................................................ 57
ZA_OFFS_H ....................................................................................................................................................... 57
ZA_OFFS_L ........................................................................................................................................................ 57
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9.13
9.14
10
TIMEBASE_CORRECTION_PLL ........................................................................................................................... 57
REG_BANK_SEL ................................................................................................................................................. 58
USR BANK 2 REGISTER MAP ........................................................................................................................... 59
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
11
GYRO_SMPLRT_DIV .......................................................................................................................................... 59
GYRO_CONFIG_1 .............................................................................................................................................. 59
GYRO_CONFIG_2 .............................................................................................................................................. 60
XG_OFFS_USRH ................................................................................................................................................ 61
XG_OFFS_USRL ................................................................................................................................................. 62
YG_OFFS_USRH ................................................................................................................................................ 62
YG_OFFS_USRL ................................................................................................................................................. 62
ZG_OFFS_USRH................................................................................................................................................. 62
ZG_OFFS_USRL ................................................................................................................................................. 62
ODR_ALIGN_EN ............................................................................................................................................ 63
ACCEL_SMPLRT_DIV_1 ................................................................................................................................. 63
ACCEL_SMPLRT_DIV_2 ................................................................................................................................. 63
ACCEL_INTEL_CTRL ....................................................................................................................................... 63
ACCEL_WOM_THR ........................................................................................................................................ 64
ACCEL_CONFIG ............................................................................................................................................. 64
ACCEL_CONFIG_2 ......................................................................................................................................... 65
FSYNC_CONFIG ............................................................................................................................................. 66
TEMP_CONFIG .............................................................................................................................................. 67
MOD_CTRL_USR ........................................................................................................................................... 67
REG_BANK_SEL ............................................................................................................................................. 67
USR BANK 3 REGISTER MAP ........................................................................................................................... 68
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
11.23
11.24
11.25
I2C_MST_ODR_CONFIG .................................................................................................................................... 68
I2C_MST_CTRL .................................................................................................................................................. 68
I2C_MST_DELAY_CTRL...................................................................................................................................... 69
I2C_SLV0_ADDR ................................................................................................................................................ 69
I2C_SLV0_REG................................................................................................................................................... 69
I2C_SLV0_CTRL ................................................................................................................................................. 70
I2C_SLV0_DO .................................................................................................................................................... 70
I2C_SLV1_ADDR ................................................................................................................................................ 70
I2C_SLV1_REG................................................................................................................................................... 71
I2C_SLV1_CTRL ............................................................................................................................................. 71
I2C_SLV1_DO ................................................................................................................................................ 72
I2C_SLV2_ADDR ............................................................................................................................................ 72
I2C_SLV2_REG............................................................................................................................................... 72
I2C_SLV2_CTRL ............................................................................................................................................. 73
I2C_SLV2_DO ................................................................................................................................................ 73
I2C_SLV3_ADDR ............................................................................................................................................ 73
I2C_SLV3_REG............................................................................................................................................... 74
I2C_SLV3_CTRL ............................................................................................................................................. 74
I2C_SLV3_DO ................................................................................................................................................ 74
I2C_SLV4_ADDR ............................................................................................................................................ 75
I2C_SLV4_REG............................................................................................................................................... 75
I2C_SLV4_CTRL ............................................................................................................................................. 75
I2C_SLV4_DO ................................................................................................................................................ 75
I2C_SLV4_DI .................................................................................................................................................. 76
REG_BANK_SEL ............................................................................................................................................. 76
Document Number: DS-000189
Revision: 1.3
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12
12.1
13
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
REGISTER MAP FOR MAGNETOMETER ........................................................................................................... 77
REGISTER MAP DESCRIPTION ................................................................................................................................... 77
DETAILED DESCRIPTIONS FOR MAGNETOMETER REGISTERS .......................................................................... 78
WIA: DEVICE ID ................................................................................................................................................... 78
ST1: STATUS 1 ..................................................................................................................................................... 78
HXL TO HZH: MEASUREMENT DATA ........................................................................................................................ 78
ST2: STATUS 2 ..................................................................................................................................................... 79
CNTL2: CONTROL 2 .............................................................................................................................................. 79
CNTL3: CONTROL 3 .............................................................................................................................................. 80
TS1, TS2: TEST 1, 2 .............................................................................................................................................. 80
USE NOTES ..................................................................................................................................................... 81
GYROSCOPE MODE TRANSITION ............................................................................................................................... 81
POWER MANAGEMENT 1 REGISTER SETTING .............................................................................................................. 81
DMP MEMORY ACCESS ......................................................................................................................................... 81
TIME BASE CORRECTION ......................................................................................................................................... 81
I2C MASTER CLOCK FREQUENCY ............................................................................................................................... 81
CLOCKING ............................................................................................................................................................ 82
LP_EN BIT-FIELD USAGE ........................................................................................................................................ 82
REGISTER ACCESS USING SPI INTERFACE .................................................................................................................... 82
15
ORIENTATION OF AXES .................................................................................................................................. 83
16
PACKAGE DIMENSIONS .................................................................................................................................. 84
17
PART NUMBER PART MARKINGS.................................................................................................................... 86
18
REFERENCES ................................................................................................................................................... 87
19
DOCUMENT INFORMATION ........................................................................................................................... 88
19.1 REVISION HISTORY ................................................................................................................................................. 88
COMPLIANCE DECLARATION DISCLAIMER ............................................................................................................................... 89
Document Number: DS-000189
Revision: 1.3
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ICM-20948
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram...................................................................................................................................... 16
Figure 2. SPI Bus Timing Diagram ..................................................................................................................................... 17
Figure 3. Pin out Diagram for ICM-20948 3 mm x 3 mm x 1 mm QFN ............................................................................. 19
Figure 4. ICM-20948 Application Schematic (a) I2C operation (b) SPI operation ............................................................. 20
Figure 5. ICM-20948 Block Diagram ................................................................................................................................. 21
Figure 6. ICM-20948 Solution Using I2C Interface ............................................................................................................ 23
Figure 7. ICM-20948 Solution Using SPI Interface ............................................................................................................ 24
Figure 8. START and STOP Conditions .............................................................................................................................. 28
Figure 9. Acknowledge on the I2C Bus .............................................................................................................................. 29
Figure 10. Complete I2C Data Transfer ............................................................................................................................. 29
Figure 11. Typical SPI Master / Slave Configuration ......................................................................................................... 31
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation ............................................................................. 83
Figure 13. Orientation of Axes of Sensitivity for Magnetometer ..................................................................................... 83
Figure 14. Package Dimensions ........................................................................................................................................ 84
Figure 15. Part Number Part Markings ............................................................................................................................. 86
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LIST OF TABLES
Table 1. Gyroscope Specifications .................................................................................................................................... 11
Table 2. Accelerometer Specifications ............................................................................................................................. 12
Table 3. Magnetometer Specifications ............................................................................................................................. 13
Table 4. D.C. Electrical Characteristics.............................................................................................................................. 13
Table 5. A.C. Electrical Characteristics .............................................................................................................................. 15
Table 6. Other Electrical Specifications ............................................................................................................................ 15
Table 7. I2C Timing Characteristics ................................................................................................................................... 16
Table 8. SPI Timing Characteristics (7 MHz) ..................................................................................................................... 17
Table 9. Absolute Maximum Ratings ................................................................................................................................ 18
Table 10. Signal Descriptions ............................................................................................................................................ 19
Table 11. Bill of Materials ................................................................................................................................................. 20
Table 12. Power Modes for ICM-20948............................................................................................................................ 26
Table 13. Interrupt Sources .............................................................................................................................................. 27
Table 14. Serial Interface .................................................................................................................................................. 28
Table 15. I2C Terms ........................................................................................................................................................... 30
Table 16. Gyroscope Configuration 1 ............................................................................................................................... 60
Table 17. Gyroscope Configuration 2 ............................................................................................................................... 61
Table 18. Accelerator Configuration................................................................................................................................. 64
Table 19. Accelerator Configuration 2 .............................................................................................................................. 66
Table 20. Register Table for Magnetometer .................................................................................................................... 77
Table 21. Register Map for Magnetometer ...................................................................................................................... 77
Table 22. Magnetometer Measurement Data Format ..................................................................................................... 79
Table 23. I2C Master Clock Frequency .............................................................................................................................. 82
Table 24. Package Dimensions ......................................................................................................................................... 85
Table 26. Part Number Part Markings .............................................................................................................................. 86
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ICM-20948
1 GENERAL DESCRIPTION
1.1
PURPOSE AND SCOPE
This document is a preliminary data sheet, providing a description, specifications, and design related information on
the ICM-20948 MotionTracking device.
For references to register map and descriptions of individual registers, please refer to the ICM-20948 Register Map
and Register Descriptions document.
1.2
PRODUCT OVERVIEW
The ICM-20948 is a multi-chip module (MCM) consisting of two dies integrated into a single QFN package. One die
houses a 3-axis gyroscope, a 3-axis accelerometer, and a Digital Motion Processor™ (DMP). The other die houses the
AK09916 3-axis magnetometer from Asahi Kasei Microdevices Corporation. The ICM-20948 is a 9-axis MotionTracking
device all in a small 3x3x1mm QFN package. The device supports the following features:
•
•
•
FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set)
Runtime Calibration
Enhanced FSYNC functionality to improve timing for applications like EIS
ICM-20948 devices, with their 9-axis integration, on-chip DMP, and run-time calibration firmware, enable
manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete
devices, guaranteeing optimal motion performance for consumers.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The
accelerometer has a user-programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated
initial sensitivity of both sensors reduces production-line calibration requirements.
Other key features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V,
and a separate digital IO supply, VDDIO from 1.71V to 1.95V.
Communication with all registers of the device is performed using I2C at up to 100 kHz (standard-mode) or up to
400 kHz (fast-mode), or SPI at up to 7 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with
companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a
footprint and thickness of 3 mm x 3 mm x 1 mm (24-pin QFN), to provide a very small yet high-performance, low-cost
package. The device provides high robustness by supporting 20,000g shock reliability.
1.3
APPLICATIONS
•
•
•
•
Smartphones and Tablets
Wearable Sensors
IoT Applications
Drones
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Revision: 1.3
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ICM-20948
2 FEATURES
2.1
GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-20948 includes the following features:
•
•
•
2.2
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range
of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps, and integrated 16-bit ADCs
User-selectable ODR; User-selectable low pass filters
Self-test
ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-20948 includes the following features:
•
•
•
•
2.3
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g, and
±16g, and integrated 16-bit ADCs
User-selectable ODR; User-selectable low pass filters
Wake-on-motion interrupt for low power operation of applications processor
Self-test
MAGNETOMETER FEATURES
The triple-axis MEMS magnetometer in ICM-20948 includes a wide range of features:
•
•
•
•
•
2.4
3-axis silicon monolithic Hall-effect magnetic sensor with magnetic concentrator
Wide dynamic measurement range and high resolution with lower current consumption.
Output data resolution of 16-bits
Full scale measurement range is ±4900 µT
Self-test function with internal magnetic source to confirm magnetic sensor operation on end products
DMP FEATURES
The DMP in ICM-20948 includes the following capabilities:
•
•
•
•
2.5
Offloads computation of motion processing algorithms from the host processor. The DMP can be used to
minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host
processor for use in applications.
The DMP enables ultra-low power run-time and background calibration of the accelerometer, gyroscope, and
compass, maintaining optimal performance of the sensor data for both physical and virtual sensors generated
through sensor fusion. This enables the best user experience for all sensor enabled applications for the
lifetime of the device.
DMP features simplify the software architecture resulting in quicker time to market.
DMP features are OS, Platform, and Architecture independent, supporting virtually any AP, MCU, or other
embedded architecture.
ADDITIONAL FEATURES
The ICM-20948 includes the following additional features:
•
•
•
•
•
•
I2C at up to 100 kHz (standard-mode) or up to 400 kHz (fast-mode) or SPI at up to 7 MHz for communication
with registers
Auxiliary master I2C bus for reading data from external sensors (e.g. magnetometer)
Digital-output temperature sensor
20,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Document Number: DS-000189
Revision: 1.3
Page 10 of 89
ICM-20948
3 ELECTRICAL CHARACTERISTICS
3.1
GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTE: All specifications apply to Low-Power Mode and Low-Noise Mode, unless noted otherwise
PARAMETER
Full-Scale Range
Gyroscope ADC Word Length
Sensitivity Scale Factor
Sensitivity Scale Factor Tolerance
Sensitivity Scale Factor Variation Over
Temperature
Nonlinearity
Cross-Axis Sensitivity
CONDITIONS
GYROSCOPE SENSITIVITY
GYRO_FS_SEL=0
GYRO_FS_SEL=1
GYRO_FS_SEL=2
GYRO_FS_SEL=3
GYRO_FS_SEL=0
GYRO_FS_SEL=1
GYRO_FS_SEL=2
GYRO_FS_SEL=3
25°C
-40°C to +85°C
Best fit straight line; 25°C
MIN
TYP
UNITS
NOTES
±250
±500
±1000
±2000
16
131
65.5
32.8
16.4
±1.5
±3
dps
dps
dps
dps
bits
LSB/(dps)
LSB/(dps)
LSB/(dps)
LSB/(dps)
%
%
1
1
1
1
1
1
1
1
1
2
2
±0.1
±2
%
%
2, 3
2, 3
dps
dps/°C
2
2
dps/√Hz
2
2
1, 3
2, 3
562.5
kHz
Hz
ms
Hz
1.125k
Hz
9k
Hz
ZERO-RATE OUTPUT (ZRO)
25°C (Component-level)
±5
-40°C to +85°C
±0.05
GYROSCOPE NOISE PERFORMANCE (GYRO_FS_SEL=0)
Noise Spectral Density
Based on Noise Bandwidth =
0.015
10 Hz
GYROSCOPE MECHANICAL FREQUENCIES
25
27
LOW PASS FILTER RESPONSE
Programmable Range
5.7
GYROSCOPE START-UP TIME
From Full-Chip Sleep mode
35
Low-Power Mode
4.4
Low-Noise Mode
GYRO_FCHOICE=1;
4.4
OUTPUT DATA RATE
GYRO_DLPFCFG=x
Low-Noise Mode
GYRO_FCHOICE=0;
GYRO_DLPFCFG=x
MAX
Initial ZRO Tolerance
ZRO Variation Over Temperature
Table 1. Gyroscope Specifications
NOTES:
1.
2.
3.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Low-noise mode specification.
Document Number: DS-000189
Revision: 1.3
Page 11 of 89
29
197
1
ICM-20948
3.2
ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES: All specifications apply to Low-Power Mode and Low-Noise Mode, unless noted otherwise
PARAMETER
Full-Scale Range
ADC Word Length
Sensitivity Scale Factor
Initial Tolerance
Sensitivity Change vs. Temperature
Nonlinearity
Cross-Axis Sensitivity
Initial Tolerance
Initial Tolerance
Zero-G Level Change vs. Temperature
Noise Spectral Density
LOW PASS FILTER RESPONSE
ACCELEROMETER STARTUP TIME
OUTPUT DATA RATE
CONDITIONS
ACCELEROMETER SENSITIVITY
ACCEL_FS=0
ACCEL_FS=1
ACCEL_FS=2
ACCEL_FS=3
Output in two’s complement format
ACCEL_FS=0
ACCEL_FS=1
ACCEL_FS=2
ACCEL_FS=3
Component-level
-40°C to +85°C ACCEL_FS=0
Best Fit Straight Line
MIN
ZERO-G OUTPUT
Component-level, all axes
Board-level, all axes
0°C to +85°C
ACCELEROMETER NOISE PERFORMANCE
Based on Noise Bandwidth = 10 Hz
Programmable Range
5.7
From Sleep mode
From Cold Start, 1 ms VDD ramp
Low-Power Mode
0.27
Low-Noise Mode
ACCEL_FCHOICE=1;
4.5
ACCEL_DLPFCFG=x
Low-Noise Mode
ACCEL_FCHOICE=0;
ACCEL_DLPFCFG=x
Table 2. Accelerometer Specifications
NOTES:
1.
2.
3.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Low-noise mode specification.
Document Number: DS-000189
Revision: 1.3
Page 12 of 89
TYP
MAX
UNITS
NOTES
±2
±4
±8
±16
16
16,384
8,192
4,096
2,048
±0.5
±0.026
±0.5
±2
G
G
G
G
Bits
LSB/g
LSB/g
LSB/g
LSB/g
%
%/ºC
%
%
1
1
1
1
1
1
1
1
1
2
2
2, 3
2, 3
±25
±50
±0.80
mg
mg
mg/°C
2
2
2
2
1, 3
2, 3
2, 3
562.5
µg/√Hz
Hz
ms
ms
Hz
1.125k
Hz
4.5k
Hz
230
246
20
30
1
ICM-20948
3.3
MAGNETOMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
MAGNETOMETER SENSITIVITY
Full-Scale Range
Output Resolution
Sensitivity Scale Factor
±4900
16
0.15
µT
bits
µT / LSB
1
1
1
LSB
2
ZERO-FIELD OUTPUT
Initial Calibration Tolerance
-2000
+2000
OTHER
Output Data Rate
100
Hz
1
Table 3. Magnetometer Specifications
NOTES:
1.
2.
3.4
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
MIN
TYP
MAX
UNITS
NOTES
1.71
1.71
1.8
1.8
3.6
1.95
V
V
1
1
3.11
mA
2
Low-Power Mode, 102.3 Hz update rate, 1x
averaging filter
1.23
mA
2
Low-Power Mode, 102.3 Hz update rate, 1x
averaging filter
68.9
µA
2
90
µA
2
8
µA
2
°C
1
VDD
VDDIO
9-Axis (DMP disabled)
Gyroscope Only
(DMP, Barometer & Accelerometer
disabled)
Accelerometer Only
(DMP, Barometer & Gyroscope
disabled)
Magnetometer Only
(DMP, Accelerometer & Gyroscope
disabled)
Full-Chip Sleep Mode
Specified Temperature Range
SUPPLY CURRENTS
Low-Noise Mode; Compass in Continuous
Mode
8 Hz update rate
TEMPERATURE RANGE
Performance parameters are not applicable
beyond Specified Temperature Range
-40
Table 4. D.C. Electrical Characteristics
NOTES:
1.
2.
Guaranteed by design.
Derived from validation or characterization of parts, not guaranteed in production.
Document Number: DS-000189
Revision: 1.3
Page 13 of 89
+85
ICM-20948
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
100
ms
1
85
°C
LSB/°C
LSB
1
100
100
ms
ms
1
1
0.3*VDDIO
V
V
pF
1
SUPPLIES
Supply Ramp Time (TRAMP)
Operating Range
Sensitivity
Room Temp Offset
Supply Ramp Time (TRAMP)
Start-up time for register read/write
I2C ADDRESS
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT1, INT Low-Level Output Voltage
Output Leakage Current
tINT, INT Pulse Width
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
Vhys, Hysteresis
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
VIL, LOW-Level Input Voltage
VIH, HIGH-Level Input Voltage
Vhys, Hysteresis
VOL1, LOW-Level Output Voltage
VOL3, LOW-Level Output Voltage
IOL, LOW-Level Output Current
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
Document Number: DS-000189
Revision: 1.3
Monotonic ramp. Ramp
0.01
20
rate is 10% to 90% of the
final value.
TEMPERATURE SENSOR
Ambient
-40
Untrimmed
333.87
21°C
0
POWER-ON RESET
Valid power-on RESET
0.01
20
From power-up
11
AD0 = 0
1101000
AD0 = 1
1101001
DIGITAL INPUTS (FSYNC, AD0, SCLK, SDI, CS)
0.7*VDDIO
< 10
DIGITAL OUTPUT (SDO, INT)
RLOAD=1 MΩ;
0.9*VDDIO
RLOAD=1 MΩ;
OPEN=1, 0.3 mA sink
Current
OPEN=1
LATCH_INT_EN=0
I2C I/O (SCL, SDA)
-0.5V
0.7*VDDIO
0.1*VDDIO
0.1
100
50
0.3*VDDIO
VDDIO +
0.5V
Cb bus capacitance in pf
0
3
6
100
20+0.1Cb
AUXILLIARY I/O (AUX_CL, AUX_DA)
-0.5V
0.7* VDDIO
0.4
Cb bus capacitance in pF
Page 14 of 89
V
V
V
V
mA
mA
nA
250
ns
0.3*VDDIO
VDDIO +
0.5V
V
V
0.1* VDDIO
VDDIO > 2V; 1 mA sink
current
VDDIO < 2V; 1 mA sink
current
VOL = 0.4V
VOL = 0.6V
0
0.4
V
V
0
0.2* VDDIO
V
250
mA
mA
nA
ns
20+0.1Cb
3
6
100
1
nA
µs
0.1*VDDIO
3 mA sink current
VOL=0.4V
VOL=0.6V
V
V
V
1
1
ICM-20948
PARAMETER
Clock Frequency Initial Tolerance
Frequency Variation over
Temperature
CONDITIONS
MIN
TYP
INTERNAL CLOCK SOURCE
Accelerometer Only Mode
-5
Gyroscope or 6-Axis Mode
WITHOUT Timebase
-9
Correction
Gyroscope or 6-Axis Mode
-1
WITH Timebase Correction
Accelerometer Only Mode
-10
Gyroscope or 6-Axis Mode
MAX
UNITS
NOTES
+5
%
+9
%
1
1
+1
+10
%
%
±1
1
1
Table 5. A.C. Electrical Characteristics
NOTES:
1.
Derived from validation or characterization of parts, not guaranteed in production.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
SPI Operating Frequency, All
Registers Read/Write
I2C Operating Frequency
CONDITIONS
SERIAL INTERFACE
MIN
Low Speed Characterization
High Speed Characterization
All registers, Fast-mode
All registers, Standard-mode
Table 6. Other Electrical Specifications
NOTES:
1.
Derived from validation or characterization of parts, not guaranteed in production.
Document Number: DS-000189
Revision: 1.3
Page 15 of 89
TYP
100
±10%
7 ±10%
MAX
UNITS
kHz
400
100
MHz
kHz
kHz
NOTES
ICM-20948
I2C TIMING CHARACTERIZATION
3.5
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
I2C TIMING
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold
Time
tLOW, SCL Low Period
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup
Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
MIN
TYPICAL
MAX
UNITS
NOTES
400
0.6
kHz
µs
1, 2
1, 2
1.3
0.6
0.6
µs
µs
µs
1, 2
1, 2
1, 2
0
100
20+0.1Cb
20+0.1Cb
0.6
µs
ns
ns
ns
µs
1, 2
1, 2
1, 2
1, 2
1, 2
µs
1, 2
pF
µs
µs
1, 2
1, 2
1, 2
I2C FAST-MODE
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
tBUF, Bus Free Time Between STOP and
START Condition
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time
300
300
1.3
< 400
0.9
0.9
Table 7. I2C Timing Characteristics
NOTES:
1.
2.
Timing Characteristics apply to both Primary and Auxiliary I2C Bus.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
tf
SDA
tSU.DAT
tr
70%
30%
70%
30%
continued below at
tf
SCL
tr
70%
30%
S
tHD.STA
tVD.DAT
70%
30%
tHD.DAT
1/fSCL
tLOW
1st clock cycle
9th clock cycle
tHIGH
tBUF
SDA
70%
30%
A
tHD.STA
tSU.STA
SCL
70%
30%
Sr
tSU.STO
tVD.ACK
9th clock cycle
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000189
Revision: 1.3
Page 16 of 89
P
S
A
ICM-20948
3.6
SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYPICAL
MAX
UNITS
7
MHz
NOTES
SPI TIMING
fSCLK, SCLK Clock Frequency
tLOW, SCLK Low Period
64
ns
tHIGH, SCLK High Period
64
ns
tSU.CS, CS Setup Time
8
ns
tHD.CS, CS Hold Time
500
ns
tSU.SDI, SDI Setup Time
5
ns
tHD.SDI, SDI Hold Time
7
ns
tVD.SDO, SDO Valid Time
Cload = 20 pF
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
Cload = 20 pF
59
ns
50
ns
ns
6
Table 8. SPI Timing Characteristics (7 MHz)
NOTES:
1.
CS
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
70%
30%
tSU;CS
SCLK
tHIGH
70%
30%
tSU;SDI
SDI
70%
30%
tHD;SDI
tLOW
LSB IN
MSB IN
tVD;SDO
SDO
tHD;CS
1/fCLK
MSB OUT
70%
30%
Figure 2. SPI Bus Timing Diagram
Document Number: DS-000189
Revision: 1.3
Page 17 of 89
tDIS;SDO
tHD;SDO
LSB OUT
ICM-20948
3.7
ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute
maximum ratings conditions for extended periods may affect device reliability.
PARAMETER
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
Input Voltage Level (AUX_DA, AD0, FSYNC, INT, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Protection
Latch-up
Table 9. Absolute Maximum Ratings
Document Number: DS-000189
Revision: 1.3
Page 18 of 89
RATING
-0.5V to +4V
-0.3V to +2.5V
-0.5V to 2V
-0.5V to VDD + 0.5V
20,000g for 0.2 ms
-40°C to +105°C
-40°C to +125°C
2kV (HBM);
200V (MM)
JEDEC Class II (2),125°C
±100 mA
ICM-20948
4 APPLICATIONS INFORMATION
4.1
PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
7
8
9
10
11
12
13
18
19
20
21
22
23
24
1 – 6, 14 - 17
PIN NAME
AUX_CL
VDDIO
AD0 / SDO
REGOUT
FSYNC
INT1
VDD
GND
RESV
RESV
AUX_DA
nCS
SCL / SCLK
SDA / SDI
NC
PIN DESCRIPTION
I2C Master serial clock, for connecting to external sensors
Digital I/O supply voltage
I2C Slave Address LSB (AD0); SPI serial data output (SDO)
Regulator filter capacitor connection
Frame synchronization digital input. Connect to GND if unused
Interrupt 1
Power supply voltage
Power supply ground
Reserved. Do not connect.
Reserved. Connect to GND.
I2C master serial data, for connecting to external sensors
Chip select (SPI mode only)
I2C serial clock (SCL); SPI serial clock (SCLK)
I2C serial data (SDA); SPI serial data input (SDI)
Do not connect
Table 10. Signal Descriptions
SDA / SDI
SCL / SCLK
nCS
AUX_DA
RESV
RESV
24
23
22
21
20
19
NOTE: Power up with SCL/SCLK and nCS pins held low is not a supported use case. In case this power up approach is used, software
reset is required using the PWR_MGMT_1 register, prior to initialization.
NC
1
18 GND
NC
2
17 NC
NC
3
NC
4
15 NC
NC
5
14 NC
NC
6
13 VDD
16 NC
7
8
9
10
11
12
AUX_CL
VDDIO
SDO / AD0
REGOUT
FSYNC
INT1
ICM-20948
Figure 3. Pin out Diagram for ICM-20948 3 mm x 3 mm x 1 mm QFN
Document Number: DS-000189
Revision: 1.3
Page 19 of 89
ICM-20948
TYPICAL OPERATING CIRCUIT
GND
NC
1
18
NC
2
17 NC
RESV
19
RESV
20
AUX_DA
21
SCL / SCLK
23
22
SDA / SDI
24
RESV
RESV
20
19
AUX_DA
22
21
SCL / SCLK
SDA / SDI
nCS
23
24
SCLK
SDI
nCS
nCS
VDDIO
SCL
SDA
GND
NC
1
18
NC
2
17 NC
16 NC
NC
3
16 NC
NC
3
NC
4
15 NC
NC
4
15 NC
NC
5
14 NC
NC
5
14 NC
NC
6
13 VDD
NC
6
13 VDD
12
11
1.71 – 3.6VDC
C2, 0.1 µF
INT1
FSYNC
9
8
REGOUT 10
1.71 – 1.95VDC
SDO / AD0
7
C2, 0.1 µF
C1, 0.1 µF
C3, 0.1 µ F
ICM-20948
AUX_CL
11
12
1.71 – 3.6VDC
INT1
FSYNC
9
7
REGOUT 10
SDO / AD0
VDDIO
AUX_CL
1.71 – 1.95VDC
8
ICM-20948
VDDIO
4.2
C1, 0.1 µF
C3, 0.1 µ F
SDO
AD0
(a)
(b)
Figure 4. ICM-20948 Application Schematic (a)
I2C
operation (b) SPI operation
Note that the INT pin should be connected to a GPIO pin on the system processor that is capable of waking the system
processor from suspend mode.
I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required.
4.3
BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
LABEL
SPECIFICATION
QUANTITY
Regulator Filter Capacitor
C1
Ceramic, X7R, 0.1 µF ±10%, 2V
1
VDD Bypass Capacitor
C2
Ceramic, X7R, 0.1 µF ±10%, 4V
1
VDDIO Bypass Capacitor
C3
Ceramic, X7R, 0.1 µF ±10%, 4V
1
Table 11. Bill of Materials
4.4
EXPOSED DIE PAD PRECAUTIONS
InvenSense products have very low active and standby current consumption. The exposed die pad is not required for
heat sinking, and should not be soldered to the PCB. Failure to adhere to this rule can induce performance changes
due to package thermo-mechanical stress. There is no electrical connection between the pad and the CMOS.
Document Number: DS-000189
Revision: 1.3
Page 20 of 89
ICM-20948
4.5
BLOCK DIAGRAM
ICM-20948
Self
test
X Accel
ADC
Self
test
Y Accel
ADC
INT1
Interrupt
Status
Register
nCS
Slave I2C and
SPI Serial
Interface
FIFO
AD0 / SDO
SCL / SCLK
SDA / SDI
Z Accel
Self
test
X Gyro
Self
test
Y Gyro
Self
test
Z Gyro
ADC
ADC
Signal Conditioning
Self
test
User & Config
Registers
Serial
Interface
Bypass
Mux
Master I2C
Serial
Interface
Sensor
Registers
Digital Motion
Processor
(DMP)
ADC
ADC
ADC
ADC
ADC
X
Compass
Y
Compass
Z
Compass
Bias & LDOs
Charge
Pump
VDD
GND
REGOUT
Figure 5. ICM-20948 Block Diagram
4.6
OVERVIEW
The ICM-20948 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS magnetometer sensor with 16-bit ADCs and signal conditioning
Digital Motion Processor (DMP) engine
Primary I2C and SPI serial communications interfaces
Auxiliary I2C serial interface
Gyroscope, Accelerometer, and Magnetometer Self-Test
Clocking
Sensor Data Registers
FIFO
FSYNC
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Power Modes
Document Number: DS-000189
Revision: 1.3
AUX_DA
FSYNC
ADC
Signal Conditioning
Temp Sensor
AUX_CL
Page 21 of 89
ICM-20948
4.7
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20948 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-,
and Z-Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is
detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that
is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters
(ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250, ±500,
±1000, or ±2000 degrees per second (dps).
4.8
THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20948’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis
induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially.
The ICM-20948’s architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal
drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor
has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted
to ±2g, ±4g, ±8g, or ±16g.
4.9
THREE-AXIS MEMS MAGNETOMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The 3-axis magnetometer uses highly sensitive Hall sensor technology. The magnetometer portion of the IC
incorporates magnetic sensors for detecting terrestrial magnetism in the X-, Y-, and Z-Axes, a sensor driving circuit, a
signal amplifier chain, and an arithmetic circuit for processing the signal from each sensor. Each ADC has a 16-bit
resolution and a full scale range of ±4900 µT.
4.10 DIGITAL MOTION PROCESSOR
The embedded Digital Motion Processor (DMP) within the ICM-20948 offloads computation of motion processing
algorithms from the host processor. The DMP acquires data from accelerometers, gyroscopes, and additional third
party sensors such as magnetometers, and processes the data. The resulting data can be read from the FIFO. The DMP
has access to the external pins, which can be used for generating interrupts.
The purpose of the DMP is to offload both timing requirements and processing power from the host processor.
Typically, motion processing algorithms should be run at a high rate, often around 200 Hz, in order to provide accurate
results with low latency. This is required even if the application updates at a much lower rate; for example, a low
power user interface may update as slowly as 5 Hz, but the motion processing should still run at 200 Hz. The DMP can
be used to minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host
processor for use in applications.
4.11 PRIMARY I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The ICM-20948 communicates to a system processor using either a SPI or an I2C serial interface. The ICM-20948
always acts as a slave when communicating to the system processor. The LSB of the of the I2C slave address is set by
pin 1 (AD0).
ICM-20948 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the ICM-20948. In addition, the ICM-20948 is an I2C master to the
optional external sensor. The ICM-20948 has limited capabilities as an I2C Master, and depends on the system
processor to manage the initial configuration of any auxiliary sensors. The ICM-20948 has an interface bypass
multiplexer, which connects the system processor I2C bus pins 23 and 24 (SCL and SDA) directly to the auxiliary sensor
I2C bus pins 7 and 21 (AUX_CL and AUX_DA).
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Revision: 1.3
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ICM-20948
Once the auxiliary sensors have been configured by the system processor, the interface bypass multiplexer should be
disabled so that the ICM-20948 auxiliary I2C master can take control of the sensor I2C bus and gather data from the
auxiliary sensors.
Interrupt
Status
Register
I2C Processor Bus: for reading all
sensor data from MPU and for
configuring external sensors (i.e.
compass in this example)
INT1
ICM-20948
AD0
Slave I2C
or SPI
Serial
Interface
VDD or GND
SCL
SCL
SDA/SDI
SDA
System
Processor
FIFO
Sensor I2C Bus: for
configuring and reading
from external sensors
User & Config
Registers
Optional
Sensor
Master I2C
Serial
Interface
Sensor
Register
Interface
Bypass
Mux
AUX_CL
SCL
AUX_DA
SDA
External
Sensor
Factory
Calibration
Digital
Motion
Processor
(DMP)
Interface bypass mux allows
direct configuration of
compass by system processor
Bias & LDOs
VDD
GND
REGOUT
Figure 6. ICM-20948 Solution Using I2C Interface
ICM-20948 Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the ICM-20948. Pins 9, 22, 23, and 24 are used to support the
SDO, nCS, SCLK, and SDI signals for SPI communications. Because these SPI pins are shared with the I2C slave pins (9,
23 and 24), the system processor cannot access the auxiliary I2C bus through the interface bypass multiplexer, which
connects the processor I2C interface pins to the sensor I2C interface pins. Since the ICM-20948 has limited capabilities
as an I2C Master, and depends on the system processor to manage the initial configuration of any auxiliary sensors,
another method must be used for programming the sensors on the auxiliary sensor I2C bus pins 7 and 21 (AUX_CL and
AUX_DA).
When using SPI communications between the ICM-20948 and the system processor, configuration of devices on the
auxiliary I2C sensor bus can be achieved by using I2C Slaves 0-4 to perform read and write transactions on any device
and register on the auxiliary I2C bus. The I2C Slave 4 interface can be used to perform only single byte read and write
transactions. Once the external sensors have been configured, the ICM-20948 can perform single or multi-byte reads
using the sensor I2C bus. The read results from the Slave 0-3 controllers can be written to the FIFO buffer as well as to
the external sensor registers.
Document Number: DS-000189
Revision: 1.3
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ICM-20948
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU and external sensors
Interrupt
Status
Register
INT1
nCS
nCS
ICM-20948
SDO
2
Slave I C
or SPI
Serial
Interface
SDI
SCLK
SCLK
SDI
System
Processor
SDO
FIFO
Sensor I2C Bus: for
configuring and
reading data from
external sensors
Config
Register
Optional
Sensor
Master I2C
Serial
Interface
Sensor
Register
Interface
Bypass
Mux
AUX_CL
SCL
AUX_DA
SDA
External
Sensor
Factory
Calibration
Digital
Motion
Processor
(DMP)
I2C Master performs
read and write
transactions on
Sensor I2C bus.
Bias & LDOs
VDD
GND
REGOUT
Figure 7. ICM-20948 Solution Using SPI Interface
4.12 AUXILIARY I2C SERIAL INTERFACE
The ICM-20948 has an auxiliary I2C bus for communicating to external sensors. This bus has two operating modes:
•
•
I2C Master Mode: The ICM-20948 acts as a master to any external sensors connected to the auxiliary I2C bus
Pass-Through Mode: The ICM-20948 directly connects the primary and auxiliary I2C buses together, allowing
the system processor to directly communicate with any external sensors.
Auxiliary I2C Bus Modes of Operation:
•
•
I2C Master Mode: Allows the ICM-20948 to directly access the data registers of external sensors. In this
mode, the ICM-20948 directly obtains data from auxiliary sensors without intervention from the system
applications processor. The I2C Master can be configured to read up to 24 bytes from up to 4 auxiliary
sensors. A fifth sensor can be configured to work single byte read/write mode.
Pass-Through Mode: Allows an external system processor to act as master and directly communicate to the
external sensors connected to the auxiliary I2C bus pins (AUX_DA and AUX_CL). In this mode, the auxiliary I2C
bus control logic of the ICM-20948 is disabled, and the auxiliary I2C pins AUX_CL and AUX_DA (pins 7 and 21)
are connected to the main I2C bus (Pins 23 and 24) through analog switches internally. Pass-Through mode is
useful for configuring the external sensors.
4.13 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each
measurement axis can be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITHOUT SELF-TEST ENABLED
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Revision: 1.3
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ICM-20948
The self-test response for each gyroscope axis is defined in the gyroscope specification table, while that for each
accelerometer axis is defined in the accelerometer specification table.
When the value of the self-test response is within the specified min/max limits, the part has passed self-test. When
the self-test response exceeds the min/max values, the part is deemed to have failed self-test. It is recommended to
use InvenSense MotionApps software for executing self-test.
4.14 CLOCKING
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope
oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for
optimum sensor performance and power consumption will be automatically selected based on the power mode.
Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the
PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted
that the internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation
oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency
varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register
TIMEBASE_CORRECTION_PLL (detailed in section 12.5), and users can factor it in during distance and angle
calculations to not sacrifice accuracy. Other than that, PLL has better frequency stability and lower frequency variation
over temperature than the internal relaxation oscillator.
4.15 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyro, accelerometer, auxiliary sensor, and temperature measurement
data. They are read-only registers, and are accessed via the serial interface. Data from these registers may be read
anytime.
4.16 FIFO
The ICM-20948 contains a FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set) that is accessible
via the Serial Interface. The FIFO configuration register determines which data is written into the FIFO. Possible
choices include gyro data, accelerometer data, temperature readings, auxiliary sensor readings, and FSYNC input.
A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst
reads. The interrupt function may be used to determine when new data is available.
For further information regarding the FIFO, please refer to the Section 7.
4.17 FSYNC
The FSYNC pin can be used from an external interrupt source to wake up the device from sleep. It is particularly useful
in EIS applications to synchronize the gyroscope ODR with external inputs from an imaging sensor. Connecting the
VSYNC or HSYNC pin of the image sensor subsystem to FSYNC on ICM-20948 allows timing synchronization between
the two otherwise unconnected subsystems.
An FSYNC_ODR delay time register is used to capture the delay between an FSYNC pulse and the very next gyroscope
data ready pulse.
4.18 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the
INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Section 5 provides a
summary of interrupt sources. The interrupt status can be read from the Interrupt Status register.
For further information regarding interrupts, please refer to Section 7.
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ICM-20948
4.19 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-20948 die temperature. The readings from the
ADC can be read from the FIFO or the Sensor Data registers.
4.20 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM20948. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed
by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of Materials for External
Components.
4.21 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillators.
4.22 POWER MODES
Table 12 lists the user-accessible power modes for ICM-20948.
MODE
1
2
3
4
5
6
7
8
NAME
Sleep Mode
Low-Power Accelerometer Mode
Low-Noise Accelerometer Mode
Gyroscope Mode
Magnetometer Mode
Accel + Gyro Mode
Accel + Magnetometer Mode
9-Axis Mode
GYRO
Off
Off
Off
On
Off
On
Off
On
ACCEL
Off
Duty-Cycled
On
Off
Off
On
On
On
Table 12. Power Modes for ICM-20948
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Revision: 1.3
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MAGNETOMETER
Off
Off
Off
Off
On
Off
On
On
DMP
Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
ICM-20948
5 PROGRAMMABLE INTERRUPTS
The ICM-20948 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status
flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. Table 13 lists the
interrupt sources.
INTERRUPT SOURCE
DMP Interrupt
Wake on Motion Interrupt
PLL RDY Interrupt
I2C Master Interrupt
Raw Data Ready Interrupt
FIFO Overflow Interrupt
FIFO Watermark Interrupt
Table 13. Interrupt Sources
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Revision: 1.3
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ICM-20948
6 DIGITAL INTERFACE
6.1
I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20948 can be accessed using either I2C at 400 kHz or SPI at 7 MHz. SPI
operates in four-wire mode.
PIN NUMBER
PIN NAME
9
AD0 / SDO
I2C Slave Address LSB (AD0); SPI serial data output (SDO)
PIN DESCRIPTION
22
23
24
nCS
SCL / SCLK
SDA / SDI
Chip select (SPI mode only)
I2C serial clock (SCL); SPI serial clock (SCLK)
I2C serial data (SDA); SPI serial data input (SDI)
Table 14. Serial Interface
NOTE: To prevent switching into
mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit. Setting
this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in Section 6.3.
I2C
For further information regarding the I2C_IF_DIS bit, please refer to Section 7.
6.2
I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ICM-20948 always operates as a slave device when communicating to the system processor, which thus acts as
the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20948 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is determined by
the logic level on pin AD0. This allows two ICM-20948s to be connected to the same I2C bus. When used in this
configuration, the address of the one of the devices should be b1101000 (pin AD0 is logic low) and the address of the
other should be b1101001 (pin AD0 is logic high).
6.3
I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a
HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until
the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while
SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
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ICM-20948
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and
holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can
hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and
releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an
8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the
slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device.
Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line
LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with
a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START
condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on
the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
START ADDRESS
condition
P
R/W
ACK
DATA
ACK
Figure 10. Complete I2C Data Transfer
Document Number: DS-000189
Revision: 1.3
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DATA
ACK
STOP
condition
ICM-20948
To write the internal ICM-20948 registers, the master transmits the start condition (S), followed by the I2C address and
the write bit (0). At the 9th clock cycle (when the clock is high), the ICM-20948 acknowledges the transfer. Then the
master puts the register address (RA) on the bus. After the ICM-20948 acknowledges the reception of the register
address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be
concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue
outputting data rather than transmitting a stop signal. In this case, the ICM-20948 automatically increments the
register address and loads the data to the appropriate register. The following figures show single and two-byte write
sequences.
Single-Byte Write Sequence
Master
S
AD+W
RA
Slave
ACK
DATA
ACK
P
ACK
Burst Write Sequence
Master
S
AD+W
RA
Slave
ACK
DATA
ACK
DATA
ACK
P
ACK
To read the internal ICM-20948 registers, the master sends a start condition, followed by the I2C address and a write
bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM-20948, the
master transmits a start signal followed by the slave address and read bit. As a result, the ICM-20948 sends an ACK
signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The
NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The following figures show single
and two-byte read sequences.
Single-Byte Read Sequence
Master
S
AD+W
Slave
RA
ACK
S
AD+R
ACK
NACK
ACK
P
DATA
Burst Read Sequence
Master
S
AD+W
Slave
6.4
RA
ACK
S
AD+R
ACK
ACK
ACK
DATA
NACK
DATA
I2C TERMS
SIGNAL
S
AD
W
R
ACK
NACK
RA
DATA
P
DESCRIPTION
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-20948 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 15. I2C Terms
Document Number: DS-000189
Revision: 1.3
Page 30 of 89
P
ICM-20948
6.5
SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20948 always
operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO) and the Serial Data Input (SDI)
are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a
time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held
high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active
devices.
SPI Operational Features
1.
2.
3.
4.
5.
Data is delivered MSB first and LSB last
Data is latched on the rising edge of SCLK
Data should be transitioned on the falling edge of SCLK
The maximum frequency of SCLK is 7MHz
SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte
contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte
contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits contain the
Register Address. In cases of multiple-byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
R/W
LSB
A6
A5
A4
A3
A2
A1
A0
D5
D4
D3
D2
D1
D0
SPI Data format
MSB
D7
6.
LSB
D6
Supports Single or Burst Read/Writes.
SCLK
SDI
SDO
SPI Master
/CS1
SPI Slave 1
/CS
/CS2
SCLK
SDI
SDO
/CS
SPI Slave 2
Figure 11. Typical SPI Master / Slave Configuration
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Revision: 1.3
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ICM-20948
7 REGISTER MAP FOR GYROSCOPE AND ACCELEROMETER
The following table lists the register map for the ICM-20948, for user banks 0, 1, 2, 3.
7.1
ADDR
(HEX)
USER BANK 0 REGISTER MAP
ADDR
(DEC.)
REGISTER NAME
SERIAL
I/F
BIT7
BIT6
00
0
WHO_AM_I
R
WHO_AM_I[7:0]
03
3
USER_CTRL
R/W
DMP_EN
BIT5
BIT4
BIT3
FIFO_EN
I2C_MST_EN
I2C_IF_DIS
DMP_RST
I2C_MST_CY
CLE
ACCEL_CYCLE
GYRO_CYCLE
-
SLEEP
LP_EN
-
TEMP_DIS
05
5
LP_CONFIG
R/W
06
6
PWR_MGMT_1
R/W
DEVICE_RESE
T
07
7
PWR_MGMT_2
R/W
-
DISABLE_ACCEL
INT1_LATCH_
INT_EN
0F
15
INT_PIN_CFG
R/W
INT1_ACTL
INT1_OPEN
10
16
INT_ENABLE
R/W
REG_WOF_E
N
-
11
17
INT_ENABLE_1
R/W
-
12
18
INT_ENABLE_2
R/W
-
13
19
INT_ENABLE_3
R/W
-
SRAM_RST
BIT1
BIT0
I2C_MST_RST
-
CLKSEL[2:0]
DISABLE_GYRO
INT_ANYRD_
2CLEAR
ACTL_FSYNC
FSYNC_INT_
MODE_EN
BYPASS_EN
-
WOM_INT_E
N
PLL_RDY_EN
DMP_INT1_E
N
I2C_MST_INT
_EN
RAW_DATA_
0_RDY_EN
FIFO_OVERFLOW_EN[4:0]
FIFO_WM_EN[4:0]
17
23
I2C_MST_STATUS
R/C
PASS_THROU
GH
19
25
INT_STATUS
R/C
-
1A
26
INT_STATUS_1
R/C
-
1B
27
INT_STATUS_2
R/C
-
FIFO_OVERFLOW_INT[4:0]
1C
28
INT_STATUS_3
R/C
-
FIFO_WM_INT[4:0]
28
40
DELAY_TIMEH
R
DELAY_TIMEH[7:0]
29
41
DELAY_TIMEL
R
DELAY_TIMEL[7:0]
2D
45
ACCEL_XOUT_H
R
ACCEL_XOUT_H[7:0]
2E
46
ACCEL_XOUT_L
R
ACCEL_XOUT_L[7:0]
2F
47
ACCEL_YOUT_H
R
ACCEL_YOUT_H[7:0]
30
48
ACCEL_YOUT_L
R
ACCEL_YOUT_L[7:0]
31
49
ACCEL_ZOUT_H
R
ACCEL_ZOUT_H[7:0]
32
50
ACCEL_ZOUT_L
R
ACCEL_ZOUT_L[7:0]
33
51
GYRO_XOUT_H
R
GYRO_XOUT_H[7:0]
34
52
GYRO_XOUT_L
R
GYRO_XOUT_L[7:0]
35
53
GYRO_YOUT_H
R
GYRO_YOUT_H[7:0]
36
54
GYRO_YOUT_L
R
GYRO_YOUT_L[7:0]
37
55
GYRO_ZOUT_H
R
GYRO_ZOUT_H[7:0]
38
56
GYRO_ZOUT_L
R
GYRO_ZOUT_L[7:0]
39
57
TEMP_OUT_H
R
TEMP_OUT_H[7:0]
3A
58
TEMP_OUT_L
R
TEMP_OUT_L[7:0]
3B
59
EXT_SLV_SENS_DATA_00
R
EXT_SLV_SENS_DATA_00[7:0]
3C
60
EXT_SLV_SENS_DATA_01
R
EXT_SLV_SENS_DATA_01[7:0]
3D
61
EXT_SLV_SENS_DATA_02
R
EXT_SLV_SENS_DATA_02[7:0]
3E
62
EXT_SLV_SENS_DATA_03
R
EXT_SLV_SENS_DATA_03[7:0]
3F
63
EXT_SLV_SENS_DATA_04
R
EXT_SLV_SENS_DATA_04[7:0]
40
64
EXT_SLV_SENS_DATA_05
R
EXT_SLV_SENS_DATA_05[7:0]
41
65
EXT_SLV_SENS_DATA_06
R
EXT_SLV_SENS_DATA_06[7:0]
42
66
EXT_SLV_SENS_DATA_07
R
EXT_SLV_SENS_DATA_07[7:0]
43
67
EXT_SLV_SENS_DATA_08
R
EXT_SLV_SENS_DATA_08[7:0]
Document Number: DS-000189
Revision: 1.3
BIT2
I2C_SLV4_DO
NE
I2C_LOST_AR
B
I2C_SLV4_NA
CK
I2C_SLV3_NA
CK
I2C_SLV2_NA
CK
I2C_SLV1_NA
CK
I2C_SLV0_NA
CK
WOM_INT
PLL_RDY_INT
DMP_INT1
I2C_MST_INT
RAW_DATA_
0_RDY_INT
Page 32 of 89
ICM-20948
ADDR
(HEX)
ADDR
(DEC.)
REGISTER NAME
SERIAL
I/F
BIT7
BIT6
BIT5
BIT4
44
68
EXT_SLV_SENS_DATA_09
R
EXT_SLV_SENS_DATA_09[7:0]
45
69
EXT_SLV_SENS_DATA_10
R
EXT_SLV_SENS_DATA_10[7:0]
46
70
EXT_SLV_SENS_DATA_11
R
EXT_SLV_SENS_DATA_11[7:0]
47
71
EXT_SLV_SENS_DATA_12
R
EXT_SLV_SENS_DATA_12[7:0]
48
72
EXT_SLV_SENS_DATA_13
R
EXT_SLV_SENS_DATA_13[7:0]
49
73
EXT_SLV_SENS_DATA_14
R
EXT_SLV_SENS_DATA_14[7:0]
4A
74
EXT_SLV_SENS_DATA_15
R
EXT_SLV_SENS_DATA_15[7:0]
4B
75
EXT_SLV_SENS_DATA_16
R
EXT_SLV_SENS_DATA_16[7:0]
4C
76
EXT_SLV_SENS_DATA_17
R
EXT_SLV_SENS_DATA_17[7:0]
4D
77
EXT_SLV_SENS_DATA_18
R
EXT_SLV_SENS_DATA_18[7:0]
4E
78
EXT_SLV_SENS_DATA_19
R
EXT_SLV_SENS_DATA_19[7:0]
4F
79
EXT_SLV_SENS_DATA_20
R
EXT_SLV_SENS_DATA_20[7:0]
50
80
EXT_SLV_SENS_DATA_21
R
EXT_SLV_SENS_DATA_21[7:0]
51
81
EXT_SLV_SENS_DATA_22
R
EXT_SLV_SENS_DATA_22[7:0]
52
82
EXT_SLV_SENS_DATA_23
R
EXT_SLV_SENS_DATA_23[7:0]
66
102
FIFO_EN_1
R/W
-
67
103
FIFO_EN_2
R/W
-
ACCEL_FIFO_
EN
68
104
FIFO_RST
R/W
-
FIFO_RESET[4:0]
69
105
FIFO_MODE
R/W
-
FIFO_MODE[4:0]
70
112
FIFO_COUNTH
R
-
FIFO_CNT[12:8]
71
113
FIFO_COUNTL
R
FIFO_CNT[7:0]
72
114
FIFO_R_W
R/W
FIFO_R_W[7:0]
74
116
DATA_RDY_STATUS
R/C
WOF_STATU
S
76
118
FIFO_CFG
R/W
-
7F
127
REG_BANK_SEL
R/W
-
7.2
-
BIT3
BIT2
BIT1
BIT0
SLV_3_FIFO_
EN
SLV_2_FIFO_
EN
SLV_1_FIFO_
EN
SLV_0_FIFO_
EN
GYRO_Z_FIF
O_EN
GYRO_Y_FIF
O_EN
GYRO_X_FIF
O_EN
TEMP_FIFO_
EN
RAW_DATA_RDY[3:0]
FIFO_CFG
USER_BANK[1:0]
-
USER BANK 1 REGISTER MAP
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
02
2
SELF_TEST_X_GYRO
R/W
XG_ST_DATA[7:0]
03
3
SELF_TEST_Y_GYRO
R/W
YG_ST_DATA[7:0]
04
4
SELF_TEST_Z_GYRO
R/W
ZG_ST_DATA[7:0]
0E
14
SELF_TEST_X_ACCEL
R/W
XA_ST_DATA[7:0]
0F
15
SELF_TEST_Y_ACCEL
R/W
YA_ST_DATA[7:0]
10
16
SELF_TEST_Z_ACCEL
R/W
ZA_ST_DATA[7:0]
14
20
XA_OFFS_H
R/W
XA_OFFS[14:7]
15
21
XA_OFFS_L
R/W
17
23
YA_OFFS_H
R/W
18
24
YA_OFFS_L
R/W
1A
26
ZA_OFFS_H
R/W
1B
27
ZA_OFFS_L
R/W
Document Number: DS-000189
Revision: 1.3
Bit7
Bit6
Bit5
Bit4
Bit3
XA_OFFS[6:0]
Bit2
Bit1
Bit0
-
YA_OFFS[14:7]
YA_OFFS[6:0]
-
ZA_OFFS[14:7]
ZA_OFFS[6:0]
Page 33 of 89
-
ICM-20948
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
28
40
TIMEBASE_CORRECTIO
N_PLL
R/W
7F
127
REG_BANK_SEL
R/W
7.3
ADDR
(HEX)
Bit7
Bit6
Bit5
Bit4
-
USER_BANK[1:0]
Bit1
Bit0
BIT1
BIT0
-
USER BANK 2 REGISTER MAP
ADDR
(DEC.)
REGISTER NAME
SERIAL
I/F
BIT7
BIT6
BIT5
BIT4
0
GYRO_SMPLRT_DIV
R/W
GYRO_SMPLRT_DIV[7:0]
01
1
GYRO_CONFIG_1
R/W
-
GYRO_DLPFCFG[2:0]
02
2
GYRO_CONFIG_2
R/W
-
XGYRO_CTEN
03
3
XG_OFFS_USRH
R/W
X_OFFS_USER[15:8]
04
4
XG_OFFS_USRL
R/W
X_OFFS_USER[7:0]
05
5
YG_OFFS_USRH
R/W
Y_OFFS_USER[15:8]
06
6
YG_OFFS_USRL
R/W
Y_OFFS_USER[7:0]
07
7
ZG_OFFS_USRH
R/W
Z_OFFS_USER[15:8]
08
8
ZG_OFFS_USRL
R/W
Z_OFFS_USER[7:0]
09
9
ODR_ALIGN_EN
R/W
-
10
16
ACCEL_SMPLRT_DIV_1
R/W
-
11
17
ACCEL_SMPLRT_DIV_2
R/W
ACCEL_SMPLRT_DIV[7:0]
12
18
ACCEL_INTEL_CTRL
R/W
-
13
19
ACCEL_WOM_THR
R/W
WOM_THRESHOLD[7:0]
14
20
ACCEL_CONFIG
R/W
-
15
21
ACCEL_CONFIG_2
R/W
-
BIT2
GYRO_FCHOI
CE
GYRO_FS_SEL[1:0]
YGYRO_CTEN
ZGYRO_CTEN
GYRO_AVGCFG[2:0]
ACCEL_SMPLRT_DIV[11:8]
ACCEL_INTEL
_EN
ACCEL_DLPFCFG[2:0]
52
82
FSYNC_CONFIG
R/W
53
83
TEMP_CONFIG
R/W
-
54
84
MOD_CTRL_USR
R/W
-
7F
127
REG_BANK_SEL
R/W
-
7.4
BIT3
ODR_ALIGN_
EN
DELAY_TIME
_EN
00
Bit2
TBC_PLL[7:0]
00
ADDR
(HEX)
Bit3
WOF_DEGLIT
CH_EN
-
ACCEL_FCHOI
CE
ACCEL_FS_SEL[1:0]
AX_ST_EN_R
EG
AY_ST_EN_R
EG
AZ_ST_EN_R
EG
WOF_EDGE_I
NT
EXT_SYNC_SET[3:0]
ACCEL_INTEL
_MODE_INT
DEC3_CFG[1:0]
TEMP_DLPFCFG[2:0]
REG_LP_DMP
_EN
USER_BANK[1:0]
-
USER BANK 3 REGISTER MAP
ADDR
(DEC.)
0
REGISTER NAME
I2C_MST_ODR_CONFIG
SERIAL
I/F
BIT7
R/W
-
BIT6
BIT4
BIT3
BIT2
BIT1
BIT0
I2C_SLV1_DE
LAY_EN
I2C_SLV0_DE
LAY_EN
I2C_MST_ODR_CONFIG[3:0]
01
1
I2C_MST_CTRL
R/W
MULT_MST_
EN
02
2
I2C_MST_DELAY_CTRL
R/W
DELAY_ES_S
HADOW
-
03
3
I2C_SLV0_ADDR
R/W
I2C_SLV0_RN
W
I2C_ID_0[6:0]
04
4
I2C_SLV0_REG
R/W
I2C_SLV0_REG[7:0]
05
5
I2C_SLV0_CTRL
R/W
I2C_SLV0_EN
06
6
I2C_SLV0_DO
R/W
I2C_SLV0_DO[7:0]
07
7
I2C_SLV1_ADDR
R/W
I2C_SLV1_RN
W
08
8
I2C_SLV1_REG
R/W
I2C_SLV1_REG[7:0]
09
9
I2C_SLV1_CTRL
R/W
I2C_SLV1_EN
Document Number: DS-000189
Revision: 1.3
BIT5
-
I2C_MST_P_
NSR
I2C_MST_CLK[3:0]
I2C_SLV4_DE
LAY_EN
I2C_SLV3_DE
LAY_EN
I2C_SLV0_RE
G_DIS
I2C_SLV0_GR
P
I2C_SLV0_LENG[3:0]
I2C_SLV1_RE
G_DIS
I2C_SLV1_GR
P
I2C_SLV1_LENG[3:0]
I2C_SLV0_BY
TE_SW
I2C_SLV2_DE
LAY_EN
I2C_ID_1[6:0]
I2C_SLV1_BY
TE_SW
Page 34 of 89
ICM-20948
ADDR
(HEX)
ADDR
(DEC.)
REGISTER NAME
SERIAL
I/F
BIT7
BIT6
0A
10
I2C_SLV1_DO
R/W
I2C_SLV1_DO[7:0]
0B
11
I2C_SLV2_ADDR
R/W
I2C_SLV2_RN
W
0C
12
I2C_SLV2_REG
R/W
I2C_SLV2_REG[7:0]
0D
13
I2C_SLV2_CTRL
R/W
I2C_SLV2_EN
0E
14
I2C_SLV2_DO
R/W
I2C_SLV2_DO[7:0]
0F
15
I2C_SLV3_ADDR
R/W
I2C_SLV3_RN
W
10
16
I2C_SLV3_REG
R/W
I2C_SLV3_REG[7:0]
11
17
I2C_SLV3_CTRL
R/W
I2C_SLV3_EN
12
18
I2C_SLV3_DO
R/W
I2C_SLV3_DO[7:0]
13
19
I2C_SLV4_ADDR
R/W
I2C_SLV4_RN
W
14
20
I2C_SLV4_REG
R/W
I2C_SLV4_REG[7:0]
15
21
I2C_SLV4_CTRL
R/W
I2C_SLV4_EN
16
22
I2C_SLV4_DO
R/W
I2C_SLV4_DO[7:0]
17
23
I2C_SLV4_DI
R
I2C_SLV4_DI[7:0]
7F
127
REG_BANK_SEL
R/W
-
Document Number: DS-000189
Revision: 1.3
BIT5
BIT4
BIT3
I2C_SLV2_RE
G_DIS
I2C_SLV2_GR
P
I2C_SLV2_LENG[3:0]
I2C_SLV3_RE
G_DIS
I2C_SLV3_GR
P
I2C_SLV3_LENG[3:0]
I2C_SLV4_RE
G_DIS
I2C_SLV4_DLY[4:0]
I2C_ID_2[6:0]
I2C_SLV2_BY
TE_SW
I2C_ID_3[6:0]
I2C_SLV3_BY
TE_SW
I2C_ID_4[6:0]
I2C_SLV4_BY
TE_SW
USER_BANK[1:0]
Page 35 of 89
-
BIT2
BIT1
BIT0
ICM-20948
8 USER BANK 0 REGISTER DESCRIPTIONS
This section describes the function and contents of the User Bank 0 Register Map within the ICM-20948.
NOTE: The device will come up in sleep mode upon power-up.
8.1
WHO_AM_I
Name: WHO_AM_I
Address: 0 (00h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0xEA
BIT
NAME
7:0
WHO_AM_I[7:0]
8.2
FUNCTION
Register to indicate to user which device is being accessed.
The value for ICM-20948 is 0xEA.
USER_CTRL
Name: USER_CTRL
Address: 3 (03h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
DMP_EN
6
FIFO_EN
5
I2C_MST_EN
4
3
I2C_IF_DIS
DMP_RST
2
SRAM_RST
1
I2C_MST_RST
FUNCTION
1 – Enables DMP features.
0 – DMP features are disabled after the current processing round has completed.
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
To disable FIFO writes by DMA, use FIFO_EN register. To disable possible FIFO writes
from DMP, disable the DMP.
1 – Enable the I2C Master I/F module; pins ES_DA and ES_SCL are isolated from pins
SDA/SDI and SCL/ SCLK.
0 – Disable I2C Master I/F module; pins ES_DA and ES_SCL are logically driven by pins
SDA/SDI and SCL/ SCLK.
1 – Reset I2C Slave module and put the serial interface in SPI mode only.
1 – Reset DMP module. Reset is asynchronous. This bit auto clears after one clock
cycle of the internal 20 MHz clock.
1 – Reset SRAM module. Reset is asynchronous. This bit auto clears after one clock
cycle of the internal 20 MHz clock.
1 – Reset I2C Master module. Reset is asynchronous. This bit auto clears after one
clock cycle of the internal 20 MHz clock.
NOTE: This bit should only be set when the I2C master has hung. If this bit is set during an active
I2C master transaction, the I2C slave will hang, which will require the host to reset the slave.
0
-
Document Number: DS-000189
Revision: 1.3
Reserved.
Page 36 of 89
ICM-20948
8.3
LP_CONFIG
Name: LP_CONFIG
Address: 5 (05h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x40
BIT
NAME
7
6
I2C_MST_CYCLE
5
ACCEL_CYCLE
4
GYRO_CYCLE
3:0
-
8.4
FUNCTION
Reserved.
1 - Operate I2C master in duty cycled mode. ODR is determined by
I2C_MST_ODR_CONFIG register.
0 – Disable I2C master duty cycled mode.
1 – Operate ACCEL in duty cycled mode. ODR is determined by ACCEL_SMPLRT_DIV
register.
0 – Disable ACCEL duty cycled mode.
1 – Operate GYRO in duty cycled mode. ODR is determined by GYRO_SMPLRT_DIV
register.
0 – Disable GYRO duty cycled mode.
Reserved.
PWR_MGMT_1
Name: PWR_MGMT_1
Address: 6 (06h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x41
BIT
NAME
7
DEVICE_RESET
6
SLEEP
5
LP_EN
4
3
2:0
TEMP_DIS
CLKSEL[2:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
1 – Reset the internal registers and restores the default settings. Write a 1 to set the
reset, the bit will auto clear.
When set, the chip is set to sleep mode (in sleep mode all analog is powered off).
Clearing the bit wakes the chip from sleep mode.
The LP_EN only affects the digital circuitry, it helps to reduce the digital current when
sensors are in LP mode. Please note that the sensors themselves are set in LP mode
by the LP_CONFIG register settings. Sensors in LP mode, and use of LP_EN bit
together help to reduce overall current. The bit settings are:
1: Turn on low power feature.
0: Turn off low power feature.
LP_EN has no effect when the sensors are in low-noise mode.
Reserved.
When set to 1, this bit disables the temperature sensor.
Code: Clock Source
0: Internal 20 MHz oscillator
1-5: Auto selects the best available clock source – PLL if ready, else use the Internal oscillator
6: Internal 20 MHz oscillator
7: Stops the clock and keeps timing generator in reset
NOTE: CLKSEL[2:0] should be set to 1~5 to achieve full gyroscope performance.
Page 37 of 89
ICM-20948
8.5
PWR_MGMT_2
Name: PWR_MGMT_2
Address: 7 (07h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:6
5:3
DISABLE_ACCEL
2:0
8.6
DISABLE_GYRO
FUNCTION
Reserved.
Only the following values are applicable:
111 – Accelerometer (all axes) disabled.
000 – Accelerometer (all axes) on.
Only the following values are applicable:
111 – Gyroscope (all axes) disabled.
000 – Gyroscope (all axes) on.
INT_PIN_CFG
Name: INT_PIN_CFG
Address: 15 (0Fh)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
INT1_ACTL
6
INT1_OPEN
5
INT1_LATCH__EN
4
INT_ANYRD_2CLEAR
3
ACTL_FSYNC
2
FSYNC_INT_MODE_EN
1
BYPASS_EN
0
-
Document Number: DS-000189
Revision: 1.3
FUNCTION
1 – The logic level for INT1 pin is active low.
0 – The logic level for INT1 pin is active high.
1 – INT1 pin is configured as open drain.
0 – INT1 pin is configured as push-pull.
1 – INT1 pin level held until interrupt status is cleared.
0 – INT1 pin indicates interrupt pulse is width 50 µs.
1 – Interrupt status in INT_STATUS is cleared (set to 0) if any read operation is
performed.
0 – Interrupt status in INT_STATUS is cleared (set to 0) only by reading INT_STATUS
register.
This bit only affects the interrupt status bits that are contained in the register
INT_STATUS, and the corresponding hardware interrupt.
This bit does not affect the interrupt status bits that are contained in registers
INT_STATUS_1, INT_STATUS_2, INT_STATUS_3, and the corresponding hardware
interrupt.
1 – The logic level for the FSYNC pin as an interrupt to the ICM-20948 is active low.
0 – The logic level for the FSYNC pin as an interrupt to the ICM-20948 is active high.
1 – This enables the FSYNC pin to be used as an interrupt. A transition to the active
level described by the ACTL_FSYNC bit will cause an interrupt. The status of the
interrupt is read in the I2C Master Status register PASS_THROUGH bit.
0 – This disables the FSYNC pin from causing an interrupt.
When asserted, the I2C_MASTER interface pins (ES_CL and ES_DA) will go into
‘bypass mode’ when the I2C master interface is disabled.
Reserved.
Page 38 of 89
ICM-20948
8.7
INT_ENABLE
Name: INT_ENABLE
Address: 16 (10h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
REG_WOF_EN
6:4
3
WOM_INT_EN
2
PLL_RDY_EN
1
DMP_INT1_EN
0
I2C_MST_INT_EN
8.8
INT_ENABLE_1
Name: INT_ENABLE_1
Address: 17 (11h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:1
0
RAW_DATA_0_RDY_EN
FUNCTION
1 – Enable wake on FSYNC interrupt.
0 – Function is disabled.
Reserved.
1 – Enable interrupt for wake on motion to propagate to interrupt pin 1.
0 – Function is disabled.
1 – Enable PLL RDY interrupt (PLL RDY means PLL is running and in use as the clock
source for the system) to propagate to interrupt pin 1.
0 – Function is disabled.
1 – Enable DMP interrupt to propagate to interrupt pin 1.
0 – Function is disabled.
1 – Enable I2C master interrupt to propagate to interrupt pin 1.
0 – Function is disabled.
FUNCTION
Reserved.
1 – Enable raw data ready interrupt from any sensor to propagate to interrupt
pin 1.
0 – Function is disabled.
8.9
INT_ENABLE_2
Name: INT_ENABLE_2
Address: 18 (12h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_OVERFLOW_EN[4:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
1 – Enable interrupt for FIFO overflow to propagate to interrupt pin 1.
0 – Function is disabled.
Page 39 of 89
ICM-20948
8.10 INT_ENABLE_3
Name: INT_ENABLE_3
Address: 19 (13h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_WM_EN[4:0]
FUNCTION
Reserved.
1 – Enable interrupt for FIFO watermark to propagate to interrupt pin 1.
0 – Function is disabled.
8.11 I2C_MST_STATUS
Name: I2C_MST_STATUS
Address: 23 (17h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7
PASS_THROUGH
6
I2C_SLV4_DONE
5
I2C_LOST_ARB
4
I2C_SLV4_NACK
3
I2C_SLV3_NACK
2
I2C_SLV2_NACK
1
I2C_SLV1_NACK
0
I2C_SLV0_NACK
FUNCTION
Status of FSYNC interrupt – used as a way to pass an external interrupt through this
chip to the host. If enabled in the INT_PIN_CFG register by asserting bit
FSYNC_INT_MODE_EN, this will cause an interrupt. A read of this register clears all
status bits in this register.
Asserted when I2C slave 4’s transfer is complete, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted, and if the
SLV4_DONE_INT_EN bit is asserted in the I2C_SLV4_CTRL register.
Asserted when I2C slave loses arbitration of the I2C bus, will cause an interrupt if bit
I2C_MST_INT_EN in the INT_ENABLE register is asserted.
Asserted when slave 4 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 3 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 2 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 1 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
Asserted when slave 0 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN
in the INT_ENABLE register is asserted.
8.12 INT_STATUS
Name: INT_STATUS
Address: 25 (19h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7:4
3
WOM_INT
2
PLL_RDY_INT
1
DMP_INT1
0
I2C_MST_INT
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
1 – Wake on motion interrupt occurred.
1 – Indicates that the PLL has been enabled and is ready (delay of 4 ms ensures lock).
1 – Indicates the DMP has generated INT1 interrupt.
1 – Indicates I2C master has generated an interrupt.
Page 40 of 89
ICM-20948
8.13 INT_STATUS_1
Name: INT_STATUS_1
Address: 26 (1Ah)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7:1
0
RAW_DATA_0_RDY_INT
FUNCTION
Reserved.
1 – Sensor Register Raw Data, from all sensors, is updated and ready to be read.
8.14 INT_STATUS_2
Name: INT_STATUS_2
Address: 27 (1Bh)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_OVERFLOW_INT[4:0]
FUNCTION
Reserved.
1 – FIFO Overflow interrupt occurred.
8.15 INT_STATUS_3
Name: INT_STATUS_3
Address: 28 (1Ch)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_WM_INT[4:0]
FUNCTION
Reserved.
1 – Watermark interrupt for FIFO occurred.
8.16 DELAY_TIMEH
Name: DELAY_TIMEH
Address: 40 (28h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
DELAY_TIMEH[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
High-byte of delay time between FSYNC event and the 1st gyro ODR event (after the
FSYNC event).
Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next
update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take
the next update due to an FSYNC event.
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8.17 DELAY_TIMEL
Name: DELAY_TIMEL
Address: 41 (29h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
DELAY_TIMEL[7:0]
FUNCTION
Low-byte of delay time between FSYNC event and the 1st gyro ODR event (after the
FSYNC event).
Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next
update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take
the next update due to an FSYNC event.
Delay time in µs = (DELAY_TIMEH * 256 + DELAY_TIMEL) * 0.9645
8.18 ACCEL_XOUT_H
Name: ACCEL_XOUT_H
Address: 45 (2Dh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_XOUT_H[7:0]
FUNCTION
High Byte of Accelerometer X-axis data.
8.19 ACCEL_XOUT_L
Name: ACCEL_XOUT_L
Address: 46 (2Eh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_XOUT_L[7:0]
FUNCTION
Low Byte of Accelerometer X-axis data.
To convert the output of the accelerometer to acceleration measurement use the
formula below:
X_acceleration = ACCEL_XOUT/Accel_Sensitivity
8.20 ACCEL_YOUT_H
Name: ACCEL_YOUT_H
Address: 47 (2Fh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_YOUT_H[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
High Byte of Accelerometer Y-axis data.
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8.21 ACCEL_YOUT_L
Name: ACCEL_YOUT_L
Address: 48 (30h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_YOUT_L[7:0]
FUNCTION
Low Byte of Accelerometer Y-axis data.
To convert the output of the accelerometer to acceleration measurement use the
formula below:
Y_acceleration = ACCEL_YOUT/Accel_Sensitivity
8.22 ACCEL_ZOUT_H
Name: ACCEL_ZOUT_H
Address: 49 (31h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_ZOUT_H[7:0]
FUNCTION
High Byte of Accelerometer Z-axis data.
8.23 ACCEL_ZOUT_L
Name: ACCEL_ZOUT_L
Address: 50 (32h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_ZOUT_L[7:0]
FUNCTION
Low Byte of Accelerometer Z-axis data.
To convert the output of the accelerometer to acceleration measurement use the
formula below:
Z_acceleration = ACCEL_ZOUT/Accel_Sensitivity
8.24 GYRO_XOUT_H
Name: GYRO_XOUT_H
Address: 51 (33h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
GYRO_XOUT_H[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
High Byte of Gyroscope X-axis data.
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8.25 GYRO_XOUT_L
Name: GYRO_XOUT_L
Address: 52 (34h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
GYRO_XOUT_L[7:0]
FUNCTION
Low Byte of Gyroscope X-axis data.
To convert the output of the gyroscope to angular rate measurement use the
formula below:
X_angular_rate = GYRO_XOUT/Gyro_Sensitivity
8.26 GYRO_YOUT_H
Name: GYRO_YOUT_H
Address: 53 (35h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
GYRO_YOUT_H[7:0]
FUNCTION
High Byte of Gyroscope Y-axis data.
8.27 GYRO_YOUT_L
Name: GYRO_YOUT_L
Address: 54 (36h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
GYRO_YOUT_L[7:0]
FUNCTION
Low Byte of Gyroscope Y-axis data.
To convert the output of the gyroscope to angular rate measurement use the
formula below:
Y_angular_rate = GYRO_YOUT/Gyro_Sensitivity
8.28 GYRO_ZOUT_H
Name: GYRO_ZOUT_H
Address: 55 (37h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
GYRO_ZOUT_H[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
High Byte of Gyroscope Z-axis data.
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8.29 GYRO_ZOUT_L
Name: GYRO_ZOUT_L
Address: 56 (38h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
GYRO_ZOUT_L[7:0]
FUNCTION
Low Byte of Gyroscope Z-axis data.
To convert the output of the gyroscope to angular rate measurement use the
formula below:
Z_angular_rate = GYRO_ZOUT/Gyro_Sensitivity
8.30 TEMP_OUT_H
Name: TEMP_OUT_H
Address: 57 (39h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
TEMP_OUT_H[7:0]
FUNCTION
High Byte of Temp sensor data.
8.31 TEMP_OUT_L
Name: TEMP_OUT_L
Address: 58 (3Ah)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
TEMP_OUT_L[7:0]
FUNCTION
Low Byte of Temp sensor data.
To convert the output of the temperature sensor to degrees C use the following
formula:
TEMP_degC = ((TEMP_OUT – RoomTemp_Offset)/Temp_Sensitivity) + 21degC
8.32 EXT_SLV_SENS_DATA_00
Name: EXT_SLV_SENS_DATA_00
Address: 59 (3Bh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_00[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
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8.33 EXT_SLV_SENS_DATA_01
Name: EXT_SLV_SENS_DATA_01
Address: 60 (3Ch)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_01[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.34 EXT_SLV_SENS_DATA_02
Name: EXT_SLV_SENS_DATA_02
Address: 61 (3Dh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_02[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.35 EXT_SLV_SENS_DATA_03
Name: EXT_SLV_SENS_DATA_03
Address: 62 (3Eh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_03[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.36 EXT_SLV_SENS_DATA_04
Name: EXT_SLV_SENS_DATA_04
Address: 63 (3Fh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_04[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 46 of 89
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8.37 EXT_SLV_SENS_DATA_05
Name: EXT_SLV_SENS_DATA_05
Address: 64 (40h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_05[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.38 EXT_SLV_SENS_DATA_06
Name: EXT_SLV_SENS_DATA_06
Address: 65 (41h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_06[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.39 EXT_SLV_SENS_DATA_07
Name: EXT_SLV_SENS_DATA_07
Address: 66 (42h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_07[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.40 EXT_SLV_SENS_DATA_08
Name: EXT_SLV_SENS_DATA_08
Address: 67 (43h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_08[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 47 of 89
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8.41 EXT_SLV_SENS_DATA_09
Name: EXT_SLV_SENS_DATA_09
Address: 68 (44h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_09[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.42 EXT_SLV_SENS_DATA_10
Name: EXT_SLV_SENS_DATA_10
Address: 69 (45h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_10[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.43 EXT_SLV_SENS_DATA_11
Name: EXT_SLV_SENS_DATA_11
Address: 70 (46h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_11[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.44 EXT_SLV_SENS_DATA_12
Name: EXT_SLV_SENS_DATA_12
Address: 71 (47h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_12[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 48 of 89
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8.45 EXT_SLV_SENS_DATA_13
Name: EXT_SLV_SENS_DATA_13
Address: 72 (48h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_13[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.46 EXT_SLV_SENS_DATA_14
Name: EXT_SLV_SENS_DATA_14
Address: 73 (49h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_14[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.47 EXT_SLV_SENS_DATA_15
Name: EXT_SLV_SENS_DATA_15
Address: 74 (4Ah)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_15[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.48 EXT_SLV_SENS_DATA_16
Name: EXT_SLV_SENS_DATA_16
Address: 75 (4Bh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_16[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
Page 49 of 89
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8.49 EXT_SLV_SENS_DATA_17
Name: EXT_SLV_SENS_DATA_17
Address: 76 (4Ch)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_17[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.50 EXT_SLV_SENS_DATA_18
Name: EXT_SLV_SENS_DATA_18
Address: 77 (4Dh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_18[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.51 EXT_SLV_SENS_DATA_19
Name: EXT_SLV_SENS_DATA_19
Address: 78 (4Eh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_19[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.52 EXT_SLV_SENS_DATA_20
Name: EXT_SLV_SENS_DATA_20
Address: 79 (4Fh)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_20[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
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8.53 EXT_SLV_SENS_DATA_21
Name: EXT_SLV_SENS_DATA_21
Address: 80 (50h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_21[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.54 EXT_SLV_SENS_DATA_22
Name: EXT_SLV_SENS_DATA_22
Address: 81 (51h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_22[7:0]
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
8.55 EXT_SLV_SENS_DATA_23
Name: EXT_SLV_SENS_DATA_23
Address: 82 (52h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
EXT_SLV_SENS_DATA_23[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The data
stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers.
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8.56 FIFO_EN_1
Name: FIFO_EN_1
Address: 102 (66h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:4
3
SLV_3_FIFO_EN
2
SLV_2_FIFO_EN
1
SLV_1_FIFO_EN
0
SLV_0_FIFO_EN
FUNCTION
Reserved.
1 – Write EXT_SENS_DATA registers associated to SLV_3 (as determined by
I2C_SLV2_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate;
0 – Function is disabled.
1 – Write EXT_SENS_DATA registers associated to SLV_2 (as determined by
I2C_SLV0_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate;
0 – Function is disabled.
1 – Write EXT_SENS_DATA registers associated to SLV_1 (as determined by
I2C_SLV0_CTRL and I2C_SLV1_CTRL) to the FIFO at the sample rate;
0 – Function is disabled.
1 – Write EXT_SENS_DATA registers associated to SLV_0 (as determined by
I2C_SLV0_CTRL) to the FIFO at the sample rate;
0 – Function is disabled.
8.57 FIFO_EN_2
Name: FIFO_EN_2
Address: 103 (67h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:5
4
ACCEL_FIFO_EN
3
GYRO_Z_FIFO_EN
2
GYRO_Y_FIFO_EN
1
GYRO_X_FIFO_EN
0
TEMP_FIFO_EN
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,
ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate;
0 – Function is disabled.
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate.
0 – Function is disabled.
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8.58 FIFO_RST
Name: FIFO_RST
Address: 104 (68h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_RESET[4:0]
FUNCTION
Reserved.
S/W FIFO reset. Assert and hold to set FIFO size to 0. Assert and de-assert to reset
FIFO.
8.59 FIFO_MODE
Name: FIFO_MODE
Address: 105 (69h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_MODE[4:0]
FUNCTION
Reserved.
0 – Stream.
1 – Snapshot.
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO,
replacing the oldest data.
8.60 FIFO_COUNTH
Name: FIFO_COUNTH
Address: 112 (70h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:5
4:0
FIFO_CNT[12:8]
FUNCTION
Reserved.
High Bits, count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
8.61 FIFO_COUNTL
Name: FIFO_COUNTL
Address: 113 (71h)
Type: USR0
Bank: 0
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
FIFO_CNT[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Low bits, count indicates the number of written bytes in the FIFO.
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8.62 FIFO_R_W
Name: FIFO_R_W
Address: 114 (72h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
FIFO_R_W[7:0]
FUNCTION
Reading from or writing to this register actually reads/writes the FIFO. For example,
to write a byte to the FIFO, write the desired byte value to FIFO_R_W[7:0]. To read a
byte from the FIFO, perform a register read operation and access the result in
FIFO_R_W[7:0].
8.63 DATA_RDY_STATUS
Name: DATA_RDY_STATUS
Address: 116 (74h)
Type: USR0
Bank: 0
Serial IF: R/C
Reset Value: 0x00
BIT
NAME
7
WOF_STATUS
6:4
3:0
RAW_DATA_RDY[3:0]
FUNCTION
Wake on FSYNC interrupt status. Cleared on read.
Reserved.
Data from sensors is copied to FIFO or SRAM.
Set when sequence controller kicks off on a sensor data load. Only bit 0 is relevant in
a single FIFO configuration. Cleared on read.
8.64 FIFO_CFG
Name: FIFO_CFG
Address: 118 (76h)
Type: USR0
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:1
0
FIFO_CFG
FUNCTION
Reserved.
This bit should be set to 1 if interrupt status for each sensor is required.
8.65 REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type: ALL
Bank: 0
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:6
5:4
USER_BANK[1:0]
3:0
-
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK.
0: Select USER BANK 0.
1: Select USER BANK 1.
2: Select USER BANK 2.
3: Select USER BANK 3.
Reserved.
Page 54 of 89
ICM-20948
9 USR BANK 1 REGISTER DESCRIPTIONS
This section describes the function and contents of the User Bank 1 Register Map within the ICM-20948.
NOTE: The device will come up in sleep mode upon power-up.
9.1
SELF_TEST_X_GYRO
Name: SELF_TEST_X_GYRO
Address: 2 (02h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
XG_ST_DATA[7:0]
9.2
SELF_TEST_Y_GYRO
Name: SELF_TEST_Y_GYRO
Address: 3 (03h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
YG_ST_DATA[7:0]
9.3
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against subsequent self-test
outputs performed by the end user.
SELF_TEST_Z_GYRO
Name: SELF_TEST_Z_GYRO
Address: 4 (04h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
ZG_ST_DATA[7:0]
9.4
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against subsequent self-test
outputs performed by the end user.
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against subsequent self-test
outputs performed by the end user.
SELF_TEST_X_ACCEL
Name: SELF_TEST_X_ACCEL
Address: 14 (0Eh)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
XA_ST_DATA[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Contains self-test data for the X Accelerometer.
Page 55 of 89
ICM-20948
9.5
SELF_TEST_Y_ACCEL
Name: SELF_TEST_Y_ACCEL
Address: 15 (0Fh)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
YA_ST_DATA[7:0]
9.6
SELF_TEST_Z_ACCEL
Name: SELF_TEST_Z_ACCEL
Address: 16 (10h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
ZA_ST_DATA[7:0]
9.7
FUNCTION
Contains self-test data for the Y Accelerometer.
FUNCTION
Contains self-test data for the Z Accelerometer.
XA_OFFS_H
Name: XA_OFFS_H
Address: 20 (14h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
NAME
FUNCTION
7:0
XA_OFFS[14:7]
Upper bits of the X accelerometer offset cancellation.
9.8
XA_OFFS_L
Name: XA_OFFS_L
Address: 21 (15h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
NAME
FUNCTION
7:1
XA_OFFS[6:0]
Lower bits of the X accelerometer offset cancellation.
0
Reserved.
9.9
YA_OFFS_H
Name: YA_OFFS_H
Address: 23 (17h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
NAME
FUNCTION
7:0
YA_OFFS[14:7]
Upper bits of the Y accelerometer offset cancellation.
Document Number: DS-000189
Revision: 1.3
Page 56 of 89
ICM-20948
9.10 YA_OFFS_L
Name: YA_OFFS_L
Address: 24 (18h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
NAME
FUNCTION
7:1
YA_OFFS[6:0]
Lower bits of the Y accelerometer offset cancellation.
0
Reserved .
9.11 ZA_OFFS_H
Name: ZA_OFFS_H
Address: 26 (1Ah)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
NAME
FUNCTION
7:0
ZA_OFFS[14:7]
Upper bits of the Z accelerometer offset cancellation.
9.12 ZA_OFFS_L
Name: ZA_OFFS_L
Address: 27 (1Bh)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: Trimmed on a per-part basis for optimal performance
BIT
NAME
FUNCTION
7:1
ZA_OFFS[6:0]
Lower bits of the Z accelerometer offset cancellation.
0
Reserved.
9.13 TIMEBASE_CORRECTION_PLL
Name: TIMEBASE_CORRECTION_PLL
Address: 40 (28h)
Type: USR1
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
TBC_PLL[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
System PLL clock period error (signed, [-10%, +10%]).
Page 57 of 89
ICM-20948
9.14 REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type:
Bank: 1
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:6
5:4
USER_BANK[1:0]
3:0
-
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK.
0: Select USER BANK 0.
1: Select USER BANK 1.
2: Select USER BANK 2.
3: Select USER BANK 3.
Reserved.
Page 58 of 89
ICM-20948
10 USR BANK 2 REGISTER MAP
This section describes the function and contents of the User Bank 2 Register Map within the ICM-20948.
NOTE: The device will come up in sleep mode upon power-up.
10.1 GYRO_SMPLRT_DIV
Name: GYRO_SMPLRT_DIV
Address: 0 (00h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
GYRO_SMPLRT_DIV[7:0]
FUNCTION
Gyro sample rate divider. Divides the internal sample rate to generate the sample
rate that controls sensor data output rate, FIFO sample rate, and DMP sequence rate.
NOTE: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0), and
(0 < DLPF_CFG < 7).
ODR is computed as follows:
1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])
10.2 GYRO_CONFIG_1
Name: GYRO_CONFIG_1
Address: 1 (01h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x01
BIT
NAME
7:6
5:3
GYRO_DLPFCFG[2:0]
2:1
GYRO_FS_SEL[1:0]
0
GYRO_FCHOICE
FUNCTION
Reserved.
Gyro low pass filter configuration as shown in Table 16.
Gyro Full Scale Select:
00 = ±250 dps
01= ±500 dps
10 = ±1000 dps
11 = ±2000 dps
0 – Bypass gyro DLPF.
1 – Enable gyro DLPF.
The gyroscope DLPF is configured by GYRO_DLPFCFG, when GYRO_FCHOICE = 1. The gyroscope data is filtered
according to the value of GYRO_DLPFCFG and GYRO_FCHOICE as shown in Table 16.
Document Number: DS-000189
Revision: 1.3
Page 59 of 89
ICM-20948
OUTPUT
GYRO_FCHOICE
GYRO_DLPFCFG
3DB BW
[HZ]
NBW [HZ]
0
x
12106
12316
1
0
196.6
229.8
1
1
151.8
187.6
1
2
119.5
154.3
1
3
51.2
73.3
1
4
23.9
35.9
1
5
11.6
17.8
1
6
5.7
8.9
1
7
361.4
376.5
RATE [HZ]
9000
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
1125/(1+GYRO_SMPLRT_DIV)Hz where
GYRO_SMPLRT_DIV is 0, 1, 2,…255
Table 16. Gyroscope Configuration 1
10.3 GYRO_CONFIG_2
Name: GYRO_CONFIG_2
Address: 2 (02h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:6
5
XGYRO_CTEN
4
YGYRO_CTEN
3
ZGYRO_CTEN
2:0
GYRO_AVGCFG[2:0]
FUNCTION
Reserved.
X Gyro self-test enable.
Y Gyro self-test enable.
Z Gyro self-test enable.
Averaging filter configuration settings for low-power mode.
0: 1x averaging.
1: 2x averaging.
2: 4x averaging.
3: 8x averaging.
4: 16x averaging.
5: 32x averaging.
6: 64x averaging.
7: 128x averaging.
Table 17 lists the gyroscope filter bandwidths available in the low-power mode of operation. In the low-power mode
of operation, the gyroscope is duty-cycled.
Document Number: DS-000189
Revision: 1.3
Page 60 of 89
ICM-20948
AVERAGES
1X
2X
4X
8X
16X
32X
64X
128X
GYRO_FCHOICE
1
1
1
1
1
1
1
1
GYRO_AVGCFG
0
1
2
3
4
5
6
7
TON [MS]
1.15
1.59
2.48
4.26
7.82
14.93
29.15
57.59
NBW [HZ]
773.5
469.8
257.8
134.8
68.9
34.8
17.5
8.8
RMS NOISE
[DPS-RMS] TYP
(BASED ON GYROSCOPE
NOISE: 0.011 DPS/√HZ)
0.31
0.24
0.18
0.13
0.09
0.06
0.05
0.03
GYRO_SMPLRT_DIV
ODR [HZ]
CURRENT CONSUMPTION [MA] TYP
255
4.4
1.04
1.05
1.05
1.06
1.09
1.14
1.24
1.45
64
17.3
1.07
1.08
1.10
1.15
1.25
1.45
1.85
N/A
63
17.6
1.07
1.08
1.11
1.16
1.26
1.46
1.87
32
34.1
1.10
1.12
1.17
1.27
1.47
1.86
31
35.2
1.10
1.13
1.18
1.28
1.48
1.89
22
48.9
1.13
1.16
1.23
1.37
1.66
2.22
16
66.2
1.16
1.21
1.30
1.49
1.88
15
70.3
1.17
1.22
1.32
1.52
1.93
10
102.3
1.23
1.30
1.45
1.74
2.34
8
125.0
1.27
1.36
1.54
1.90
7
140.6
1.30
1.40
1.60
2.01
5
187.5
1.38
1.52
1.79
2.33
4
225.0
1.45
1.62
1.94
3
281.3
1.56
1.76
2.17
2
375.0
1.74
2.00
1
562.5
2.09
Table 17. Gyroscope Configuration 2
NOTE: Ton is the ON time for motion measurement when the gyroscope is in duty cycle mode.
10.4 XG_OFFS_USRH
Name: XG_OFFS_USRH
Address: 3 (03h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
X_OFFS_USER[15:8]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Upper byte of X gyro offset cancellation.
Page 61 of 89
N/A
N/A
N/A
N/A
N/A
N/A
ICM-20948
10.5 XG_OFFS_USRL
Name: XG_OFFS_USRL
Address: 4 (04h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
X_OFFS_USER[7:0]
FUNCTION
Lower byte of X gyro offset cancellation.
10.6 YG_OFFS_USRH
Name: YG_OFFS_USRH
Address: 5 (05h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
Y_OFFS_USER[15:8]
FUNCTION
Upper byte of Y gyro offset cancellation.
10.7 YG_OFFS_USRL
Name: YG_OFFS_USRL
Address: 6 (06h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
Y_OFFS_USER[7:0]
FUNCTION
Lower byte of Y gyro offset cancellation.
10.8 ZG_OFFS_USRH
Name: ZG_OFFS_USRH
Address: 7 (07h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
Z_OFFS_USER[15:8]
FUNCTION
Upper byte of Z gyro offset cancellation.
10.9 ZG_OFFS_USRL
Name: ZG_OFFS_USRL
Address: 8 (08h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
Z_OFFS_USER[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Lower byte of Z gyro offset cancellation.
Page 62 of 89
ICM-20948
10.10 ODR_ALIGN_EN
Name: ODR_ALIGN_EN
Address: 9 (09h)
Type: USR2
Bank: 2
OTP: No
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:1
0
ODR_ALIGN_EN
FUNCTION
Reserved.
0: Disables ODR start-time alignment.
1: Enables ODR start-time alignment when any of the following registers is written
(with the same value or with different values): GYRO_SMPLRT_DIV,
ACCEL_SMPLRT_DIV_1, ACCEL_SMPLRT_DIV_2, I2C_MST_ODR_CONFIG.
10.11 ACCEL_SMPLRT_DIV_1
Name: ACCEL_SMPLRT_DIV_1
Address: 16 (10h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:4
3:0
ACCEL_SMPLRT_DIV[11:8]
FUNCTION
Reserved.
MSB for ACCEL sample rate div.
10.12 ACCEL_SMPLRT_DIV_2
Name: ACCEL_SMPLRT_DIV_2
Address: 17 (11h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
ACCEL_SMPLRT_DIV[7:0]
FUNCTION
LSB for ACCEL sample rate div.
ODR is computed as follows:
1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0])
10.13 ACCEL_INTEL_CTRL
Name: ACCEL_INTEL_CTRL
Address: 18 (12h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:2
1
ACCEL_INTEL_EN
0
ACCEL_INTEL_MODE_INT
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
Enable the WOM logic.
Selects WOM algorithm.
1 = Compare the current sample with the previous sample.
0 = Initial sample is stored, all future samples are compared to the initial sample.
Page 63 of 89
ICM-20948
10.14 ACCEL_WOM_THR
Name: ACCEL_WOM_THR
Address: 19 (13h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
WOM_THRESHOLD[7:0]
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for ACCEL
x/y/z axes. LSB = 4 mg. Range is 0 mg to 1020 mg.
10.15 ACCEL_CONFIG
Name: ACCEL_CONFIG
Address: 20 (14h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x01
BIT
NAME
7:6
5:3
ACCEL_DLPFCFG[2:0]
2:1
ACCEL_FS_SEL[1:0]
0
FUNCTION
Reserved.
Accelerometer low pass filter configuration as shown in Table 18.
Accelerometer Full Scale Select:
00: ±2g
01: ±4g
10: ±8g
11: ±16g
0: Bypass accel DLPF.
1: Enable accel DLPF.
ACCEL_FCHOICE
OUTPUT
ACCEL_FCHOICE
ACCEL_DLPFCFG
3DB BW
[HZ]
NBW [HZ]
0
x
1209
1248
1
0
246.0
265.0
1
1
246.0
265.0
1
2
111.4
136.0
1
3
50.4
68.8
1
4
23.9
34.4
1
5
11.5
17.0
1
6
5.7
8.3
1
7
473
499
RATE [HZ]
4500
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
1125/(1+ACCEL_SMPLRT_DIV)Hz where
ACCEL_SMPLRT_DIV is 0, 1, 2,…4095
Table 18. Accelerator Configuration
The data rate out of the DLPF filter block can be further reduced by a factor of
1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0]) where ACCEL_SMPLRT_DIV is a 12-bit integer.
Document Number: DS-000189
Revision: 1.3
Page 64 of 89
ICM-20948
10.16 ACCEL_CONFIG_2
Name: ACCEL_CONFIG_2
Address: 21 (15h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:5
4
AX_ST_EN_REG
3
AY_ST_EN_REG
2
AZ_ST_EN_REG
1:0
DEC3_CFG[1:0]
FUNCTION
Reserved.
X Accel self-test enable.
Y Accel self-test enable.
Z Accel self-test enable.
Controls the number of samples averaged in the accelerometer decimator:
0: Average 1 or 4 samples depending on ACCEL_FCHOICE (see Table 19).
1: Average 8 samples.
2: Average 16 samples.
3: Average 32 samples.
Table 19 lists the accelerometer filter bandwidths available in the low-power mode of operation. In the low-power
mode of operation, the accelerometer is duty-cycled.
AVERAGES
1X
4X
8X
16X
32X
ACCEL_FCHOICE
0
1
1
1
1
ACCEL_DLPFCFG
x
7
7
7
7
DEC3_CFG
0
0
1
2
3
TON (MS)
0.821
1.488
2.377
4.154
7.71
NBW (HZ)
1237.5
496.8
264.8
136.5
69.2
RMS NOISE
[MG-RMS] TYP
(BASED ON
ACCELEROMETER NOISE:
190µG/√HZ)
6.7
4.2
3.1
2.2
1.6
ACCEL_SMPLRT_DIV
ODR [HZ]
4095
0.27
6.2
6.3
6.5
6.9
7.6
2044
0.55
6.3
6.6
7.0
7.7
9.2
1022
1.1
6.7
7.2
8.0
9.4
12.3
513
2.2
7.3
8.4
9.9
12.8
18.6
255
4.4
8.7
10.9
13.8
19.7
31.4
127
8.8
11.4
15.8
21.6
33.3
56.7
63
17.6
16.8
25.6
37.3
60.7
107.5
31
35.2
27.6
45.2
68.6
115.3
208.9
22
48.9
36.1
60.5
93.0
158.1
288.3
15
10
70.3
102.3
49.2
84.3
131.1
224.7
411.9
68.9
119.9
188.0
324.1
596.3
7
140.6
92.4
162.7
256.3
443.3
N/A
Document Number: DS-000189
Revision: 1.3
Page 65 of 89
CURRENT CONSUMPTION [µA] TYP
ICM-20948
5
187.5
121.2
214.9
3
281.3
178.9
319.3
1
562.5
351.7
N/A
N/A
Table 19. Accelerator Configuration 2
NOTE: Ton is the ON time for motion measurement when the accelerometer is in duty cycle mode.
10.17 FSYNC_CONFIG
Name: FSYNC_CONFIG
Address: 82 (52h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
DELAY_TIME_EN
6
5
4
WOF_DEGLITCH_EN
WOF_EDGE_INT
3:0
EXT_SYNC_SET[3:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
0: Disables delay time measurement between FSYNC event and the first ODR event
(after FSYNC event).
1: Enables delay time measurement between FSYNC event and the first ODR event
(after FSYNC event).
Reserved.
Enable digital deglitching of FSYNC input for Wake on FSYNC.
0: FSYNC is a level interrupt for Wake on FSYNC.
1: FSYNC is an edge interrupt for Wake on FSYNC.
ACTL_FSYNC is used to set the polarity of the interrupt.
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET FSYNC bit location.
0: Function disabled.
1: TEMP_OUT_L[0].
2: GYRO_XOUT_L[0].
3: GYRO_YOUT_L[0].
4: GYRO_ZOUT_L[0].
5: ACCEL_XOUT_L[0].
6: ACCEL_YOUT_L[0].
7: ACCEL_ZOUT_L[0].
Page 66 of 89
ICM-20948
10.18 TEMP_CONFIG
Name: TEMP_CONFIG
Address: 83 (53h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
2:0
TEMP_DLPFCFG[2:0]
FUNCTION
Low pass filter configuration for temperature sensor as shown in the table below:
TEMP_DLPCFG
0
1
2
3
4
5
6
7
TEMP SENSOR
NBW (HZ)
7932.0
217.9
123.5
65.9
34.1
17.3
8.8
7932.0
10.19 MOD_CTRL_USR
Name: MOD_CTRL_USR
Address: 84 (54h)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x03
BIT
NAME
7:1
0
REG_LP_DMP_EN
FUNCTION
Reserved.
Enable turning on DMP in Low Power Accelerometer mode.
10.20 REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type: USR2
Bank: 2
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:6
5:4
USER_BANK[1:0]
3:0
-
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK.
0: Select USER BANK 0.
1: Select USER BANK 1.
2: Select USER BANK 2.
3: Select USER BANK 3.
Reserved.
Page 67 of 89
RATE (KHZ)
9
1.125
1.125
1.125
1.125
1.125
Rate (kHz)
9
ICM-20948
11 USR BANK 3 REGISTER MAP
This section describes the function and contents of the User Bank 3 Register Map within the ICM-20948.
NOTE: The device will come up in sleep mode upon power-up.
11.1 I2C_MST_ODR_CONFIG
Name: I2C_MST_ODR_CONFIG
Address: 0 (00h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:4
3:0
I2C_MST_ODR_CONFIG[3:0]
FUNCTION
Reserved
ODR configuration for external sensor when gyroscope and accelerometer are
disabled. ODR is computed as follows:
1.1 kHz/(2^((odr_config[3:0])) )
When gyroscope is enabled, all sensors (including I2C_MASTER) use the gyroscope
ODR. If gyroscope is disabled, then all sensors (including I2C_MASTER) use the
accelerometer ODR.
11.2 I2C_MST_CTRL
Name: I2C_MST_CTRL
Address: 1 (01h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
MULT_MST_EN
6:5
4
I2C_MST_P_NSR
3:0
I2C_MST_CLK[3:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Enables multi-master capability. When disabled, clocking to the I2C_MST_IF can be
disabled when not in use and the logic to detect lost arbitration is disabled.
Reserved.
This bit controls the I2C Master’s transition from one slave read to the next slave
read.
0 - There is a restart between reads.
1 - There is a stop between reads.
Sets I2C master clock frequency as shown in Table 23.
Page 68 of 89
ICM-20948
11.3 I2C_MST_DELAY_CTRL
Name: I2C_MST_DELAY_CTRL
Address: 2 (02h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
DELAY_ES_SHADOW
6:5
4
I2C_SLV4_DELAY_EN
3
I2C_SLV3_DELAY_EN
2
I2C_SLV2_DELAY_EN
1
I2C_SLV1_DELAY_EN
0
I2C_SLV0_DELAY_EN
FUNCTION
Delays shadowing of external sensor data until all data is received.
Reserved.
When enabled, slave 4 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 3 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 2 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 1 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 0 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
11.4 I2C_SLV0_ADDR
Name: I2C_SLV0_ADDR
Address: 3 (03h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV0_RNW
6:0
I2C_ID_0[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 0.
11.5 I2C_SLV0_REG
Name: I2C_SLV0_REG
Address: 4 (04h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV0_REG[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
I2C slave 0 register address from where to begin data transfer.
Page 69 of 89
ICM-20948
11.6 I2C_SLV0_CTRL
Name: I2C_SLV0_CTRL
Address: 5 (05h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV0_EN
6
I2C_SLV0_BYTE_SW
5
I2C_SLV0_REG_DIS
4
I2C_SLV0_GRP
3:0
I2C_SLV0_LENG[3:0]
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register, which is always EXT_SENS_DATA_00 for I2C slave 0.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV0_REG[0] = 1, or if the last byte
read has a register address lsb = 0.
For example, if I2C_SLV0_REG = 0x1, and I2C_SLV0_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_00,
2) the second and third bytes will be read and swapped, so the data read from address
0x2 will be stored at EXT_SENS_DATA_02, and the data read from address 0x3 will be
stored at EXT_SENS_DATA_01,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_03.
0 – No swapping occurs; bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or write
data.
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc.., or if
the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
Number of bytes to be read from I2C slave 0.
11.7 I2C_SLV0_DO
Name: I2C_SLV0_DO
Address: 6 (06h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV0_DO[7:0]
FUNCTION
Data out when slave 0 is set to write.
11.8 I2C_SLV1_ADDR
Name: I2C_SLV1_ADDR
Address: 7 (07h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV1_RNW
6:0
I2C_ID_1[6:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 1.
Page 70 of 89
ICM-20948
11.9 I2C_SLV1_REG
Name: I2C_SLV1_REG
Address: 8 (08h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV1_REG[7:0]
FUNCTION
I2C slave 1 register address from where to begin data transfer.
11.10 I2C_SLV1_CTRL
Name: I2C_SLV1_CTRL
Address: 9 (09h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV1_EN
6
I2C_SLV1_BYTE_SW
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register as determined by I2C_SLV0_EN and
I2C_SLV0_LENG.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV1_REG[0] = 1, or if the last byte
read has a register address lsb = 0.
For example, if I2C_SLV0_EN = 0x1, and I2C_SLV0_LENG = 0x3 (to show swap has to
do with I2C slave address not EXT_SENS_DATA address), and if I2C_SLV1_REG = 0x1,
and I2C_SLV1_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_03 (slave
0’s data will be in EXT_SENS_DATA_00, EXT_SENS_DATA_01, and
EXT_SENS_DATA_02),
2) the second and third bytes will be read and swapped, so the data read from
address 0x2 will be stored at EXT_SENS_DATA_04, and the data read from address
0x3 will be stored at EXT_SENS_DATA_05,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_06.
5
I2C_SLV1_REG_DIS
4
I2C_SLV1_GRP
3:0
I2C_SLV1_LENG[3:0]
Document Number: DS-000189
Revision: 1.3
0 – No swapping occurs, bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or
write data.
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
Number of bytes to be read from I2C slave 1.
Page 71 of 89
ICM-20948
11.11 I2C_SLV1_DO
Name: I2C_SLV1_DO
Address: 10 (0Ah)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV1_DO[7:0]
FUNCTION
Data out when slave 1 is set to write.
11.12 I2C_SLV2_ADDR
Name: I2C_SLV2_ADDR
Address: 11 (0Bh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV2_RNW
6:0
I2C_ID_2[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 2.
11.13 I2C_SLV2_REG
Name: I2C_SLV2_REG
Address: 12 (0Ch)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV2_REG[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
I2C slave 2 register address from where to begin data transfer.
Page 72 of 89
ICM-20948
11.14 I2C_SLV2_CTRL
Name: I2C_SLV2_CTRL
Address: 13 (0Dh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV2_EN
6
I2C_SLV2_BYTE_SW
5
I2C_SLV2_REG_DIS
4
I2C_SLV2_GRP
3:0
I2C_SLV2_LENG[3:0]
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register as determined by I2C_SLV0_EN, I2C_SLV0_LENG,
I2C_SLV1_EN and I2C_SLV1_LENG.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV2_REG[0] = 1, or if the last byte
read has a register address lsb = 0.
See I2C_SLV1_CTRL for an example.
0 – No swapping occurs, bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or
write data.
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
Number of bytes to be read from I2C slave 2.
11.15 I2C_SLV2_DO
Name: I2C_SLV2_DO
Address: 14 (0Eh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV2_DO[7:0]
FUNCTION
Data out when slave 2 is set to write.
11.16 I2C_SLV3_ADDR
Name: I2C_SLV3_ADDR
Address: 15 (0Fh)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV3_RNW
6:0
I2C_ID_3[6:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 3.
Page 73 of 89
ICM-20948
11.17 I2C_SLV3_REG
Name: I2C_SLV3_REG
Address: 16 (10h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV3_REG[7:0]
FUNCTION
I2C slave 3 register address from where to begin data transfer.
11.18 I2C_SLV3_CTRL
Name: I2C_SLV3_CTRL
Address: 17 (11h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV3_EN
6
I2C_SLV3_BYTE_SW
5
I2C_SLV3_REG_DIS
4
I2C_SLV3_GRP
3:0
I2C_SLV3_LENG[3:0]
FUNCTION
1 – Enable reading data from this slave at the sample rate and storing data at the first
available EXT_SENS_DATA register as determined by I2C_SLV0_EN, I2C_SLV0_LENG,
I2C_SLV1_EN, I2C_SLV1_LENG, I2C_SLV2_EN and I2C_SLV2_LENG.
0 – Function is disabled for this slave.
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV3_REG[0] = 1, or if the last byte
read has a register address lsb = 0.
See I2C_SLV1_CTRL for an example.
0 – No swapping occurs, bytes are written in order read.
When set, the transaction does not write a register value, it will only read data, or
write data.
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc.
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
Number of bytes to be read from I2C slave 3.
11.19 I2C_SLV3_DO
Name: I2C_SLV3_DO
Address: 18 (12h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV3_DO[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Data out when slave 3 is set to write.
Page 74 of 89
ICM-20948
11.20 I2C_SLV4_ADDR
Name: I2C_SLV4_ADDR
Address: 19 (13h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV4_RNW
6:0
I2C_ID_4[6:0]
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 4.
NOTE: The I2C Slave 4 interface can be used to perform only single byte read and write transactions.
11.21 I2C_SLV4_REG
Name: I2C_SLV4_REG
Address: 20 (14h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV4_REG[7:0]
FUNCTION
I2C slave 4 register address from where to begin data transfer.
11.22 I2C_SLV4_CTRL
Name: I2C_SLV4_CTRL
Address: 21 (15h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7
I2C_SLV4_EN
6
I2C_SLV4_INT_EN
5
I2C_SLV4_REG_DIS
4:0
I2C_SLV4_DLY[4:0]
FUNCTION
1 – Enable data transfer with this slave at the sample rate. If read command, store
data in I2C_SLV4_DI register, if write command, write data stored in I2C_SLV4_DO
register. Bit is cleared when a single transfer is complete. Be sure to write
I2C_SLV4_DO first.
0 – Function is disabled for this slave.
1 – Enables the completion of the I2C slave 4 data transfer to cause an interrupt.
0 – Completion of the I2C slave 4 data transfer will not cause an interrupt.
When set, the transaction does not write a register value, it will only read data, or
write data.
When enabled via the I2C_MST_DELAY_CTRL, those slaves will only be enabled
every1/(1+I2C_SLV4_DLY) samples as determined by I2C_MST_ODR_CONFIG.
11.23 I2C_SLV4_DO
Name: I2C_SLV4_DO
Address: 22 (16h)
Type: USR3
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV4_DO[7:0]
Document Number: DS-000189
Revision: 1.3
FUNCTION
Data out when slave 4 is set to write.
Page 75 of 89
ICM-20948
11.24 I2C_SLV4_DI
Name: I2C_SLV4_DI
Address: 23 (17h)
Type: USR3
Bank: 3
Serial IF: R
Reset Value: 0x00
BIT
NAME
7:0
I2C_SLV4_DI[7:0]
FUNCTION
Data read from I2C Slave 4.
11.25 REG_BANK_SEL
Name: REG_BANK_SEL
Address: 127 (7Fh)
Type:
Bank: 3
Serial IF: R/W
Reset Value: 0x00
BIT
NAME
7:6
5:4
USER_BANK[1:0]
3:0
-
Document Number: DS-000189
Revision: 1.3
FUNCTION
Reserved.
Use the following values in this bit-field to select a USER BANK.
0: Select USER BANK 0.
1: Select USER BANK 1.
2: Select USER BANK 2.
3: Select USER BANK 3.
Reserved.
Page 76 of 89
ICM-20948
12 REGISTER MAP FOR MAGNETOMETER
The register map for the ICM-20948’s Magnetometer (AK09916) section is listed below.
NAME
WIA2
ST1
HXL
HXH
HYL
HYH
HZL
HZH
ST2
CNTL2
CNTL3
TS1
TS2
ADDRESS
01H
10H
11H
12H
13H
14H
15H
16H
18H
31H
32H
33H
34H
READ/WRITE
READ
READ
READ
READ
READ/ WRITE
READ/ WRITE
READ/ WRITE
READ/ WRITE
DESCRIPTION
BIT WIDTH
8
8
8
8
8
8
8
8
8
8
8
8
8
Device ID
Status 1
Measurement data
Status 2
Control 2
Control 3
Test
Test
EXPLANATION
Data status
X-axis data
Y-axis data
Z-axis data
Data status
Control Settings
Control Settings
DO NOT ACCESS
DO NOT ACCESS
Table 20. Register Table for Magnetometer
Addresses 00h to 18h, 30h to 32h are compliant with automatic increment function of serial interface respectively. In
other modes, read data is not correct. When the address is in 00h to 18h, the address is incremented 00h 01h
02h 03h 10h 11h ... 18h, and the address goes back to 00h after 18h. When the address is in
30h to 32h, the address goes back to 30h after 32h.
12.1 REGISTER MAP DESCRIPTION
ADDR
REGISTER NAME
D7
01H
10H
11H
12H
13H
14H
15H
16H
18H
WIA2
ST1
HXL
HXH
HYL
HYH
HZL
HZH
ST2
0
0
HX7
HX15
HY7
HY15
HZ7
HZ15
0
31H
32H
33H
34H
CNTL2
CNTL3
TS1
TS2
0
0
-
D6
D5
D4
READ-ONLY REGISTER
0
0
0
0
0
0
HX6
HX5
HX4
HX14
HX13
HX12
HY6
HY5
HY4
HY14
HY13
HY12
HZ6
HZ5
HZ4
HZ14
HZ13
HZ12
RSV30
RSV29
RSV28
WRITE/READ REGISTER
0
0
MODE4
0
0
0
-
D3
D2
D1
D0
1
0
HX3
HX11
HY3
HY11
HZ3
HZ11
HOFL
0
0
HX2
HX10
HY2
HY10
HZ2
HZ10
0
0
DOR
HX1
HX9
HY1
HY9
HZ1
HZ9
0
1
DRDY
HX0
HX8
HY0
HY8
HZ0
HZ8
0
MODE3
0
-
MODE2
0
-
MODE1
0
-
MODE0
SRST
-
Table 21. Register Map for Magnetometer
When VDD is turned ON, POR function works and all registers of AK09916 are initialized.
TS1 and TS2 are test registers for shipment test. Do not access these registers.
Document Number: DS-000189
Revision: 1.3
Page 77 of 89
ICM-20948
13 DETAILED DESCRIPTIONS FOR MAGNETOMETER REGISTERS
This section details each register within the ICM-20948 Magnetometer section.
13.1 WIA: DEVICE ID
ADDR
REGISTER NAME
D7
D6
01H
WIA
0
0
D5
D4
READ-ONLY REGISTER
0
0
D3
D2
D1
D0
1
0
0
1
D3
D2
D1
D0
0
0
0
0
DOR
0
DRDY
0
Device ID of AK09916. It is described in one byte and fixed value.
09H: fixed
13.2 ST1: STATUS 1
ADDR
REGISTER NAME
D7
ST1
0
0
10H
Reset
D6
D5
D4
READ-ONLY REGISTER
0
0
0
0
0
0
DRDY: Data Ready
“0”: Normal
“1”: Data is ready
DRDY bit turns to “1” when data is ready in Single measurement mode, Continuous measurement mode 1, 2, 3, 4 or
Self-test mode. It returns to “0” when any one of ST2 register or measurement data register (HXL to TMPS) is read.
DOR: Data Overrun
“0”: Normal
“1”: Data overrun
DOR bit turns to “1” when data has been skipped in Continuous measurement mode 1, 2, 3, 4. It returns to “0” when
any one of ST2 register or measurement data register (HXL to TMPS) is read.
13.3 HXL TO HZH: MEASUREMENT DATA
ADDR
REGISTER NAME
11H
12H
13H
14H
15H
16H
HXL
HXH
HYL
HYH
HZL
HZH
Reset
D7
HX7
HX15
HY7
HY15
HZ7
HZ15
0
D6
D5
Measurement data of magnetic sensor X-axis/Y-axis/Z-axis
HXL[7:0]: X-axis measurement data lower 8bit
HXH[15:8]: X-axis measurement data higher 8bit
HYL[7:0]: Y-axis measurement data lower 8bit
HYH[15:8]: Y-axis measurement data higher 8bit
Document Number: DS-000189
Revision: 1.3
D4
READ-ONLY REGISTER
HX6
HX5
HX4
HX14
HX13
HX12
HY6
HY5
HY4
HY14
HY13
HY12
HZ6
HZ5
HZ4
HZ14
HZ13
HZ12
0
0
0
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D3
D2
D1
D0
HX3
HX11
HY3
HY11
HZ3
HZ11
0
HX2
HX10
HY2
HY10
HZ2
HZ10
0
HX1
HX9
HY1
HY9
HZ1
HZ9
0
HX0
HX8
HY0
HY8
HZ0
HZ8
0
ICM-20948
HZL[7:0]: Z-axis measurement data lower 8bit
HZH[15:8]: Z-axis measurement data higher 8bit
Measurement data is stored in two’s complement and Little Endian format. Measurement range of each
from --32752 to 32752 in 16-bit output.
MEASUREMENT DATA (EACH AXIS) [15:0]
TWO’S COMPLEMENT
HEX
DECIMAL
MAGNETIC FLUX
DENSITY [µT]
0111 1111 1111 0000
7FF0
32752
4912(max.)
|
|
|
|
0000 0000 0000 0001
0001
1
0.15
0000 0000 0000 0000
0000
0
0
1111 1111 1111 1111
FFFF
-1
-0.15
|
|
|
|
1000 0000 0001 0000
8010
-32752
-4912(min.)
axis is
Table 22. Magnetometer Measurement Data Format
13.4 ST2: STATUS 2
ADDR
18H
REGISTER NAME
D7
ST2
0
0
Reset
D6
D5
D4
READ-ONLY REGISTER
RSV30
RSV29
RSV28
0
0
0
D3
D2
D1
D0
HOFL
0
0
0
0
0
0
0
ST2[6:4] bits: Reserved register for AKM.
HOFL: Magnetic sensor overflow
“0”: Normal
“1”: Magnetic sensor overflow occurred
In Single measurement mode, Continuous measurement mode 1, 2, 3, 4, and Self-test mode, magnetic sensor may
overflow even though measurement data register is not saturated. In this case, measurement data is not correct and
HOFL bit turns to “1”. When measurement data register is updated, HOFL bit is updated.
ST2 register has a role as data reading end register, also. When any of measurement data register (HXL to TMPS) is
read in Continuous measurement mode 1, 2, 3, 4, it means data reading start and taken as data reading until ST2
register is read. Therefore, when any of measurement data is read, be sure to read ST2 register at the end.
13.5 CNTL2: CONTROL 2
ADDR
31H
REGISTER NAME
CNTL2
Reset
D7
D6
0
0
0
0
D5
D4
D3
READ/WRITE REGISTER
0
MPDE4
MODE3
0
0
0
MODE[4:0] bits: Operation mode setting
“00000”: Power-down mode
“00001”: Single measurement mode
“00010”: Continuous measurement mode 1
“00100”: Continuous measurement mode 2
Document Number: DS-000189
Revision: 1.3
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D2
D1
D0
MODE2
0
MODE1
0
MODE0
0
ICM-20948
“00110”: Continuous measurement mode 3
“01000”: Continuous measurement mode 4
“10000”: Self-test mode
Other code settings are prohibited
When each mode is set, AK09916 transits to the set mode.
13.6 CNTL3: CONTROL 3
ADDR
32H
REGISTER NAME
CNTL3
Reset
D7
D6
0
0
0
0
D5
D4
READ/WRITE REGISTER
0
0
0
0
D3
D2
D1
D0
0
0
0
0
0
0
SRST
0
SRST: Soft reset
"0":
Normal
"1":
Reset
When “1” is set, all registers are initialized. After reset, SRST bit turns to “0” automatically.
13.7 TS1, TS2: TEST 1, 2
ADDR
REGISTER NAME
D7
33H
34H
TS1
TS2
0
Reset
D6
D5
D4
READ/WRITE REGISTER
0
0
0
D3
D2
D1
D0
0
0
0
0
TS1 and TS2 registers are test registers for shipment test. Do not use these registers.
Document Number: DS-000189
Revision: 1.3
Page 80 of 89
ICM-20948
14 USE NOTES
14.1 GYROSCOPE MODE TRANSITION
When gyroscope is transitioning from low-power to low-noise mode, several unsettled output samples will be
observed at the gyroscope output due to filter switching and settling. The number of unsettled gyroscope output
samples depends on the filter and ODR settings.
14.2 POWER MANAGEMENT 1 REGISTER SETTING
CLKSEL[2:0] has to be set to 001 to achieve the datasheet performance.
14.3 DMP MEMORY ACCESS
Reading/writing DMP memory and FIFO through I2C in a multithreaded environment can cause wrong data being read.
To avoid the issue, one may use SPI instead of I2C, or use I2C with mutexes.
14.4 TIME BASE CORRECTION
The system clock frequency at room temperature in gyroscope mode and 6-Axis mode varies from part to part, and
the clock rates specified in datasheet are the nominal values. The percentage of frequency deviation from the nominal
values for each part is logged in register TIMEBASE_CORRECTION_PLL, and the range of the code is ±10% with each
LSB representing a step of 0.079%. For example, if on one part TIMEBASE_CORRECTION_PLL = 0x0C = d’12, it means
the clock frequency in gyroscope mode and 6-Axis mode is ~0.94% faster than the nominal value.
When operating in accelerometer-only mode, the system clock frequency at room temperature is the nominal
frequency over parts, and it is independent of the value stored in TIMEBASE_CORRECTION_PLL register.
14.5 I2C MASTER CLOCK FREQUENCY
I2C master clock frequency can be set by register I2C_MST_CLK as shown in Table 23. Due to temperature variation
and part to part variation of system clock frequency in different power modes, I2C_MST_CLK should be set such that
in all conditions the clock frequency will not exceed what a slave device can support. To achieve a targeted clock
frequency of 400 kHz, MAX, it is recommended to set I2C_MST_CLK = 7 (345.6 kHz / 46.67% duty cycle).
Document Number: DS-000189
Revision: 1.3
I2C_MST_CLK
NOMINAL CLK
FREQUENCY [KHZ]
DUTY CYCLE
0
370.29
50.00%
1
-
-
2
370.29
50.00%
3
432.00
50.00%
4
370.29
42.86%
5
370.29
50.00%
6
345.60
40.00%
7
345.60
46.67%
8
304.94
47.06%
9
432.00
50.00%
10
432.00
41.67%
11
432.00
41.67%
12
471.27
45.45%
13
432.00
50.00%
Page 81 of 89
ICM-20948
I2C_MST_CLK
NOMINAL CLK
FREQUENCY [KHZ]
DUTY CYCLE
14
345.60
46.67%
15
345.60
46.67%
Table 23. I2C Master Clock Frequency
14.6 CLOCKING
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope
oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for
optimum sensor performance and power consumption will be automatically selected based on the power mode.
Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the
PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted
that the internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation
oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency
varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register
TIMEBASE_CORRECTION_PLL, and users can factor it in during distance and angle calculations to not sacrifice
accuracy. Other than that, PLL has better frequency stability and lower frequency variation over temperature than the
internal relaxation oscillator.
14.7 LP_EN BIT-FIELD USAGE
The LP_EN bit-field (User Bank 0, PWR_MGMT_1 register, bit [5] helps to reduce the digital current. The
recommended setting for this bit-field is 1 to achieve the lowest possible current. However, when LP_EN is set to 1,
user may not be able to write to the following registers. If it is desired to write to registers in this list, it is
recommended to first set LP_EN=0, write the desired register(s), then set LP_EN=1 again:
•
•
•
•
USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE,
FIFO_COUNTH, FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
USER BANK 1: All registers except REG_BANK_SEL
USER BANK 2: All registers except REG_BANK_SEL
USER BANK 3: All registers except REG_BANK_SEL
14.8 REGISTER ACCESS USING SPI INTERFACE
Using the SPI interface, when the AP/user disables the gyroscope sensor (User Bank 0, PWR_MGMT_2 register, bits
[2:0]=111) as part of a sequence of register read or write commands, the AP/user will be required to subsequently
wait 22 µs prior to any of the following operations:
(1) Writing to any of the following registers:
•
•
•
•
USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE,
FIFO_COUNTH, FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
USER BANK 1: All registers except REG_BANK_SEL
USER BANK 2: All registers except REG_BANK_SEL
USER BANK 3: All registers except REG_BANK_SEL
(2) Reading data from FIFO
(3) Reading from memory
Document Number: DS-000189
Revision: 1.3
Page 82 of 89
ICM-20948
15 ORIENTATION OF AXES
Figure 12 and Figure 13 show the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figures.
+Z
+Y
+Z
ICM
+Y
-20
94
8
+X
+X
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation
ICM
-20
94
8
+X
+Y
+Z
Figure 13. Orientation of Axes of Sensitivity for Magnetometer
Document Number: DS-000189
Revision: 1.3
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ICM-20948
16 PACKAGE DIMENSIONS
This section provides package dimensions for the device. Information for the 24 Lead QFN 3.0x3.0x0.9 package is in
Figure 14 and Table 24
Figure 14. Package Dimensions
Document Number: DS-000189
Revision: 1.3
Page 84 of 89
ICM-20948
SYMBOLS
A
A1
b
c
D
D2
E
E2
e
K
L
R
s
y
DIMENSIONS IN MILLIMETERS
NOM.
1.00
0.02
0.20
0.15 REF.
3.00
1.70
3.00
1.54
0.40
0.35 REF.
0.30
REF.
0.25 REF.
---
MIN.
0.95
0.00
0.15
--2.90
1.65
2.90
1.49
----0.25
0.075
--0.00
Table 24. Package Dimensions
Document Number: DS-000189
Revision: 1.3
Page 85 of 89
MAX.
1.05
0.05
0.25
--3.10
1.75
3.10
1.59
----0.35
----0.075
ICM-20948
17 PART NUMBER PART MARKINGS
The part number part markings for ICM-20948 devices are summarized below:
PART NUMBER
ICM-20948
PART NUMBER PART MARKING
I2948
Table 25. Part Number Part Markings
TOP VIEW
Part Number
Lot Traceability Code
I2948
XXXXXX
YYWW
Y Y = Year Code
W W = Work Week
Figure 15. Part Number Part Markings
Document Number: DS-000189
Revision: 1.3
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ICM-20948
18 REFERENCES
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
•
•
Manufacturing Recommendations
o Assembly Guidelines and Recommendations
o PCB Design Guidelines and Recommendations
o MEMS Handling Instructions
o ESD Considerations
o Reflow Specification
o Storage Specifications
o Package Marking Specification
o Tape & Reel Specification
o Reel & Pizza Box Label
o Packaging
o Representative Shipping Carton Label
Compliance
o Environmental Compliance
o DRC Compliance
o Compliance Declaration Disclaimer
Document Number: DS-000189
Revision: 1.3
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ICM-20948
19 DOCUMENT INFORMATION
19.1 REVISION HISTORY
REVISION DATE
REVISION
DESCRIPTION
12/07/2016
1.0
Initial Release
1/17/2017
1.1
Formatting fix
04/06/2017
1.2
Updated Section 4
06/02/2017
1.3
Updated Sections 3, 4
Document Number: DS-000189
Revision: 1.3
Page 88 of 89
ICM-20948
COMPLIANCE DECLARATION DISCLAIMER
InvenSense believes the environmental and other compliance information given in this document to be correct but
cannot guarantee accuracy or completeness. Conformity documents substantiating the specifications and component
characteristics are on file. InvenSense subcontracts manufacturing and the information contained herein is based on
data received from vendors and suppliers, which has not been validated by InvenSense.
This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by
InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to
change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its
design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding the information and
specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising from information contained in this
document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement
of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or
otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks
that are registered trademarks are the property of their respective companies. InvenSense sensors should not be used or sold in the development,
storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well
as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power
plant equipment, disaster prevention and crime prevention equipment.
©2016—2017 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP,
AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names
may be trademarks of the respective companies with which they are associated.
©2016—2017 InvenSense. All rights reserved.
Document Number: DS-000189
Revision: 1.3
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