ICM-42670-P

ICM-42670-P Datasheet High Performance 6-Axis MotionTrackingTM IMU ICM-42670-P HIGHLIGHTS ICM-42670-P FEATURES The ICM-42670-P is a high performance 6-axis MEMS MotionTracking device that combines a 3-axis gyroscope and a 3-axis accelerometer. It has a configurable host interface that supports I3CSM, I2C, and SPI serial communication, features up to 2.25 Kbytes FIFO and 2 programmable interrupts with ultra-lowpower wake-on-motion support to minimize system power consumption. The ICM-42670-P supports the lowest gyro and accel sensor noise in this IMU class, and has the highest stability against temperature, shock (up to 20,000g) or SMT/bend induced offset as well as immunity against out-of-band vibration induced noise. Other industry-leading features include on-chip APEX Motion Processing engine for gesture recognition, and pedometer, along with programmable digital filters, and an embedded temperature sensor. The device supports a VDD operating range of 1.71V to 3.6V, and a separate VDDIO operating range from 1.71V to 3.6V. • • • • • • • • APPLICATIONS • • • • • • • • BLOCK DIAGRAM Low-Noise mode 6-axis current consumption of 0.55 mA Low-Power mode support for always-on experience Sleep Mode Current Consumption: 3.5µA User selectable Gyro Full-scale range (dps): ± 250/500/1000/2000 User selectable Accelerometer Full-scale range (g): ± 2/4/8/16 User-programmable digital filters for gyro, accel, and temp sensor APEX Motion Functions: Pedometer, Tilt Detection, Low-g Detection, Freefall Detection, Wake on Motion, Significant Motion Detection Host interface: 12.5 MHz I3CSM, 1 MHz I2C, 24 MHz SPI Wearables (Fitness Bands, SmartWatches, Healthcare wearables) Hearables (True Wireless Headsets) Gaming Controllers Smart Home Appliances Smart TV remotes Drones Robotics Augmented Reality/Virtual Reality ORDERING INFORMATION PART TEMP RANGE ICM-42670-P† −40°C to +85°C PACKAGE 2.5x3mm 14-Pin LGA †Denotes RoHS and Green-Compliant Package InvenSense Inc. reserves the right to change specifications and information herein without notice unless the product is in mass production and the datasheet has been designated by InvenSense in writing as subject to a specified Product / Process Change Notification Method regulation. InvenSense, a TDK Group Company 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 invensense.tdk.com Document Number: DS-000451 Revision: 1.0 Rev. Date: 04/15/2021 ICM-42670-P TABLE OF CONTENTS ICM-42670-P Highlights ...................................................................................................................................... 1 Block Diagram ..................................................................................................................................................... 1 ICM-42670-P Features ........................................................................................................................................ 1 Applications ........................................................................................................................................................ 1 Ordering Information ......................................................................................................................................... 1 Introduction ........................................................................................................................................................ 8 Purpose and Scope .................................................................................................................................. 8 Product Overview .................................................................................................................................... 8 Applications ............................................................................................................................................. 8 Features .............................................................................................................................................................. 9 Gyroscope Features ................................................................................................................................. 9 Accelerometer Features .......................................................................................................................... 9 Motion Features ...................................................................................................................................... 9 Additional Features .................................................................................................................................. 9 Electrical Characteristics ................................................................................................................................... 10 Gyroscope Specifications ....................................................................................................................... 10 Accelerometer Specifications ................................................................................................................ 11 Electrical Specifications ......................................................................................................................... 12 I2C Timing Characterization ................................................................................................................... 14 SPI Timing Characterization – 4-Wire SPI Mode .................................................................................... 15 SPI Timing Characterization – 3-Wire SPI Mode .................................................................................... 16 Absolute Maximum Ratings ................................................................................................................... 17 Applications Information .................................................................................................................................. 18 Pin Out Diagram and Signal Description ................................................................................................ 18 Typical Operating Circuit........................................................................................................................ 19 Bill of Materials for External Components ............................................................................................. 20 System Block Diagram ........................................................................................................................... 20 Overview ................................................................................................................................................ 20 Three-Axis MEMS Gyroscope................................................................................................................. 20 Three-Axis MEMS Accelerometer .......................................................................................................... 20 I3CSM, I2C and SPI Host Interface ............................................................................................................ 21 Self-Test ................................................................................................................................................. 21 Sensor Data Registers ........................................................................................................................ 21 Interrupts........................................................................................................................................... 21 Digital-Output Temperature Sensor .................................................................................................. 21 Bias and LDOs .................................................................................................................................... 21 Charge Pump ..................................................................................................................................... 21 Standard Power Modes ..................................................................................................................... 22 Signal Path ........................................................................................................................................................ 23 Page 2 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO................................................................................................................................................................... 24 Packet Structure .................................................................................................................................... 24 FIFO Header ........................................................................................................................................... 26 Maximum FIFO Storage ......................................................................................................................... 27 Programmable Interrupts ................................................................................................................................. 28 APEX Motion Functions .................................................................................................................................... 29 Digital Interface ................................................................................................................................................ 30 I3CSM, I2C and SPI Serial Interfaces ......................................................................................................... 30 I3CSM Interface ....................................................................................................................................... 30 I2C Interface ........................................................................................................................................... 32 I2C Communications Protocol ................................................................................................................ 32 I2C Terms ................................................................................................................................................ 34 SPI Interface ........................................................................................................................................... 35 Assembly........................................................................................................................................................... 36 Orientation of Axes ........................................................................................................................... 36 Package Dimensions .......................................................................................................................... 37 Part Number Package Marking ......................................................................................................................... 38 Use Notes ......................................................................................................................................................... 39 Gyroscope Power On to Power Off Transition .................................................................................. 39 Accessing MREG1, MREG2 And MREG3 Registers ............................................................................................ 40 Register Map .................................................................................................................................................... 41 User Bank 0 Register Map ................................................................................................................. 41 User Bank MREG1 Register Map ....................................................................................................... 42 User Bank MREG2 Register Map ....................................................................................................... 43 User Bank MREG3 Register Map ....................................................................................................... 43 User Bank 0 Register Map – Descriptions......................................................................................................... 45 MCLK_RDY ......................................................................................................................................... 45 DEVICE_CONFIG ................................................................................................................................ 45 SIGNAL_PATH_RESET ........................................................................................................................ 46 DRIVE_CONFIG1 ................................................................................................................................ 47 DRIVE_CONFIG2 ................................................................................................................................ 48 DRIVE_CONFIG3 ................................................................................................................................ 49 INT_CONFIG ....................................................................................................................................... 50 TEMP_DATA1 .................................................................................................................................... 50 TEMP_DATA0 .................................................................................................................................... 51 ACCEL_DATA_X1 ................................................................................................................................ 51 ACCEL_DATA_X0 ................................................................................................................................ 51 ACCEL_DATA_Y1 ................................................................................................................................ 51 ACCEL_DATA_Y0 ................................................................................................................................ 52 ACCEL_DATA_Z1 ................................................................................................................................ 52 Page 3 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ACCEL_DATA_Z0 ................................................................................................................................ 52 GYRO_DATA_X1................................................................................................................................. 52 GYRO_DATA_X0................................................................................................................................. 52 GYRO_DATA_Y1 ................................................................................................................................. 53 GYRO_DATA_Y0 ................................................................................................................................. 53 GYRO_DATA_Z1 ................................................................................................................................. 53 GYRO_DATA_Z0 ................................................................................................................................. 53 TMST_FSYNCH ................................................................................................................................... 53 TMST_FSYNCL .................................................................................................................................... 54 APEX_DATA4 ..................................................................................................................................... 54 APEX_DATA5 ..................................................................................................................................... 54 PWR_MGMT0 .................................................................................................................................... 55 GYRO_CONFIG0 ................................................................................................................................. 56 ACCEL_CONFIG0 ................................................................................................................................ 57 TEMP_CONFIG0 ................................................................................................................................. 58 GYRO_CONFIG1 ................................................................................................................................. 58 ACCEL_CONFIG1 ................................................................................................................................ 59 APEX_CONFIG0 .................................................................................................................................. 59 APEX_CONFIG1 .................................................................................................................................. 60 WOM_CONFIG ................................................................................................................................... 61 FIFO_CONFIG1 ................................................................................................................................... 61 FIFO_CONFIG2 ................................................................................................................................... 62 FIFO_CONFIG3 ................................................................................................................................... 62 INT_SOURCE0 .................................................................................................................................... 63 INT_SOURCE1 .................................................................................................................................... 63 INT_SOURCE3 .................................................................................................................................... 64 INT_SOURCE4 .................................................................................................................................... 64 FIFO_LOST_PKT0 ............................................................................................................................... 65 FIFO_LOST_PKT1 ............................................................................................................................... 65 APEX_DATA0 ..................................................................................................................................... 65 APEX_DATA1 ..................................................................................................................................... 65 APEX_DATA2 ..................................................................................................................................... 65 APEX_DATA3 ..................................................................................................................................... 66 INTF_CONFIG0 ................................................................................................................................... 66 INTF_CONFIG1 ................................................................................................................................... 67 INT_STATUS_DRDY ............................................................................................................................ 67 INT_STATUS ....................................................................................................................................... 68 INT_STATUS2 ..................................................................................................................................... 68 INT_STATUS3 ..................................................................................................................................... 68 FIFO_COUNTH ................................................................................................................................... 69 Page 4 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO_COUNTL .................................................................................................................................... 69 FIFO_DATA......................................................................................................................................... 69 WHO_AM_I ....................................................................................................................................... 69 BLK_SEL_W ........................................................................................................................................ 70 MADDR_W......................................................................................................................................... 70 M_W .................................................................................................................................................. 70 BLK_SEL_R ......................................................................................................................................... 70 MADDR_R .......................................................................................................................................... 71 M_R ................................................................................................................................................... 71 User Bank MREG1 Register Map – Descriptions............................................................................................... 72 TMST_CONFIG1 ................................................................................................................................. 72 FIFO_CONFIG5 ................................................................................................................................... 73 FIFO_CONFIG6 ................................................................................................................................... 74 FSYNC_CONFIG .................................................................................................................................. 75 INT_CONFIG0 ..................................................................................................................................... 75 INT_CONFIG1 ..................................................................................................................................... 76 SENSOR_CONFIG3 ............................................................................................................................. 76 ST_CONFIG ........................................................................................................................................ 77 SELFTEST ............................................................................................................................................ 78 INTF_CONFIG6 ................................................................................................................................... 78 INTF_CONFIG10 ................................................................................................................................. 78 INTF_CONFIG7 ................................................................................................................................... 79 OTP_CONFIG...................................................................................................................................... 79 INT_SOURCE6 .................................................................................................................................... 80 INT_SOURCE7 .................................................................................................................................... 80 INT_SOURCE8 .................................................................................................................................... 81 INT_SOURCE9 .................................................................................................................................... 81 INT_SOURCE10 .................................................................................................................................. 82 APEX_CONFIG2 .................................................................................................................................. 83 APEX_CONFIG3 .................................................................................................................................. 84 APEX_CONFIG4 .................................................................................................................................. 85 APEX_CONFIG5 .................................................................................................................................. 86 APEX_CONFIG9 .................................................................................................................................. 87 APEX_CONFIG10 ................................................................................................................................ 88 APEX_CONFIG11 ................................................................................................................................ 89 ACCEL_WOM_X_THR......................................................................................................................... 90 ACCEL_WOM_Y_THR ......................................................................................................................... 90 ACCEL_WOM_Z_THR ......................................................................................................................... 90 OFFSET_USER0 .................................................................................................................................. 90 OFFSET_USER1 .................................................................................................................................. 91 Page 5 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P OFFSET_USER2 .................................................................................................................................. 91 OFFSET_USER3 .................................................................................................................................. 91 OFFSET_USER4 .................................................................................................................................. 91 OFFSET_USER5 .................................................................................................................................. 92 OFFSET_USER6 .................................................................................................................................. 92 OFFSET_USER7 .................................................................................................................................. 92 OFFSET_USER8 .................................................................................................................................. 92 ST_STATUS1 ....................................................................................................................................... 93 ST_STATUS2 ....................................................................................................................................... 93 FDR_CONFIG ...................................................................................................................................... 94 APEX_CONFIG12 ................................................................................................................................ 95 User Bank MREG2 Register Map – Descriptions............................................................................................... 96 OTP_CTRL7 ........................................................................................................................................ 96 User Bank MREG3 Register Map – Descriptions............................................................................................... 97 XA_ST_DATA ...................................................................................................................................... 97 YA_ST_DATA ...................................................................................................................................... 97 ZA_ST_DATA ...................................................................................................................................... 97 XG_ST_DATA...................................................................................................................................... 97 YG_ST_DATA ...................................................................................................................................... 97 ZG_ST_DATA ...................................................................................................................................... 98 SmartMotion Product Family ........................................................................................................................... 99 Reference ....................................................................................................................................................... 100 Revision History .............................................................................................................................................. 101 Page 6 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P TABLE OF FIGURES Figure 1. I2C Bus Timing Diagram .................................................................................................................................14 Figure 2. 4-Wire SPI Bus Timing Diagram ....................................................................................................................15 Figure 3. 3-Wire SPI Bus Timing Diagram ....................................................................................................................16 Figure 4. Pin Out Diagram for ICM-42670-P 2.5x3.0x0.76 mm LGA ............................................................................18 Figure 5. ICM-42670-P Application Schematic (I3CSM / I2C Interface to Host) .............................................................19 Figure 6. ICM-42670-P Application Schematic (SPI Interface to Host) ........................................................................19 Figure 7. ICM-42670-P System Block Diagram.............................................................................................................20 Figure 8. ICM-42670-P Signal Path ..............................................................................................................................23 Figure 9. FIFO Packet Structure ...................................................................................................................................24 Figure 10. Maximum FIFO Storage ..............................................................................................................................27 Figure 11. START and STOP Conditions .......................................................................................................................32 Figure 12. Acknowledge on the I2C Bus .......................................................................................................................33 Figure 13. Complete I2C Data Transfer ........................................................................................................................33 Figure 14. Typical SPI Master/Slave Configuration ......................................................................................................35 Figure 15. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................36 TABLE OF TABLES Table 1. Gyroscope Specifications ...............................................................................................................................10 Table 2. Accelerometer Specifications ........................................................................................................................11 Table 3. D.C. Electrical Characteristics .........................................................................................................................12 Table 4. A.C. Electrical Characteristics .........................................................................................................................13 Table 5. I2C Timing Characteristics...............................................................................................................................14 Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) .................................................................................15 Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) .................................................................................16 Table 8. Absolute Maximum Ratings ...........................................................................................................................17 Table 9. Signal Descriptions .........................................................................................................................................18 Table 10. Bill of Materials ............................................................................................................................................20 Table 11. Standard Power Modes for ICM-42670-P ....................................................................................................22 Table 12. I3CSM CCC Commands...................................................................................................................................32 Table 13. I2C Terms ......................................................................................................................................................34 Page 7 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INTRODUCTION PURPOSE AND SCOPE This document is a product specification, providing a description, specifications, and design related information on the ICM-42670-P Single-Interface MotionTracking device. The device is housed in a small 2.5x3x0.76 mm 14-pin LGA package. PRODUCT OVERVIEW The ICM-42670-P is a 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis accelerometer in a small 2.5x3x0.76 mm (14-pin LGA) package. It also features up to 2.25 Kbytes FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. ICM-42670-P, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for consumers. The gyroscope supports four programmable full-scale range settings from ±250 dps to ±2000 dps and the accelerometer supports four programmable full-scale range settings from ±2g to ±16g. Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I3CSM, I2C, and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.71V to 3.6V. The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I2C interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz. The device provides high robustness by supporting 20,000g shock reliability. APPLICATIONS • • • • • • • • Wearables (Fitness Bands, SmartWatches, Healthcare wearables) Hearables (True Wireless Headsets) Gaming Controllers Smart Home Appliances Smart TV remotes Drones Robotics Augmented Reality/Virtual Reality Page 8 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FEATURES GYROSCOPE FEATURES The triple-axis MEMS gyroscope in the ICM-42670-P includes a wide range of features: • • • • • Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±250, ±500, ±1000, and ±2000 degrees/sec Low Noise (LN) power mode support Digitally programmable low-pass filters Factory calibrated sensitivity scale factor Self-test ACCELEROMETER FEATURES The triple-axis MEMS accelerometer in ICM-42670-P includes a wide range of features: • • • • • Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2g, ±4g, ±8g and ±16g Low Noise (LN) and Low Power (LP) power modes support User-programmable interrupts Wake-on-motion interrupt for low power operation of applications processor Self-test MOTION FEATURES ICM-42670-P includes the following motion features, also known as APEX (Advanced Pedometer and Event Detection – neXt gen) • • • • • • Pedometer: Tracks step count and issues a step detect Interrupt. Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 degrees for more than a programmable time. Low-g Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a programmable threshold and stays below the threshold for a programmable time. Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration. Wake on Motion (WoM): Detects motion when accelerometer samples exceed a programmable threshold. This motion event can be used to enable device operation from sleep mode. Significant Motion Detector (SMD): Detects significant motion based on accelerometer data. ADDITIONAL FEATURES ICM-42670-P includes the following additional features: • • • • • • • • Up to 2.25 Kbytes FIFO buffer enables the applications processor to read the data in bursts User-programmable digital filters for gyroscope, accelerometer, and temperature sensor 12.5M Hz I3CSM (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode) / 1 MHz I2C / 24 MHz SPI slave host interface Digital-output temperature sensor Smallest and thinnest LGA package for portable devices: 2.5x3x0.76 mm (14-pin LGA) 20,000g shock tolerant MEMS structure hermetically sealed and bonded at wafer level RoHS and Green compliant Page 9 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ELECTRICAL CHARACTERISTICS GYROSCOPE SPECIFICATIONS Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN GYROSCOPE SENSITIVITY GYRO_UI_FS_SEL=0 GYRO_UI_FS_SEL=1 Full-Scale Range GYRO_UI_FS_SEL=2 GYRO_UI_FS_SEL=3 Gyroscope ADC Word Length Sensitivity Scale Factor Output in two’s complement format GYRO_UI_FS_SEL=0 GYRO_UI_FS_SEL=1 GYRO_UI_FS_SEL=2 GYRO_UI_FS_SEL=3 Sensitivity Scale Factor Initial Tolerance Sensitivity Scale Factor Variation Over Temperature Nonlinearity Cross-Axis Sensitivity 25°C Initial ZRO Tolerance 25°C ZRO Variation vs. Temperature -40°C to +85°C; Board-Level OTHER PARAMETERS @ 10 Hz -40°C to +85°C; Board-Level Best fit straight line; 25°C; Board-Level Board-level TYP MAX UNITS NOTES ±2000 º/s ±1000 ±500 ±250 º/s º/s º/s 2 2 16 16.4 bits LSB/(º/s) 32.8 65.5 131 LSB/(º/s) LSB/(º/s) LSB/(º/s) ±1 % 1, 7 ±0.007 %/ºC 3, 6 ±0.1 ±2 % % 3, 6 3, 6 ±1 º/s 1, 7 ±0.015 º/s/ºC 3, 6 0.007 º/s /√Hz 1 º/s-rms kHz Hz ms Hz 4 1 2 3 2 2 2 2, 5 2 2 2 2 ZERO-RATE OUTPUT (ZRO) Rate Noise Spectral Density Total RMS Noise Gyroscope Mechanical Frequencies Low Pass Filter Response Gyroscope Start-Up Time Output Data Rate Bandwidth = 100 Hz 25 16 Time from gyro enable to gyro drive ready 0.07 28 30 180 30 12.5 1600 Table 1. Gyroscope Specifications Notes: 1. 2. 3. 4. 5. 6. 7. Tested in production at component-level. Guaranteed by design. Derived from validation or characterization of parts, not tested in production. Calculated from Rate Noise Spectral Density. 20-bits data format supported in FIFO, see section 6.1. Board-level spec values depend on specific board design. For design information of boards used for device characterization, that forms the basis of the spec values reported here, please contact your local TDK InvenSense FAE. Value after factory test and trim. Page 10 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ACCELEROMETER SPECIFICATIONS Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS UNITS NOTES ±16 g ±8 ±4 g g 2 2 ACCEL_UI_FS_SEL=3 Output in two’s complement format ACCEL_UI_FS_SEL=0 ±2 16 2,048 g bits LSB/g ACCEL_UI_FS_SEL=1 ACCEL_UI_FS_SEL=2 ACCEL_UI_FS_SEL=3 4,096 8,192 16,384 LSB/g LSB/g LSB/g ±1 % 1, 7 ACCELEROMETER SENSITIVITY ACCEL_UI_FS_SEL=0 Full-Scale Range ACCEL_UI_FS_SEL=1 ACCEL_UI_FS_SEL=2 ADC Word Length Sensitivity Scale Factor Sensitivity Scale Factor Initial Tolerance Sensitivity Change vs. Temperature MIN 25°C -40°C to +85°C; Board-Level TYP MAX 2 2 2, 5 2 2 2 2 Nonlinearity Cross-Axis Sensitivity Best Fit Straight Line, ±2g; Board-Level Board-level ±0.01 ±0.1 ±1 %/ºC % % 3, 6 3, 6 3, 6 Initial Tolerance Zero-G Level Change vs. Temperature ZERO-G OUTPUT 25°C -40°C to +85°C; Board-Level ±25 ±0.15 mg mg/ºC 1, 7 3, 6 OTHER PARAMETERS Power Spectral Density @ 10 Hz 100 µg/√Hz 1 RMS Noise Low Pass Filter Response Accelerometer Startup Time Output Data Rate Bandwidth = 100 Hz 1.0 mg-rms Hz ms Hz 4 2 3 2 16 From sleep mode to valid data 180 10 1.5625 1600 Table 2. Accelerometer Specifications Notes: 1. 2. 3. 4. 5. 6. 7. Tested in production at component-level. Guaranteed by design. Derived from validation or characterization of parts, not tested in production. Calculated from Power Spectral Density. 20-bits data format supported in FIFO, see section 6.1. Board-level spec values depend on specific board design. For design information of boards used for device characterization, that forms the basis of the spec values reported here, please contact your local TDK InvenSense FAE. Value after factory test and trim. Page 11 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ELECTRICAL SPECIFICATIONS D.C. Electrical Characteristics 3.3.1 Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES 1.71 1.71 1.8 1.8 3.6 3.6 V V 1 1 SUPPLY VOLTAGES VDD VDDIO SUPPLY CURRENTS 6-Axis Gyroscope + Accelerometer 0.55 mA 2 3-Axis Accelerometer 0.20 mA 2 3-Axis Gyroscope 0.42 mA 2 Full-Chip Sleep Mode At 25ºC 3.5 µA 2 Specified Temperature Range TEMPERATURE RANGE Performance parameters are not applicable beyond Specified Temperature Range °C 1 Low-Noise Mode -40 Table 3. D.C. Electrical Characteristics Notes: 1. 2. Guaranteed by design. Derived from validation or characterization of parts, not tested in production. Page 12 of 102 Document Number: DS-000451 Revision: 1.0 +85 ICM-42670-P 3.3.2 A.C. Electrical Characteristics Typical Operating Conditions, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES SUPPLIES Supply Ramp Time Valid power-on RESET 0.1 Power Supply Noise 3 ms 1 mV peak-peak 1 °C LSB bits Hz °C 1 3 2 2, 4 3 0.64 sec 2 129 2.01 LSB/°C LSB/°C 1 1 1 ms 1 10 TEMPERATURE SENSOR Operating Range 25°C Output ADC Resolution ODR Room Temperature Offset Stabilization Time (fixed number of clock cycles) Sensitivity Sensitivity for FIFO data Ambient Start-up time for register read/write From power-up -40 Output in two’s complement format 85 0 16 With Filter 25°C 1.5625 -3 Trimmed Trimmed 125 1.95 1600 3 126.9 1.983 POWER-ON RESET I2C ADDRESS AP_AD0 = 0 AP_AD0 = 1 I2C ADDRESS 1101000 1101001 DIGITAL INPUTS (FSYNC, SCLK, SDI, CS) 0.7*VDDIO VIH, High Level Input Voltage V VIL, Low Level Input Voltage 0.3*VDDIO CI, Input Capacitance 20ms should be allowed to elapse before it is powered back on. Page 39 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ACCESSING MREG1, MREG2 AND MREG3 REGISTERS The following procedure must be used to access registers in user banks MREG1, MREG2, and MREG3. MREG1, MREG2, and MREG3 registers are accessed indirectly, using the following registers in Bank 0 (_W registers for Write, _R registers for Read) • • • • • • BLK_SEL_W MADDR_W M_W BLK_SEL_R MADDR_R M_R For MREG1 write access, BLK_SEL_W must be set to 0x00. For MREG2 write access, BLK_SEL_W must be set to 0x28. For MREG3 write access, BLK_SEL_W must be set to 0x50. For MREG1 read access, BLK_SEL_R must be set to 0x00. For MREG2 read access, BLK_SEL_R must be set to 0x28. For MREG3 read access, BLK_SEL_R must be set to 0x50. User must ensure BLK_SEL_W and BLK_SEL_R are set to 0x00 after completing MREG1, MREG2, or MREG3 access. Example: To write a value to an MREG1 register at address 0x14 use the following steps: • • • • BLK_SEL_W must be set to 0 MADDR_W must be set to 0x14 (address of the MREG1 register being accessed) M_W must be set to the desired value Wait for 10 µs Example: To read the value of an MREG1 register at address 0x14 use the following steps: • • • • • BLK_SEL_R must be set to 0 MADDR_R must be set to 0x14 (address of the MREG1 register being accessed) Wait for 10µs Read register M_R to access the value in MREG1 register 0x14 Wait for 10 µs Host must not access any other register for 10 µs once MREG1, MREG2 or MREG3 access is kicked off. Additionally, please note the following for MREG1, MREG2 or MREG3 register accesses: • • • • • User must check that register field MCLK_RDY is at value 1, to confirm that internal clock is running before initiating MREG register access. MREG1, MREG2, or MREG3 read and write operations cannot happen in all power modes. Sleep mode, and Accelerometer low power mode with WUOSC do not support MREG1, MREG2 or MREG3 access. When in sleep mode or accelerometer LP mode with WUOSC, MREG1, MREG2 or MREG3 read/write operations require the user to power on the RC oscillator using register field IDLE from register PWR_MGMT0. It can take up to 10 µs for MREG1, MREG2 or MREG3 read/write operations to be effective. No register access must be performed during this period Multiple serial protocol transactions are needed for a single data byte transfer, please refer to the examples provided. Data transfers through indirect access are only supported for single byte transfers and burst data transfer is not supported for read or write operations. Page 40 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P REGISTER MAP This section lists the register map for the ICM-42670-P, for user banks 0, MREG1, MREG2 and MREG3. USER BANK 0 REGISTER MAP ADDR (HEX) ADDR (DEC) REGISTER NAME SERIAL I/F 00 00 MCLK_RDY R BIT7 BIT6 BIT5 BIT4 BIT3 - BIT2 BIT1 MCLK_RDY SPI_AP_4WIR E 01 01 DEVICE_CONFIG R/W 02 02 SIGNAL_PATH_RESET R/W 03 03 DRIVE_CONFIG1 R/W - I3C_DDR_SLEW_RATE I3C_SDR_SLEW_RATE 04 04 DRIVE_CONFIG2 R/W - I2C_SLEW_RATE ALL_SLEW_RATE 05 05 DRIVE_CONFIG3 R/W 06 06 INT_CONFIG R/W - BIT0 SOFT_RESET_ DEVICE_CON FIG - - - SPI_MODE FIFO_FLUSH - - SPI_SLEW_RATE INT2_DRIVE_ CIRCUIT INT2_MODE INT2_POLARI TY 09 09 TEMP_DATA1 R 0A 10 TEMP_DATA0 R TEMP_DATA[7:0] 0B 11 ACCEL_DATA_X1 R ACCEL_DATA_X[15:8] INT1_DRIVE_ CIRCUIT INT1_MODE INT1_POLARI TY TEMP_DATA[15:8] 0C 12 ACCEL_DATA_X0 R ACCEL_DATA_X[7:0] 0D 13 ACCEL_DATA_Y1 R ACCEL_DATA_Y[15:8] 0E 14 ACCEL_DATA_Y0 R ACCEL_DATA_Y[7:0] 0F 15 ACCEL_DATA_Z1 R ACCEL _DATA_Z[15:8] 10 16 ACCEL _DATA_Z0 R ACCEL _DATA_Z[7:0] 11 17 GYRO _DATA_X1 R GYRO _DATA_X[15:8] 12 18 GYRO _DATA_X0 R GYRO _DATA_X[7:0] 13 19 GYRO _DATA_Y1 R GYRO_DATA_Y[15:8] 14 20 GYRO _DATA_Y0 R GYRO_DATA_Y[7:0] 15 21 GYRO_DATA_Z1 R GYRO_DATA_Z[15:8] 16 22 GYRO_DATA_Z0 R GYRO_DATA_Z[7:0] 17 23 TMST_FSYNCH R TMST_FSYNC_DATA[15:8] TMST_FSYNC_DATA[7:0] 18 24 TMST_FSYNCL R 1D 29 APEX_DATA4 R FF_DUR[7:0] 1E 30 APEX_DATA5 R FF_DUR[15:8] 1F 31 PWR_MGMT0 R/W ACCEL_LP_CL K_SEL 20 32 GYRO_CONFIG0 R/W 21 33 ACCEL_CONFIG0 R/W 22 34 TEMP_CONFIG0 R/W - 23 35 GYRO_CONFIG1 R/W 24 36 ACCEL_CONFIG1 R/W 25 37 APEX_CONFIG0 R/W 26 38 APEX_CONFIG1 R/W 27 39 WOM_CONFIG R/W 28 40 FIFO_CONFIG1 R/W 29 41 FIFO_CONFIG2 R/W 2A 42 FIFO_CONFIG3 R/W - IDLE - GYRO_UI_FS_SEL - GYRO_ODR - ACCEL_UI_FS_SEL - ACCEL_ODR GYRO_MODE ACCEL_MODE TEMP_FILT_BW - - GYRO_UI_FILT_BW ACCEL_UI_AVG - - SMD_ENABL E FF_ENABLE TILT_ENABLE - ACCEL_UI_FILT_BW DMP_POWE R_SAVE_EN DMP_INIT_E N PED_ENABLE - WOM_INT_DUR DMP_MEM_ RESET_EN - DMP_ODR WOM_INT_ MODE - WOM_MODE WOM_EN FIFO_MODE FIFO_BYPASS FIFO_WM[7:0] - 2B 43 INT_SOURCE0 R/W ST_INT1_EN FSYNC_INT1_ EN 2C 44 INT_SOURCE1 R/W - I3C_PROTOC OL_ERROR_I NT1_EN 2D 45 INT_SOURCE3 R/W ST_INT2_EN FSYNC_INT2_ EN 2E 46 INT_SOURCE4 R/W - I3C_PROTOC OL_ERROR_I NT2_EN FIFO_WM[11:8] PLL_RDY_INT 1_EN RESET_DONE _INT1_EN - PLL_RDY_INT 2_EN Page 41 of 102 Document Number: DS-000451 Revision: 1.0 - RESET_DONE _INT2_EN - DRDY_INT1_ EN FIFO_THS_IN T1_EN FIFO_FULL_I NT1_EN AGC_RDY_IN T1_EN SMD_INT1_E N WOM_Z_INT 1_EN WOM_Y_INT 1_EN WOM_X_INT 1_EN DRDY_INT2_ EN FIFO_THS_IN T2_EN FIFO_FULL_I NT2_EN AGC_RDY_IN T2_EN SMD_INT2_E N WOM_Z_INT 2_EN WOM_Y_INT 2_EN WOM_X_INT 2_EN ICM-42670-P ADDR (HEX) ADDR (DEC) REGISTER NAME SERIAL I/F BIT7 BIT6 BIT5 BIT4 BIT3 2F 47 FIFO_LOST_PKT0 R FIFO_LOST_PKT_CNT[7:0] 30 48 FIFO_LOST_PKT1 R FIFO_LOST_PKT_CNT[15:8] 31 49 APEX_DATA0 R STEP_CNT[7:0] 32 50 APEX_DATA1 R STEP_CNT[15:8] 33 51 APEX_DATA2 R 34 52 APEX_DATA3 R 35 53 INTF_CONFIG0 R/W 36 54 INTF_CONFIG1 R/W 39 57 INT_STATUS_DRDY R/C 3A 58 INT_STATUS R/C 3B 59 INT_STATUS2 R/C BIT2 BIT1 BIT0 STEP_CADENCE FIFO_COUNT _FORMAT - FIFO_COUNT _ENDIAN DMP_IDLE SENSOR_DAT A_ENDIAN ACTIVITY_CLASS - - I3C_SDR_EN I3C_DDR_EN CLKSEL DATA_RDY_I NT ST_INT FSYNC_INT PLL_RDY_INT RESET_DONE _INT - FIFO_THS_IN T SMD_INT STEP_DET_IN T STEP_CNT_O VF_INT TILT_DET_IN T - 3C 60 INT_STATUS3 R/C - 3D 61 FIFO_COUNTH R FIFO_COUNT[15:8] 3E 62 FIFO_COUNTL R FIFO_COUNT[7:0] 3F 63 FIFO_DATA R FIFO_DATA 75 117 WHO_AM_I R WHOAMI 79 121 BLK_SEL_W R/W BLK_SEL_W 7A 122 MADDR_W R/W MADDR_W 7B 123 M_W R/W M_W 7C 124 BLK_SEL_R R/W BLK_SEL_R 7D 125 MADDR_R R/W MADDR_R 7E 126 M_R R/W M_R FIFO_FULL_I NT AGC_RDY_IN T WOM_X_INT WOM_Y_INT WOM_Z_INT FF_DET_INT LOWG_DET_I NT - USER BANK MREG1 REGISTER MAP ADDR (HEX) ADDR (DEC) REGISTER NAME SERIAL I/F 00 00 TMST_CONFIG1 R/W 01 01 FIFO_CONFIG5 R/W 02 02 FIFO_CONFIG6 R/W 03 03 FSYNC_CONFIG R/W 04 04 INT_CONFIG0 R/W BIT7 BIT6 BIT5 FIFO_WM_G T_TH - BIT3 BIT2 BIT1 BIT0 TMST_ON_S REG_EN TMST_RES TMST_DELTA _EN TMST_FSYNC _EN TMST_EN FIFO_RESUM E_PARTIAL_R D FIFO_HIRES_ EN FIFO_TMST_F SYNC_EN FIFO_GYRO_ EN FIFO_ACCEL_ EN FIFO_EMPTY _INDICATOR_ DIS - - 05 INT_CONFIG1 R/W - 06 06 SENSOR_CONFIG3 R/W - APEX_DISABL E 13 19 ST_CONFIG R/W - ST_NUMBER _SAMPLE 14 20 SELFTEST R/W GYRO_ST_EN ACCEL_ST_E N 23 35 INTF_CONFIG6 R/W 25 37 INTF_CONFIG10 R/W 28 40 INTF_CONFIG7 R/W 2B 43 OTP_CONFIG R/W - FSYNC_UI_FL AG_CLEAR_S EL - UI_DRDY_INT_CLEAR 05 RCOSC_REQ_ ON_FIFO_TH S_DIS - FSYNC_UI_SEL INT_TPULSE_ DURATION FIFO_THS_INT_CLEAR INT_ASYNC_ RESET FSYNC_POLA RITY FIFO_FULL_INT_CLEAR - ACCEL_ST_LIM GYRO_ST_LIM - I3C_TIMEOU T_EN ASYNCTIME0 _DIS I3C_IBI_BYTE _EN I3C_IBI_EN - I3C_DDR_WR _MODE - 2F 47 INT_SOURCE6 R/W FF_INT1_EN LOWG_INT1_ EN 30 48 INT_SOURCE7 R/W FF_INT2_EN LOWG_INT2_ EN - OTP_COPY_MODE - STEP_DET_IN T1_EN STEP_CNT_O FL_INT1_EN TILT_DET_IN T1_EN - STEP_DET_IN T2_EN STEP_CNT_O FL_INT2_EN TILT_DET_IN T2_EN - Page 42 of 102 Document Number: DS-000451 Revision: 1.0 BIT4 ICM-42670-P ADDR (HEX) ADDR (DEC) REGISTER NAME SERIAL I/F 31 49 INT_SOURCE8 R/W 32 50 INT_SOURCE9 R/W 33 51 INT_SOURCE10 R/W 44 68 APEX_CONFIG2 R/W LOW_ENERGY_AMP_TH_SEL 45 69 APEX_CONFIG3 R/W PED_AMP_TH_SEL 46 70 APEX_CONFIG4 R/W 47 71 APEX_CONFIG5 R/W 48 72 APEX_CONFIG9 R/W BIT7 BIT6 - I3C_PROTOC OL_ERROR_I BI_EN FF_IBI_EN - BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 FSYNC_IBI_E N PLL_RDY_IBI_ EN UI_DRDY_IBI _EN FIFO_THS_IBI _EN FIFO_FULL_IB I_EN AGC_RDY_IBI _EN LOWG_IBI_E N SMD_IBI_EN WOM_Z_IBI_ EN WOM_Y_IBI_ EN WOM_X_IBI_ EN ST_DONE_IBI _EN STEP_DET_IB I_EN STEP_CNT_O FL_IBI_EN TILT_DET_IBI _EN DMP_POWER_SAVE_TIME_SEL PED_STEP_CNT_TH_SEL PED_STEP_DET_TH_SEL PED_SB_TIMER_TH_SEL TILT_WAIT_TIME_SEL PED_HI_EN_TH_SEL LOWG_PEAK_TH_HYST_SEL HIGHG_PEAK_TH_HYST_SEL FF_DEBOUNCE_DURATION_SEL SENSITIVITY_ MODE SMD_SENSITIVITY_SEL 49 73 APEX_CONFIG10 R/W LOWG_PEAK_TH_SEL LOWG_TIME_TH_SEL 4A 74 APEX_CONFIG11 R/W HIGHG_PEAK_TH_SEL HIGHG_TIME_TH_SEL 4B 75 ACCEL_WOM_X_THR R/W WOM_X_TH 4C 76 ACCEL_WOM_Y_THR R/W WOM_Y_TH 4D 77 ACCEL_WOM_Z_THR R/W WOM_Z_TH 4E 78 OFFSET_USER0 R/W GYRO_X_OFFUSER[7:0] 4F 79 OFFSET_USER1 R/W 50 80 OFFSET_USER2 R/W GYRO_Y_OFFUSER[11:8] GYRO_X_OFFUSER[11:8] 51 81 OFFSET_USER3 R/W 52 82 OFFSET_USER4 R/W 53 83 OFFSET_USER5 R/W 54 84 OFFSET_USER6 R/W 55 85 OFFSET_USER7 R/W 56 86 OFFSET_USER8 R/W 63 99 ST_STATUS1 R 64 100 ST_STATUS2 R 66 102 FDR_CONFIG R/W - FDR_SEL 67 103 APEX_CONFIG12 R/W FF_MAX_DURATION_SEL FF_MIN_DURATION_SEL GYRO_Y_OFFUSER[7:0] GYRO_Z_OFFUSER[7:0] ACCEL_X_OFFUSER[11:8] GYRO_Z_OFFUSER[11:8] ACCEL_X_OFFUSER[7:0] ACCEL_Y_OFFUSER[7:0] ACCEL_Z_OFFUSER[11:8] ACCEL_Y_OFFUSER[11:8] ACCEL_Z_OFFUSER[7:0] - ST_INCOMPL ETE ACCEL_ST_P ASS ACCEL_ST_D ONE AZ_ST_PASS AY_ST_PASS AX_ST_PASS - GYRO_ST_PA SS GYRO_ST_DO NE GZ_ST_PASS GY_ST_PASS GX_ST_PASS - USER BANK MREG2 REGISTER MAP ADDR (HEX) ADDR (DEC) REGISTER NAME SERIAL I/F 06 06 OTP_CTRL7 R/W BIT7 BIT6 BIT5 BIT4 - BIT3 BIT2 BIT1 BIT0 OTP_RELOAD - OTP_PWR_D OWN - BIT3 BIT2 BIT1 BIT0 USER BANK MREG3 REGISTER MAP ADDR (HEX) ADDR (DEC) REGISTER NAME SERIAL I/F 00 00 XA_ST_DATA R XA_ST_DATA 01 01 YA_ST_DATA R YA_ST_DATA 02 02 ZA_ST_DATA R ZA_ST_DATA 03 03 XG_ST_DATA R XG_ST_DATA 04 04 YG_ST_DATA R YG_ST_DATA 05 05 ZG_ST_DATA R ZG_ST_DATA BIT7 BIT6 Page 43 of 102 Document Number: DS-000451 Revision: 1.0 BIT5 BIT4 ICM-42670-P Detailed register descriptions are provided in the sections that follow. Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used to determine the default value of reserved register fields, and unless otherwise noted this default value must be maintained even if the values of other register fields are modified by the user. In the sections that follow, some register fields are described as can be changed on-the-fly even if sensor is on. These are the only register fields that can be changed on-the-fly even if sensor is on. Register fields not described as such must not be changed on-the-fly if sensor is on. Page 44 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P USER BANK 0 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within user bank 0. Note: The device powers up in sleep mode. MCLK_RDY Name: MCLK_RDY Address: 00 (00h) Serial IF: R Reset value: 0x00 at power-up, changes to 0x01 after OTP load is completed BIT NAME FUNCTION 7:4 Reserved 0: Indicates internal clock is currently not running 3 MCLK_RDY 1: Indicates internal clock is currently running 2:0 Reserved DEVICE_CONFIG Name: DEVICE_CONFIG Address: 01 (01h) Serial IF: R/W Reset value: 0x04 BIT NAME 7:3 2 SPI_AP_4WIRE 1 - 0 SPI_MODE FUNCTION Reserved 0: AP interface uses 3-wire SPI mode 1: AP interface uses 4-wire SPI mode Reserved SPI mode selection 0: Mode 0 and Mode 3 1: Mode 1 and Mode 2 If device is operating in non-SPI mode, user is not allowed to change the power-on default setting of this register. Change of this register setting will not take effect till AP_CS = 1. Page 45 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P SIGNAL_PATH_RESET Name: SIGNAL_PATH_RESET Address: 02 (02h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:5 4 SOFT_RESET_DEVICE_CON FIG 3 - 2 FIFO_FLUSH 1:0 - FUNCTION Reserved Software Reset (auto clear bit) 0: Software reset not enabled 1: Software reset enabled Reserved When set to 1, FIFO will get flushed. FIFO flush requires the following programming sequence: • Write FIFO_FLUSH =1 • Wait for 1.5 µs • Read FIFO_FLUSH, it should now be 0 Host can only program this register bit to 1. Reserved Page 46 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P DRIVE_CONFIG1 Name: DRIVE_CONFIG1 Address: 03 (03h) Serial IF: R/W Reset value: 0x2B BIT NAME 7:6 - 5:3 I3C_DDR_SLEW_RATE FUNCTION Reserved Controls slew rate for output pin 14 when device is in I3CSM DDR protocol. While in I3CSM operation, the device automatically switches to use I3C_DDR_SLEW_RATE after receiving ENTHDR0 ccc command from the host. The device automatically switches back to I3C_SDR_SLEW_RATE after the host issues HDR_EXIT pattern. 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 101: MAX: 2 ns 110: Reserved 111: Reserved This register field should not be programmed in I3C/DDR mode. Controls slew rate for output pin 14 in I3CSM SDR protocol. After device reset, I2C_SLEW_RATE is used by default. If I3CSM feature is enabled, the device automatically switches to use I3C_SDR_SLEW_RATE after receiving 0x7E+W message (an I3CSM broadcast message). 2:0 I3C_SDR_SLEW_RATE 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 101: MAX: 2 ns 110: Reserved 111: Reserved This register field should not be programmed in I3C/DDR mode Page 47 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P DRIVE_CONFIG2 Name: DRIVE_CONFIG2 Address: 04 (04h) Serial IF: R/W Reset value: 0x0D BIT NAME 7:6 - 5:3 I2C_SLEW_RATE FUNCTION Reserved Controls slew rate for output pin 14 in I2C mode. After device reset, the I2C_SLEW_RATE is used by default. If the 1st write operation from host is an SPI transaction, the device automatically switches to SPI_SLEW_RATE. If I3CSM feature is enabled, the device automatically switches to I3C_SDR_SLEW_RATE after receiving 0x7E+W message (an I3C broadcast message). 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 101: MAX: 2 ns 110: Reserved 111: Reserved This register field should not be programmed in I3C/DDR mode Configure drive strength for all output pins in all modes (SPI3, SPI4, I 2C, I3CSM) excluding pin 14. 2:0 ALL_SLEW_RATE 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 101: MAX: 2 ns 110: Reserved 111: Reserved This register field should not be programmed in I3C/DDR mode Page 48 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P DRIVE_CONFIG3 Name: DRIVE_CONFIG3 Address: 05 (05h) Serial IF: R/W Reset value: 0x05 BIT NAME 7:3 - 2:0 SPI_SLEW_RATE FUNCTION Reserved Controls slew rate for output pin 14 in SPI 3-wire mode. In SPI 4-wire mode this register controls the slew rate of pin 1 as it is used as an output in SPI 4wire mode only. After chip reset, the I2C_SLEW_RATE is used by default for pin 14 pin. If the 1st write operation from the host is an SPI3/4 transaction, the device automatically switches to SPI_SLEW_RATE. 000: MIN: 20 ns; TYP: 40 ns; MAX: 60 ns 001: MIN: 12 ns; TYP: 24 ns; MAX: 36 ns 010: MIN: 6 ns; TYP: 12 ns; MAX: 19 ns 011: MIN: 4 ns; TYP: 8 ns; MAX: 14 ns 100: MIN: 2 ns; TYP: 4 ns; MAX: 8 ns 101: MAX: 2 ns 110: Reserved 111: Reserved This register field should not be programmed in I3C/DDR mode Page 49 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_CONFIG Name: INT_CONFIG Address: 06 (06h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:6 5 INT2_MODE 4 INT2_DRIVE_CIRCUIT 3 INT2_POLARITY 2 INT1_MODE 1 INT1_DRIVE_CIRCUIT 0 INT1_POLARITY FUNCTION Reserved INT2 interrupt mode 0: Pulsed mode 1: Latched mode INT2 drive circuit 0: Open drain 1: Push pull INT2 interrupt polarity 0: Active low 1: Active high INT1 interrupt mode 0: Pulsed mode 1: Latched mode INT1 drive circuit 0: Open drain 1: Push pull INT1 interrupt polarity 0: Active low 1: Active high TEMP_DATA1 Name: TEMP_DATA1 Address: 09 (09h) Serial IF: R Reset value: 0x80 BIT NAME 7:0 TEMP_DATA[15:8] FUNCTION Upper byte of temperature data Page 50 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P TEMP_DATA0 Name: TEMP_DATA0 Address: 10 (0Ah) Serial IF: R Reset value: 0x00 BIT NAME 7:0 TEMP_DATA[7:0] FUNCTION Lower byte of temperature data Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula: • Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25 Temperature data stored in FIFO can be an 8-bit or 16-bit quantity, depending on packet format. It can be converted to degrees centigrade by using the following formulas: • • 8-bit quantity: Temperature in Degrees Centigrade = (TEMP_DATA / 2) + 25; where TEMP_DATA refers to the 8 MSBs of the 16-bit word coming from the temperature sensor. In this mode the 8 LSBs are set to ‘0’. 16-bit quantity: Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25 ACCEL_DATA_X1 Name: ACCEL_DATA_X1 Address: 11 (0Bh) Serial IF: R Reset value: 0x80 BIT NAME 7:0 ACCEL_DATA_X[15:8] FUNCTION Upper byte of Accel X-axis data ACCEL_DATA_X0 Name: ACCEL_DATA_X0 Address: 12 (0Ch) Serial IF: R Reset value: 0x00 BIT NAME 7:0 ACCEL_DATA_X[7:0] FUNCTION Lower byte of Accel X-axis data ACCEL_DATA_Y1 Name: ACCEL_DATA_Y1 Address: 13 (0Dh) Serial IF: R Reset value: 0x80 BIT NAME 7:0 ACCEL_DATA_Y[15:8] FUNCTION Upper byte of Accel Y-axis data Page 51 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ACCEL_DATA_Y0 Name: ACCEL_DATA_Y0 Address: 14 (0Eh) Serial IF: R Reset value: 0x00 BIT NAME 7:0 ACCEL_DATA_Y[7:0] FUNCTION Lower byte of Accel Y-axis data ACCEL_DATA_Z1 Name: ACCEL_DATA_Z1 Address: 15 (0Fh) Serial IF: R Reset value: 0x80 BIT NAME 7:0 ACCEL_DATA_Z[15:8] FUNCTION Upper byte of Accel Z-axis data ACCEL_DATA_Z0 Name: ACCEL_DATA_Z0 Address: 16 (10h) Serial IF: R Reset value: 0x00 BIT NAME 7:0 ACCEL_DATA_Z[7:0] FUNCTION Lower byte of Accel Z-axis data GYRO_DATA_X1 Name: GYRO_DATA_X1 Address: 17 (11h) Serial IF: R Reset value: 0x80 BIT NAME 7:0 GYRO_DATA_X[15:8] FUNCTION Upper byte of Gyro X-axis data GYRO_DATA_X0 Name: GYRO_DATA_X0 Address: 18 (12h) Serial IF: R Reset value: 0x00 BIT NAME 7:0 GYRO_DATA_X[7:0] FUNCTION Lower byte of Gyro X-axis data Page 52 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P GYRO_DATA_Y1 Name: GYRO_DATA_Y1 Address: 19 (13h) Serial IF: R Reset value: 0x80 BIT NAME 7:0 GYRO_DATA_Y[15:8] FUNCTION Upper byte of Gyro Y-axis data GYRO_DATA_Y0 Name: GYRO_DATA_Y0 Address: 20 (14h) Serial IF: R Reset value: 0x00 BIT NAME 7:0 GYRO_DATA_Y[7:0] FUNCTION Lower byte of Gyro Y-axis data GYRO_DATA_Z1 Name: GYRO_DATA_Z1 Address: 21 (15h) Serial IF: R Reset value: 0x80 BIT NAME 7:0 GYRO_DATA_Z[15:8] FUNCTION Upper byte of Gyro Z-axis data GYRO_DATA_Z0 Name: GYRO_DATA_Z0 Address: 22 (16h) Serial IF: R Reset value: 0x00 BIT NAME 7:0 GYRO_DATA_Z[7:0] FUNCTION Lower byte of Gyro Z-axis data TMST_FSYNCH Name: TMST_FSYNCH Address: 23 (17h) Serial IF: SYNCR Reset value: 0x00 BIT NAME 7:0 TMST_FSYNC_DATA[15:8] FUNCTION Stores the upper byte of the time delta from the rising edge of FSYNC to the latest ODR until the UI Interface reads the FSYNC tag in the status register Page 53 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P TMST_FSYNCL Name: TMST_FSYNCL Address: 24 (18h) Serial IF: SYNCR Reset value: 0x00 BIT NAME 7:0 TMST_FSYNC_DATA[7:0] FUNCTION Stores the lower byte of the time delta from the rising edge of FSYNC to the latest ODR until the UI Interface reads the FSYNC tag in the status register APEX_DATA4 Name: APEX_DATA4 Address: 29 (1Dh) Serial IF: R Reset value: 0x00 BIT NAME FUNCTION Lower byte of Freefall Duration 7:0 FF_DUR[7:0] The duration is given in number of samples and it can be converted to freefall distance in meters by applying the following formula: FF_DISTANCE = 0.5*9.81*(FF_DUR*DMP_ODR_S)^2 Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds. APEX_DATA5 Name: APEX_DATA5 Address: 30 (1Eh) Serial IF: R Reset value: 0x00 BIT NAME FUNCTION Upper byte of Freefall Duration 7:0 FF_DUR[15:8] The duration is given in number of samples and it can be converted to freefall distance in meters by applying the following formula: FF_DISTANCE = 0.5*9.81*(FF_DUR*DMP_ODR_S)^2 Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds. Page 54 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P PWR_MGMT0 Name: PWR_MGMT0 Address: 31 (1Fh) Serial IF: R/W Reset value: 0x00 BIT NAME 7 6:5 4 ACCEL_LP_CLK_SEL - IDLE FUNCTION 0: Accelerometer LP mode uses Wake Up oscillator clock. This is the lowest power consumption mode and it is the recommended setting. 1: Accelerometer LP mode uses RC oscillator clock This field can be changed on-the-fly even if accel sensor is on Reserved If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro are powered off. Nominally this bit is set to 0, so when Accel and Gyro are powered off, the chip will go to OFF state, since the RC oscillator will also be powered off This field can be changed on-the-fly even if a sensor is on 00: Turns gyroscope off 01: Places gyroscope in Standby Mode 10: Reserved 11: Places gyroscope in Low Noise (LN) Mode 3:2 GYRO_MODE Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning from OFF to any of the other modes, do not issue any register writes for 200 µs. This field can be changed on-the-fly even if gyro sensor is on 00: Turns accelerometer off 01: Turns accelerometer off 10: Places accelerometer in Low Power (LP) Mode 11: Places accelerometer in Low Noise (LN) Mode When selecting LP Mode please refer to ACCEL_LP_CLK_SEL setting, bit[7] of this register. 1:0 ACCEL_MODE Before entering LP mode and during LP Mode the following combinations of ODR and averaging are not permitted: 1) ODR=1600 Hz or ODR=800 Hz: any averaging. 2) ODR=400 Hz: averaging=16x, 32x or 64x. 3) ODR=200 Hz: averaging=64x. When transitioning from OFF to any of the other modes, do not issue any register writes for 200 µs. This field can be changed on-the-fly even if accel sensor is on Page 55 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P GYRO_CONFIG0 Name: GYRO_CONFIG0 Address: 32 (20h) Serial IF: R/W Reset value: 0x06 BIT NAME 7 - 6:5 4 3:0 FUNCTION Reserved Full scale select for gyroscope UI interface output GYRO_UI_FS_SEL 00: ±2000 dps 01: ±1000 dps 10: ±500 dps 11: ±250 dps - This field can be changed on-the-fly even if gyro sensor is on Reserved Gyroscope ODR selection for UI interface output GYRO_ODR 0000: Reserved 0001: Reserved 0010: Reserved 0011: Reserved 0100: Reserved 0101: 1.6k Hz 0110: 800 Hz 0111: 400 Hz 1000: 200 Hz 1001: 100 Hz 1010: 50 Hz 1011: 25 Hz 1100: 12.5 Hz 1101: Reserved 1110: Reserved 1111: Reserved This field can be changed on-the-fly even if gyro sensor is on Page 56 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ACCEL_CONFIG0 Name: ACCEL_CONFIG0 Address: 33 (21h) Serial IF: R/W Reset value: 0x06 BIT NAME 7 - 6:5 4 3:0 FUNCTION Reserved Full scale select for accelerometer UI interface output ACCEL_UI_FS_SEL 00: ±16g 01: ±8g 10: ±4g 11: ±2g - This field can be changed on-the-fly even if accel sensor is on Reserved Accelerometer ODR selection for UI interface output ACCEL_ODR 0000: Reserved 0001: Reserved 0010: Reserved 0011: Reserved 0100: Reserved 0101: 1.6 kHz (LN mode) 0110: 800 Hz (LN mode) 0111: 400 Hz (LP or LN mode) 1000: 200 Hz (LP or LN mode) 1001: 100 Hz (LP or LN mode) 1010: 50 Hz (LP or LN mode) 1011: 25 Hz (LP or LN mode) 1100: 12.5 Hz (LP or LN mode) 1101: 6.25 Hz (LP mode) 1110: 3.125 Hz (LP mode) 1111: 1.5625 Hz (LP mode) This field can be changed on-the-fly when accel sensor is on Page 57 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P TEMP_CONFIG0 Name: TEMP_CONFIG0 Address: 34 (22h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 - 6:4 3:0 TEMP_FILT_BW - FUNCTION Reserved Sets the bandwidth of the temperature signal DLPF 000: DLPF bypassed 001: DLPF BW = 180 Hz 010: DLPF BW = 72 Hz 011: DLPF BW = 34 Hz 100: DLPF BW = 16 Hz 101: DLPF BW = 8 Hz 110: DLPF BW = 4 Hz 111: DLPF BW = 4 Hz This field can be changed on-the-fly even if sensor is on Reserved GYRO_CONFIG1 Name: GYRO_CONFIG1 Address: 35 (23h) Serial IF: R/W Reset value: 0x31 BIT NAME 7:3 - 2:0 GYRO_UI_FILT_BW FUNCTION Reserved Selects GYRO UI low pass filter bandwidth 000: Low pass filter bypassed 001: 180 Hz 010: 121 Hz 011: 73 Hz 100: 53 Hz 101: 34 Hz 110: 25 Hz 111: 16 Hz This field can be changed on-the-fly even if gyro sensor is on Page 58 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ACCEL_CONFIG1 Name: ACCEL_CONFIG1 Address: 36 (24h) Serial IF: R/W Reset value: 0x41 BIT NAME 7 - 6:4 3 2:0 ACCEL_UI_AVG FUNCTION Reserved Selects averaging filter setting to create accelerometer output in accelerometer low power mode (LPM) 000: 2x average 001: 4x average 010: 8x average 011: 16x average 100: 32x average 101: 64x average 110: 64x average 111: 64x average - This field cannot be changed when the accel sensor is in LPM Reserved Selects ACCEL UI low pass filter bandwidth ACCEL_UI_FILT_BW 000: Low pass filter bypassed 001: 180 Hz 010: 121 Hz 011: 73 Hz 100: 53 Hz 101: 34 Hz 110: 25 Hz 111: 16 Hz This field can be changed on-the-fly even if accel sensor is on APEX_CONFIG0 Name: APEX_CONFIG0 Address: 37 (25h) Serial IF: R/W Reset value: 0x08 BIT NAME 7:4 3 DMP_POWER_SAVE_EN 2 DMP_INIT_EN 1 - 0 DMP_MEM_RESET_EN FUNCTION Reserved When this bit is set to 1, power saving is enabled for DMP algorithms When this bit is set to 1, DMP runs DMP SW initialization procedure. Bit is reset by hardware when the procedure is finished. All other APEX features are ignored as long as DMP_INIT_EN is set. This field can be changed on-the-fly even if accel sensor is on. Reserved When this bit is set to 1, it clears DMP SRAM for APEX operation or Self-test operation. Page 59 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_CONFIG1 Name: APEX_CONFIG1 Address: 38 (26h) Serial IF: R/W Reset value: 0x02 BIT NAME 7 6 5 4 3 2 1:0 SMD_ENABLE FF_ENABLE TILT_ENABLE PED_ENABLE - FUNCTION Reserved 0: Significant Motion Detection not enabled 1: Significant Motion Detection enabled This field can be changed on-the-fly even if accel sensor is on 0: Freefall Detection not enabled 1: Freefall Detection enabled This field can be changed on-the-fly even if accel sensor is on 0: Tilt Detection not enabled 1: Tilt Detection enabled This field can be changed on-the-fly even if accel sensor is on 0: Pedometer not enabled 1: Pedometer enabled This field can be changed on-the-fly even if accel sensor is on Reserved 00: 25 Hz 01: 400 Hz 10: 50 Hz 11: 100 Hz DMP_ODR The ACCEL_ODR field must be configured to an ODR equal or greater to the DMP_ODR field, for correct device operation. This field can be changed on-the-fly even if accel sensor is on Page 60 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P WOM_CONFIG Name: WOM_CONFIG Address: 39 (27h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:5 - 4:3 WOM_INT_DUR FUNCTION Reserved Selects Wake on Motion interrupt assertion from among the following options 00: WoM interrupt asserted at first overthreshold event 01: WoM interrupt asserted at second overthreshold event 10: WoM interrupt asserted at third overthreshold event 11: WoM interrupt asserted at fourth overthreshold event This field can be changed on-the-fly even if accel sensor is on, but it cannot be changed if WOM_EN is already enabled 0: Set WoM interrupt on the OR of all enabled accelerometer thresholds 1: Set WoM interrupt on the AND of all enabled accelerometer thresholds 2 WOM_INT_MODE This field can be changed on-the-fly even if accel sensor is on, but it cannot be changed if WOM_EN is already enabled 0: Initial sample is stored. Future samples are compared to initial sample 1: Compare current sample to previous sample 1 0 WOM_MODE WOM_EN This field can be changed on-the-fly even if accel sensor is on, but it cannot be changed if WOM_EN is already enabled 0: WOM disabled 1: WOM enabled This field can be changed on-the-fly even if accel sensor is on FIFO_CONFIG1 Name: FIFO_CONFIG1 Address: 40 (28h) Serial IF: R/W Reset value: 0x01 BIT NAME 7:2 1 FIFO_MODE 0 FIFO_BYPASS FUNCTION Reserved FIFO mode control 0: Stream-to-FIFO Mode 1: STOP-on-FULL Mode FIFO bypass control 0: FIFO is not bypassed 1: FIFO is bypassed Page 61 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO_CONFIG2 Name: FIFO_CONFIG2 Address: 41 (29h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 FIFO_WM[7:0] FUNCTION Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches or exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing this register. Interrupt only fires once. This register should be set to nonzero value, before choosing this interrupt source. This field should be changed when FIFO is empty to avoid spurious interrupts. FIFO_CONFIG3 Name: FIFO_CONFIG3 Address: 42 (2Ah) Serial IF: R/W Reset value: 0x00 BIT NAME 7:4 - 3:0 FIFO_WM[11:8] FUNCTION Reserved Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches or exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing this register. Interrupt only fires once. This register should be set to nonzero value, before choosing this interrupt source. This field should be changed when FIFO is empty to avoid spurious interrupts. Page 62 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_SOURCE0 Name: INT_SOURCE0 Address: 43 (2Bh) Serial IF: R/W Reset value: 0x10 BIT NAME 7 ST_INT1_EN 6 FSYNC_INT1_EN 5 PLL_RDY_INT1_EN 4 RESET_DONE_INT1_EN 3 DRDY_INT1_EN 2 FIFO_THS_INT1_EN 1 FIFO_FULL_INT1_EN 0 AGC_RDY_INT1_EN FUNCTION 0: Self-Test Done interrupt not routed to INT1 1: Self-Test Done interrupt routed to INT1 0: FSYNC interrupt not routed to INT1 1: FSYNC interrupt routed to INT1 0: PLL ready interrupt not routed to INT1 1: PLL ready interrupt routed to INT1 0: Reset done interrupt not routed to INT1 1: Reset done interrupt routed to INT1 0: Data Ready interrupt not routed to INT1 1: Data Ready interrupt routed to INT1 0: FIFO threshold interrupt not routed to INT1 1: FIFO threshold interrupt routed to INT1 0: FIFO full interrupt not routed to INT1 1: FIFO full interrupt routed to INT1 To avoid FIFO FULL interrupts while reading FIFO, this bit should be disabled while reading FIFO 0: UI AGC ready interrupt not routed to INT1 1: UI AGC ready interrupt routed to INT1 INT_SOURCE1 Name: INT_SOURCE1 Address: 44 (2Ch) Serial IF: R/W Reset value: 0x00 BIT NAME 7 I3C_PROTOCOL_ERROR_IN 6 T1_EN 5:4 3 SMD_INT1_EN 2 WOM_Z_INT1_EN 1 WOM_Y_INT1_EN 0 WOM_X_INT1_EN FUNCTION Reserved 0: I3CSM protocol error interrupt not routed to INT1 1: I3CSM protocol error interrupt routed to INT1 Reserved 0: SMD interrupt not routed to INT1 1: SMD interrupt routed to INT1 0: Z-axis WOM interrupt not routed to INT1 1: Z-axis WOM interrupt routed to INT1 0: Y-axis WOM interrupt not routed to INT1 1: Y-axis WOM interrupt routed to INT1 0: X-axis WOM interrupt not routed to INT1 1: X-axis WOM interrupt routed to INT1 Page 63 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_SOURCE3 Name: INT_SOURCE3 Address: 45 (2Dh) Serial IF: R/W Reset value: 0x00 BIT NAME 7 ST_INT2_EN 6 FSYNC_INT2_EN 5 PLL_RDY_INT2_EN 4 RESET_DONE_INT2_EN 3 DRDY_INT2_EN 2 FIFO_THS_INT2_EN 1 FIFO_FULL_INT2_EN 0 AGC_RDY_INT2_EN FUNCTION 0: Self-Test Done interrupt not routed to INT2 1: Self-Test Done interrupt routed to INT2 0: FSYNC interrupt not routed to INT2 1: FSYNC interrupt routed to INT2 0: PLL ready interrupt not routed to INT2 1: PLL ready interrupt routed to INT2 0: Reset done interrupt not routed to INT2 1: Reset done interrupt routed to INT2 0: Data Ready interrupt not routed to INT2 1: Data Ready interrupt routed to INT2 0: FIFO threshold interrupt not routed to INT2 1: FIFO threshold interrupt routed to INT2 0: FIFO full interrupt not routed to INT2 1: FIFO full interrupt routed to INT2 0: AGC ready interrupt not routed to INT2 1: AGC ready interrupt routed to INT2 INT_SOURCE4 Name: INT_SOURCE4 Address: 46 (2Eh) Serial IF: R/W Reset value: 0x00 BIT NAME 7 I3C_PROTOCOL_ERROR_IN 6 T2_EN 5:4 3 SMD_INT2_EN 2 WOM_Z_INT2_EN 1 WOM_Y_INT2_EN 0 WOM_X_INT2_EN FUNCTION Reserved 0: I3CSM protocol error interrupt not routed to INT2 1: I3CSM protocol error interrupt routed to INT2 Reserved 0: SMD interrupt not routed to INT2 1: SMD interrupt routed to INT2 0: Z-axis WOM interrupt not routed to INT2 1: Z-axis WOM interrupt routed to INT2 0: Y-axis WOM interrupt not routed to INT2 1: Y-axis WOM interrupt routed to INT2 0: X-axis WOM interrupt not routed to INT2 1: X-axis WOM interrupt routed to INT2 Page 64 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO_LOST_PKT0 Name: FIFO_LOST_PKT0 Address: 47 (2Fh) Serial IF: R Reset value: 0x00 BIT NAME 7:0 FIFO_LOST_PKT_CNT[7:0] FUNCTION Low byte, number of packets lost in the FIFO FIFO_LOST_PKT1 Name: FIFO_LOST_PKT1 Address: 48 (30h) Serial IF: R Reset value: 0x00 BIT NAME 7:0 FIFO_LOST_PKT_CNT[15:8] FUNCTION High byte, number of packets lost in the FIFO APEX_DATA0 Name: APEX_DATA0 Address: 49 (31h) Serial IF: SYNCR Reset value: 0x00 BIT NAME 7:0 STEP_CNT[7:0] FUNCTION Pedometer Output: Lower byte of Step Count measured by pedometer APEX_DATA1 Name: APEX_DATA1 Address: 50 (32h) Serial IF: SYNCR Reset value: 0x00 BIT NAME 7:0 STEP_CNT[15:8] FUNCTION Pedometer Output: Upper byte of Step Count measured by pedometer APEX_DATA2 Name: APEX_DATA2 Address: 51 (33h) Serial IF: R Reset value: 0x00 BIT NAME 7:0 STEP_CADENCE FUNCTION Pedometer Output: Walk/run cadency in number of samples. Format is u6.2. e.g. At 50 Hz ODR and 2 Hz walk frequency, the cadency is 25 samples and the register will output 100. Page 65 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_DATA3 Name: APEX_DATA3 Address: 52 (34h) Serial IF: R Reset value: 0x04 BIT NAME 7:3 2 1:0 DMP_IDLE ACTIVITY_CLASS FUNCTION Reserved 0: Indicates DMP is running 1: Indicates DMP is idle Pedometer Output: Detected activity 00: Unknown 01: Walk 10: Run 11: Reserved INTF_CONFIG0 Name: INTF_CONFIG0 Address: 53 (35h) Serial IF: R/W Reset value: 0x30 BIT NAME 7 6 FIFO_COUNT_FORMAT 5 FIFO_COUNT_ENDIAN 4 SENSOR_DATA_ENDIAN 3:0 - FUNCTION Reserved 0: FIFO count is reported in bytes 1: FIFO count is reported in records (1 record = 16 bytes for header + gyro + accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel + temp sensor data) This bit applies to FIFO Count and Lost Packet Count 0: Reported in Little Endian format 1: Reported in Big Endian format 0: Sensor data is reported in Little Endian format 1: Sensor data is reported in Big Endian format Reserved Page 66 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INTF_CONFIG1 Name: INTF_CONFIG1 Address: 54 (36h) Serial IF: R/W Reset value: 0x4D BIT NAME 7:4 3 2 1:0 I3C_SDR_EN I3C_DDR_EN CLKSEL FUNCTION Reserved 0: I3CSM SDR mode not enabled 1: I3CSM SDR mode enabled Device will be in pure I2C mode if {I3C_SDR_EN, I3C_DDR_EN} = 00 0: I3CSM DDR mode not enabled 1: I3CSM DDR mode enabled This bit will not take effect unless I3C_SDR_EN = 1. 00: Always select internal RC oscillator 01: Select PLL when available, else select RC oscillator (default) 10: Reserved 11: Disable all clocks INT_STATUS_DRDY Name: INT_STATUS_DRDY Address: 57 (39h) Serial IF: R/C Reset value: 0x00 BIT NAME 7:1 0 DATA_RDY_INT FUNCTION Reserved This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears to 0 after the register has been read. Page 67 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_STATUS Name: INT_STATUS Address: 58 (3Ah) Serial IF: R/C Reset value: 0x10 BIT NAME 7 ST_INT 6 FSYNC_INT 5 PLL_RDY_INT 4 RESET_DONE_INT 3 - 2 FIFO_THS_INT 1 FIFO_FULL_INT 0 AGC_RDY_INT FUNCTION This bit automatically sets to 1 when a Self Test done interrupt is generated. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when an FSYNC interrupt is generated. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when a PLL Ready interrupt is generated. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when software reset is complete. The bit clears to 0 after the register has been read. Reserved This bit automatically sets to 1 when the FIFO buffer reaches the threshold value. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when an AGC Ready interrupt is generated. The bit clears to 0 after the register has been read. INT_STATUS2 Name: INT_STATUS2 Address: 59 (3Bh) Serial IF: R/C Reset value: 0x00 BIT NAME 7:4 3 SMD_INT 2 WOM_X_INT 1 WOM_Y_INT 0 WOM_Z_INT FUNCTION Reserved Significant Motion Detection Interrupt, clears on read Wake on Motion Interrupt on X-axis, clears on read Wake on Motion Interrupt on Y-axis, clears on read Wake on Motion Interrupt on Z-axis, clears on read INT_STATUS3 Name: INT_STATUS3 Address: 60 (3Ch) Serial IF: R/C Reset value: 0x00 BIT NAME 7:6 5 STEP_DET_INT 4 STEP_CNT_OVF_INT 3 TILT_DET_INT 2 FF_DET_INT 1 LOWG_DET_INT 0 - FUNCTION Reserved Step Detection Interrupt, clears on read Step Count Overflow Interrupt, clears on read Tilt Detection Interrupt, clears on read Freefall Interrupt, clears on read LowG Interrupt, clears on read Reserved Page 68 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO_COUNTH Name: FIFO_COUNTH Address: 61 (3Dh) Serial IF: R Reset value: 0x00 BIT NAME 7:0 FIFO_COUNT[15:8] FUNCTION High Bits, count indicates the number of records or bytes available in FIFO according to FIFO_COUNT_FORMAT setting. Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH and FIFO_COUNTL. FIFO_COUNTL Name: FIFO_COUNTL Address: 62 (3Eh) Serial IF: R Reset value: 0x00 BIT NAME 7:0 FIFO_COUNT[7:0] FUNCTION Low Bits, count indicates the number of records or bytes available in FIFO according to FIFO_COUNT_REC setting. Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL. FIFO_DATA Name: FIFO_DATA Address: 63 (3Fh) Serial IF: R Reset value: 0xFF BIT NAME 7:0 FIFO_DATA FUNCTION FIFO data port WHO_AM_I Name: WHO_AM_I Address: 117 (75h) Serial IF: R Reset value: 0x67 BIT NAME 7:0 WHOAMI FUNCTION Register to indicate to user which device is being accessed Description: This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the register is 0x67. This is different from the I 2C address of the device as seen on the slave I2C controller by the applications processor. Page 69 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P BLK_SEL_W Name: BLK_SEL_W Address: 121 (79h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 BLK_SEL_W FUNCTION Block address for accessing MREG1 or MREG2 register space for register write operation MADDR_W Name: MADDR_W Address: 122 (7Ah) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 MADDR_W FUNCTION To write to a register in MREG1 or MREG2 space, set this register field to the address of the register in MREG1 or MREG2 space. M_W Name: M_W Address: 123 (7Bh) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 M_W FUNCTION To write a value to a register in MREG1 or MREG2 space, that value must be written to M_W. BLK_SEL_R Name: BLK_SEL_R Address: 124 (7Ch) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 BLK_SEL_R FUNCTION Block address for accessing MREG1 or MREG2 register space for register read operation Page 70 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P MADDR_R Name: MADDR_R Address: 125 (7Dh) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 MADDR_R FUNCTION To read the value of a register in MREG1 or MREG2 space, set this register field to the address of the register in MREG1 or MREG2 space. M_R Name: M_R Address: 126 (7Eh) Serial IF: R/W Reset value: 0x00 BIT NAME 7:0 M_R FUNCTION To read the value of a register in MREG1 or MREG2 space, that value is accessed from M_R. Page 71 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P USER BANK MREG1 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within user bank MREG1. The procedure for accessing MREG1 registers is described in section 12. TMST_CONFIG1 Name: TMST_CONFIG1 Address: 00 (00h) Serial IF: R/W Reset value: 0x02 BIT NAME 7:5 - 4 TMST_ON_SREG_EN 3 TMST_RES 2 TMST_DELTA_EN 1 TMST_FSYNC_EN 0 TMST_EN FUNCTION Reserved 0: TMST_FSYNCH and TMST_FSYNCL registers report the delta time from FSYNC to next ODR 1: TMST_FSYNCH and TMST_FSYNCL registers report: absolute timestamp when FSYNC even is not present; delta time from FSYNC to next ODR when FSYNC event is present Time Stamp resolution: When set to 0 (default), time stamp resolution is 1 µs. When set to 1, resolution is 16 µs Time Stamp delta enable: When set to 1, the time stamp field contains the measurement of time since the last occurrence of ODR. Time Stamp register FSYNC enable (default). When set to 1, the contents of the Timestamp feature of FSYNC is enabled. The user also needs to select FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the FIFO. 0: Time Stamp register disable 1: Time Stamp register enable Page 72 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO_CONFIG5 Name: FIFO_CONFIG5 Address: 01 (01h) Serial IF: R/W Reset value: 0x20 BIT NAME 7:6 - 5 FIFO_WM_GT_TH 4 FIFO_RESUME_PARTIAL_RD 3 FIFO_HIRES_EN 2 FIFO_TMST_FSYNC_EN 1 FIFO_GYRO_EN 0 FIFO_ACCEL_EN FUNCTION Reserved 0: Trigger FIFO Watermark interrupt when FIFO_COUNT = FIFO_WM 1: Trigger FIFO Watermark interrupt on every ODR if FIFO_COUNT = FIFO_WM 0: FIFO is read in packets. If a partial packet is read, then the subsequent read will start from the beginning of the un-read packet. 1: FIFO can be read partially. When read is resumed, FIFO bytes will continue from last read point. The SW driver is responsible for cascading previous read and present read and for maintaining frame boundaries. 0: 20-bit resolution not enabled in the FIFO packet readout 1: 20-bit resolution enabled in the FIFO packet readout 0: TMST in the FIFO cannot be replaced by the FSYNC timestamp 1: Allows the TMST in the FIFO to be replaced by the FSYNC timestamp 0: Gyro packets not enabled to go to FIFO 1: Enables Gyro packets to go to FIFO 0: Accel packets not enabled to go to FIFO 1: Enables Accel packets to go to FIFO Page 73 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FIFO_CONFIG6 Name: FIFO_CONFIG6 Address: 02 (02h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:5 4 3:1 0 FUNCTION - Reserved FIFO_EMPTY_INDICATOR_DIS 0: 0xFF is sent out as FIFO data when FIFO is empty. 1: The last FIFO data is sent out when FIFO is empty. - Reserved RCOSC_REQ_ON_FIFO_THS_DIS 0: When the FIFO is operating in ALP+WUOSC mode and the watermark (WM) interrupt is enabled, the FIFO wakes up the system oscillator (RCOSC) as soon as the watermark level is reached. The system oscillator remains enabled until a Host FIFO read operation happens. This will temporarily cause a small increase in the power consumption due to the enabling of the system oscillator. 1: The system oscillator is not automatically woken-up by the FIFO/INT when the WM interrupt is triggered. The side effect is that the host can receive invalid packets until the system oscillator is off after it has been turned on for other reasons not related to a WM interrupt. The recommended setting of this bit is ‘1’ before entering and during all power modes excluding ALP with WUOSC. This is in order to avoid having to do a FIFO access/flush before entering sleep mode. During ALP with WUOSC it is recommended to set this bit to ‘0’. It is recommended to reset this bit back to ‘1’ before exiting ALP+WUOSC with a wait time of 1 ODR or higher. Page 74 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P FSYNC_CONFIG Name: FSYNC_CONFIG Address: 03 (03h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 - 6:4 FSYNC_UI_SEL 3:2 - 1 FSYNC_UI_FLAG_CLEAR_SEL 0 FSYNC_POLARITY FUNCTION Reserved 000: Do not tag FSYNC flag 001: Tag FSYNC flag to TEMP_OUT LSB 010: Tag FSYNC flag to GYRO_XOUT LSB 011: Tag FSYNC flag to GYRO_YOUT LSB 100: Tag FSYNC flag to GYRO_ZOUT LSB 101: Tag FSYNC flag to ACCEL_XOUT LSB 110: Tag FSYNC flag to ACCEL_YOUT LSB 111: Tag FSYNC flag to ACCEL_ZOUT LSB Reserved 0: FSYNC flag is cleared when UI sensor register is updated 1: FSYNC flag is cleared when UI interface reads the sensor register LSB of FSYNC tagged axis 0: Start from Rising edge of FSYNC pulse to measure FSYNC interval 1: Start from Falling edge of FSYNC pulse to measure FSYNC interval INT_CONFIG0 Name: INT_CONFIG0 Address: 04 (04h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:6 - 5:4 UI_DRDY_INT_CLEAR 3:2 FIFO_THS_INT_CLEAR 1:0 FIFO_FULL_INT_CLEAR FUNCTION Reserved Data Ready Interrupt Clear Option (latched mode) 00: Clear on Status Bit Read 01: Clear on Status Bit Read 10: Clear on Sensor Register Read 11: Clear on Status Bit Read OR on Sensor Register read FIFO Threshold Interrupt Clear Option (latched mode) 00: Clear on Status Bit Read 01: Clear on Status Bit Read 10: Clear on FIFO data 1Byte Read 11: Clear on Status Bit Read OR on FIFO data 1 byte read FIFO Full Interrupt Clear Option (latched mode) 00: Clear on Status Bit Read 01: Clear on Status Bit Read 10: Clear on FIFO data 1Byte Read 11: Clear on Status Bit Read OR on FIFO data 1 byte read Page 75 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_CONFIG1 Name: INT_CONFIG1 Address: 05 (05h) Serial IF: R/W Reset value: 0x10 BIT NAME 7 6 INT_TPULSE_DURATION 5 - 4 INT_ASYNC_RESET 3:0 - FUNCTION Reserved Interrupt pulse duration 0: Interrupt pulse duration is 100 µs 1: Interrupt pulse duration is 8 µs Reserved 0: The interrupt pulse is reset as soon as the interrupt status register is read if the pulse is still active. 1: The interrupt pulse remains high for the intended duration independent of when the interrupt status register is read. This is the default and recommended setting. In this case, when in ALP with the WUOSC clock, the clearing of the interrupt status register requires up to one ODR period after reading. Reserved SENSOR_CONFIG3 Name: SENSOR_CONFIG3 Address: 06 (06h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 6 APEX_DISABLE 5:0 - FUNCTION Reserved 1: Disable APEX features to extend FIFO size to 2.25 Kbytes Reserved Page 76 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P ST_CONFIG Name: ST_CONFIG Address: 19 (13h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 - 6 FUNCTION Reserved This bit selects the number of sensor samples that should be used to process self-test ST_NUMBER_SAMPLE 0: 16 samples 1: 200 samples These bits control the tolerated ratio between self-test processed values and reference (fused) ones for accelerometer 5:3 ACCEL_ST_LIM 000 to 110: Reserved 111: 50% These bits control the tolerated ratio between self-test processed values and reference (fused) ones for gyroscope 2:0 GYRO_ST_LIM 000 to 110: Reserved 111: 50% Page 77 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P SELFTEST Name: SELFTEST Address: 20 (14h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 GYRO_ST_EN 6 ACCEL_ST_EN 5:0 - FUNCTION 1: Enable gyro self-test operation. Host needs to program this bit to 0 to move device out of self-test mode. If host programs this bit to 0 while ST_BUSY = 1 and ST_DONE = 0, the current running self-test operation is terminated by host. 1: Enable accel self-test operation. Host needs to program this bit to 0 to move device out of self-test mode. If host programs this bit to 0 while ST_BUSY = 1 and ST_DONE = 0, the current running self-test operation is terminated by host. Reserved INTF_CONFIG6 Name: INTF_CONFIG6 Address: 35 (23h) Serial IF: R/W Reset value: 0x7C BIT NAME 7:5 4 I3C_TIMEOUT_EN 3 I3C_IBI_BYTE_EN 2 I3C_IBI_EN 1:0 - FUNCTION Reserved 0: I2C/I3CSM timeout function not enabled 1: I2C/I3CSM timeout function enabled 0: I3CSM IBI payload function not enabled 1: I3CSM IBI payload function enabled 0: I3CSM IBI function not enabled 1: I3CSM IBI function enabled Reserved INTF_CONFIG10 Name: INTF_CONFIG10 Address: 37 (25h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 6:0 ASYNCTIME0_DIS - FUNCTION 0: I3CSMAsynchronous Mode 0 timing control is enabled 1: I3CSM Asynchronous Mode 0 timing control is disabled Reserved Page 78 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INTF_CONFIG7 Name: INTF_CONFIG7 Address: 40 (28h) Serial IF: R/W Reset value: 0x0C BIT NAME 7:4 - 3 2:0 I3C_DDR_WR_MODE - FUNCTION Reserved This bit controls how I3CSM slave treats the 1st 2-byte data from host in a DDR write operation. 0: (a) The 1st-byte in DDR-WR configures the starting register address where the write operation should occur. (b) The 2nd-byte in DDR-WR is ignored and dropped. (c) The 3rd-byte in DDR-WR will be written into the register with address specified by the 1st-byte. Or, the next DDR-RD will be starting from the address specified by the 1st-byte of previous DDR-WR. 1: (a) The 1st-byte in DDR-WR configures the starting register address where the write operation should occur. (b) The 2nd-byte in DDR-WR will be written into the register with address specified by the 1st-byte. Reserved OTP_CONFIG Name: OTP_CONFIG Address: 43 (2Bh) Serial IF: R/W Reset value: 0x06 BIT NAME 7:4 3:2 OTP_COPY_MODE 1:0 - FUNCTION Reserved 00: Reserved 01: Enable copying OTP block to SRAM 10: Reserved 11: Enable copying self-test data from OTP memory to SRAM Reserved Page 79 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_SOURCE6 Name: INT_SOURCE6 Address: 47 (2Fh) Serial IF: R/W Reset value: 0x00 BIT NAME 7 FF_INT1_EN 6 LOWG_INT1_EN 5 STEP_DET_INT1_EN 4 STEP_CNT_OFL_INT1_EN 3 TILT_DET_INT1_EN 2:0 - FUNCTION 0: Freefall interrupt not routed to INT1 1: Freefall interrupt routed to INT1 0: Low-g interrupt not routed to INT1 1: Low-g interrupt routed to INT1 0: Step detect interrupt not routed to INT1 1: Step detect interrupt routed to INT1 0: Step count overflow interrupt not routed to INT1 1: Step count overflow interrupt routed to INT1 0: Tilt detect interrupt not routed to INT1 1: Tile detect interrupt routed to INT1 Reserved INT_SOURCE7 Name: INT_SOURCE7 Address: 48 (30h) Serial IF: R/W Reset value: 0x00 BIT NAME 7 FF_INT2_EN 6 LOWG_ INT2_EN 5 STEP_DET_INT2_EN 4 STEP_CNT_OFL_INT2_EN 3 TILT_DET_INT2_EN 2:0 - FUNCTION 0: Freefall interrupt not routed to INT2 1: Freefall interrupt routed to INT2 0: Low-g interrupt not routed to INT2 1: Low-g interrupt routed to INT2 0: Step detect interrupt not routed to INT2 1: Step detect interrupt routed to INT2 0: Step count overflow interrupt not routed to INT2 1: Step count overflow interrupt routed to INT2 0: Tilt detect interrupt not routed to INT2 1: Tile detect interrupt routed to INT2 Reserved Page 80 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_SOURCE8 Name: INT_SOURCE8 Address: 49 (31h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:6 5 FSYNC_IBI_EN 4 PLL_RDY_IBI_EN 3 UI_DRDY_IBI_EN 2 FIFO_THS_IBI_EN 1 FIFO_FULL_IBI_EN 0 AGC_RDY_IBI_EN FUNCTION Reserved 0: FSYNC interrupt not routed to IBI 1: FSYNC interrupt routed to IBI 0: PLL ready interrupt not routed to IBI 1: PLL ready interrupt routed to IBI 0: UI data ready interrupt not routed to IBI 1: UI data ready interrupt routed to IBI 0: FIFO threshold interrupt not routed to IBI 1: FIFO threshold interrupt routed to IBI 0: FIFO full interrupt not routed to IBI 1: FIFO full interrupt routed to IBI 0: AGC ready interrupt not routed to IBI 1: AGC ready interrupt routed to IBI INT_SOURCE9 Name: INT_SOURCE9 Address: 50 (32h) Serial IF: R/W Reset value: 0x00 BIT NAME I3C_PROTOCOL_ERROR_IBI 7 _EN 6 FF_IBI_EN 5 LOWG_IBI_EN 4 SMD_IBI_EN 3 WOM_Z_IBI_EN 2 WOM_Y_IBI_EN 1 WOM_X_IBI_EN 0 ST_DONE_IBI_EN FUNCTION 0: I3C protocol error interrupt not routed to IBI 1: I3CSM protocol error interrupt routed to IBI 0: Freefall interrupt not routed to IBI 1: Freefall interrupt routed to IBI 0: Low-g interrupt not routed to IBI 1: Low-g interrupt routed to IBI 0: SMD interrupt not routed to IBI 1: SMD interrupt routed to IBI 0: Z-axis WOM interrupt not routed to IBI 1: Z-axis WOM interrupt routed to IBI 0: Y-axis WOM interrupt not routed to IBI 1: Y-axis WOM interrupt routed to IBI 0: X-axis WOM interrupt not routed to IBI 1: X-axis WOM interrupt routed to IBI 0: Self-test done interrupt not routed to IBI 1: Self-test done interrupt routed to IBI SM Page 81 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P INT_SOURCE10 Name: INT_SOURCE10 Address: 51 (33h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:6 5 STEP_DET_IBI_EN 4 STEP_CNT_OFL_IBI_EN 3 TILT_DET_IBI_EN 2:0 - FUNCTION Reserved 0: Step detect interrupt not routed to IBI 1: Step detect interrupt routed to IBI 0: Step count overflow interrupt not routed to IBI 1: Step count overflow interrupt routed to IBI 0: Tilt detect interrupt not routed to IBI 1: Tile detect interrupt routed to IBI Reserved Page 82 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_CONFIG2 Name: APEX_CONFIG2 Address: 68 (44h) Serial IF: R/W Reset value: 0xA2 BIT NAME 7:4 3:0 LOW_ENERGY_AMP_TH_S EL DMP_POWER_SAVE_TIME _SEL FUNCTION Threshold to select a valid step. Used to increase step detection for slow walk use case. 0000: 30 mg 0001: 35 mg 0010: 40 mg 0011: 45 mg 0100: 50 mg 0101: 55 mg 0110: 60 mg 0111: 65 mg 1000: 70 mg 1001: 75 mg 1010: 80 mg (default) 1011: 85 mg 1100: 90 mg 1101: 95 mg 1110: 100 mg 1111: 105 mg Duration of the period while the DMP stays awake after receiving a WOM event. 0000: 0 seconds 0001: 4 seconds 0010: 8 seconds (default) 0011: 12 seconds 0100: 16 seconds 0101: 20 seconds 0110: 24 seconds 0111: 28 seconds 1000: 32 seconds 1001: 36 seconds 1010: 40 seconds 1011: 44 seconds 1100: 48 seconds 1101: 52 seconds 1110: 56 seconds 1111: 60 seconds Page 83 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_CONFIG3 Name: APEX_CONFIG3 Address: 69 (45h) Serial IF: R/W Reset value: 0x85 BIT NAME FUNCTION Threshold of step detection sensitivity. Low values increase detection sensitivity: reduce miss-detection. High values reduce detection sensitivity: reduce false-positive. 7:4 PED_AMP_TH_SEL 0000: 30 mg 0001: 34 mg 0010: 38 mg 0011: 42 mg 0100: 46 mg 0101: 50 mg 0110: 54 mg 0111: 58 mg 1000: 62 mg (default) 1001: 66 mg 1010: 70 mg 1011: 74 mg 1100: 78 mg 1101: 82 mg 1110: 86 mg 1111: 90 mg Minimum number of steps that must be detected before step count is incremented. Low values reduce latency but increase false positives. High values increase step count accuracy but increase latency. 3:0 PED_STEP_CNT_TH_SEL 0000: 0 steps 0001: 1 step 0010: 2 steps 0011: 3 steps 0100: 4 steps 0101: 5 steps (default) 0110: 6 steps 0111: 7 steps 1000: 8 steps 1001: 9 steps 1010: 10 steps 1011: 11 steps 1100: 12 steps 1101: 13 steps 1110: 14 steps 1111: 15 steps Page 84 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_CONFIG4 Name: APEX_CONFIG4 Address: 70 (46h) Serial IF: R/W Reset value: 0x51 BIT NAME FUNCTION Minimum number of steps that must be detected before step event is signaled. Low values reduce latency but increase false positives. High values increase step event validity but increase latency. 7:5 4:2 PED_STEP_DET_TH_SEL PED_SB_TIMER_TH_SEL 000: 0 steps 001: 1 step 010: 2 steps (default) 011: 3 steps 100: 4 steps 101: 5 steps 110: 6 steps 111: 7 steps Duration before algorithm considers that user has stopped taking steps. 000: 50 samples 001: 75 sample 010: 100 samples 011: 125 samples 100: 150 samples (default) 101: 175 samples 110: 200 samples 111: 225 samples Threshold to classify acceleration signal as motion not due to steps. High values improve vibration rejection. Low values improve detection. 1:0 PED_HI_EN_TH_SEL 00: 87.89 mg 01: 104.49 mg (default) 10: 132.81 mg 11: 155.27 mg Page 85 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_CONFIG5 Name: APEX_CONFIG5 Address: 71 (47h) Serial IF: R/W Reset value: 0x80 BIT NAME 7:6 5:3 2:0 TILT_WAIT_TIME_SEL LOWG_PEAK_TH_HYST_SEL HIGHG_PEAK_TH_HYST_SEL FUNCTION Minimum duration for which the device should be tilted before signaling event. 00: 0s 01: 2s 10: 4s (default) 11: 6s Hysteresis value added to the low-g threshold after exceeding it. 000: 31 mg (default) 001: 63 mg 010: 94 mg 011: 125 mg 100: 156 mg 101: 188 mg 110: 219 mg 111: 250 mg Hysteresis value subtracted from the high-g threshold after exceeding it. 000: 31 mg (default) 001: 63 mg 010: 94 mg 011: 125 mg 100: 156 mg 101: 188 mg 110: 219 mg 111: 250 mg Page 86 of 102 Document Number: DS-000451 Revision: 1.0 ICM-42670-P APEX_CONFIG9 Name: APEX_CONFIG9 Address: 72 (48h) Serial IF: R/W Reset value: 0x00 BIT NAME 7:4 FF_DEBOUNCE_DURATION_ SEL 3:1 SMD_SENSITIVITY_SEL 0 SENSITIVITY_MODE FUNCTION Period after a freefall is signaled during which a new freefall will not be detected. Prevents false detection due to bounces. 0000: 0 ms 0001: 1250 ms 0010: 1375 ms 0011: 1500 ms 0100: 1625 ms 0101: 1750 ms 0110: 1875 ms 0111: 2000 ms 1000: 2125 ms (default) 1001: 2250 ms 1010: 2375 ms 1011: 2500 ms 1100: 2625 ms 1101: 2750 ms 1110: 2875 ms 1111: 3000 ms Parameter to tune SMD algorithm robustness to rejection, ranging from 0 to 4 (values higher than 4 are reserved). Low values increase detection rate but increase false positives. High values reduce false positives but reduce detection rate (especially for transport use cases). Default value is 0. Pedometer sensitivity mode 0: Normal (default) 1: Slow walk Slow walk mode improves slow walk detection (