IIM-42652

IIM-42652 Datasheet High-performance 6-Axis SmartIndustrial™ MotionTracking MEMS Device for Industrial Applications GENERAL DESCRIPTION APPLICATIONS The IIM-42652 is a 6-axis SmartIndustrial™ MotionTracking device that supports an extended operating temperature range. The IIM-42652 combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 2.5 mm x 3 mm x 0.91 mm (14-pin LGA) package. It also features a 2 KB FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. IIM-42652 supports highly accurate external clock input to reduce system level sensitivity error, improve orientation measurement from gyroscope data and to reduce ODR sensitivity to temperature and device to device variation. The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I2C interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz. The device features an operating voltage range from 3.6V down to 1.71V. ORDERING INFORMATION PART NUMBER IIM-42652† TEMPERATURE PACKAGE −40°C to +105°C 14-pin LGA • • • • • Navigation Orientation measurement Tilt sensing Platform stabilization Robotics FEATURES • • • • • • • • • • Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec Digital-output X-, Y-, and Z-axis accelerometer with programmable fullscale range of ±2g, ±4g, ±8g and ±16g User-programmable interrupts I3CSM / I2C / SPI slave host interface Digital-output temperature sensor Small and thin package: 2.5 mm x 3 mm x 0.91 mm (14-pin LGA) 20,000 g shock tolerant MEMS structure hermetically sealed and bonded at wafer level MEMS structure hermetically sealed and bonded at wafer level RoHS and Green compliant TYPICAL OPERATING CIRCUIT AP_SDO RESV RESV INT1 / INT 14 AP_CS AP_SCLK AP_SDIO / AP_SDI †Denotes RoHS and Green-compliant package 13 12 11 1 2 10 ICM-42605 IIM-42652 3 4 9 8 5 6 RESV RESV INT2 / FSYNC / CLKIN VDD 7 RESV GND VDDIO C1, 0.1 µF 1.71 – 3.6VDC C3, 10 nF Application Schematic (SPI Interface to Host) InvenSense, Inc. reserves the right to change specifications and information herein without notice unless the product is in mass production and the datasheet has been designated by InvenSense in writing as subject to a specified Product / Process Change Notification Method regulation. InvenSense, a TDK Group Company 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 invensense.tdk.com Document Number: DS-000401 Revision: 1.2 Release Date: 10/01/2021 1.71 – 3.6VDC C2, 2.2 µF IIM-42652 TABLE OF CONTENTS General Description ............................................................................................................................................. 1 Ordering Information .......................................................................................................................................... 1 Applications ......................................................................................................................................................... 1 Features ............................................................................................................................................................... 1 Typical Operating Circuit ..................................................................................................................................... 1 1 Introduction .......................................................................................................................................................... 9 Purpose and Scope ................................................................................................................................... 9 Product Overview ..................................................................................................................................... 9 Applications .............................................................................................................................................. 9 2 Features .............................................................................................................................................................. 10 Gyroscope Features ................................................................................................................................ 10 Accelerometer Features ......................................................................................................................... 10 Motion Features ..................................................................................................................................... 10 Additional Features................................................................................................................................. 10 3 Electrical Characteristics..................................................................................................................................... 11 Gyroscope Specifications ........................................................................................................................ 11 Accelerometer Specifications ................................................................................................................. 12 Electrical Specifications .......................................................................................................................... 13 I2C Timing Characterization .................................................................................................................... 15 SPI Timing Characterization – 4-Wire SPI Mode ..................................................................................... 16 SPI Timing Characterization – 3-Wire SPI Mode ..................................................................................... 17 RTC (CLKIN) Timing Characterization ...................................................................................................... 18 Absolute Maximum Ratings .................................................................................................................... 19 4 Applications Information .................................................................................................................................... 20 Pin Out Diagram and Signal Description ................................................................................................. 20 Typical Operating Circuit......................................................................................................................... 21 Bill of Materials for External Components .............................................................................................. 22 System Block Diagram ............................................................................................................................ 22 Overview ................................................................................................................................................. 23 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 23 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ........................................ 23 I3CSM, I2C, and SPI Host Interface ............................................................................................................ 23 Self-Test .................................................................................................................................................. 23 Clocking .............................................................................................................................................. 24 Sensor Data Registers ......................................................................................................................... 24 Interrupts............................................................................................................................................ 24 Document Number: DS-000401 Revision: 1.2 Page 2 of 119 IIM-42652 Digital-Output Temperature Sensor ................................................................................................... 24 Bias and LDOs ..................................................................................................................................... 25 Charge Pump ...................................................................................................................................... 25 Standard Power Modes ...................................................................................................................... 25 5 Signal Path .......................................................................................................................................................... 26 Summary of Parameters Used to Configure the Signal Path .................................................................. 26 Notch Filter ............................................................................................................................................. 26 Anti-Alias Filter ....................................................................................................................................... 28 User Programmable Offset ..................................................................................................................... 30 UI Filter Block .......................................................................................................................................... 30 ODR And FSR Selection ........................................................................................................................... 36 6 FIFO..................................................................................................................................................................... 38 Packet Structure ..................................................................................................................................... 38 FIFO Header ............................................................................................................................................ 40 Maximum FIFO Storage .......................................................................................................................... 41 FIFO Configuration Registers .................................................................................................................. 41 7 Programmable Interrupts ................................................................................................................................... 43 8 APEX Motion Functions ...................................................................................................................................... 44 APEX ODR Support .................................................................................................................................. 44 DMP Power Save Mode .......................................................................................................................... 45 Pedometer Programming ....................................................................................................................... 45 Tilt Detection Programming.................................................................................................................... 46 Freefall Detection Programming............................................................................................................. 47 Tap Detection Programming ................................................................................................................... 48 Wake on Motion Programming .............................................................................................................. 48 Significant Motion Detection Programming ........................................................................................... 49 9 Digital Interface .................................................................................................................................................. 51 I3CSM, I2C, and SPI Serial Interfaces ......................................................................................................... 51 I3CSM Interface ........................................................................................................................................ 51 I2C Interface ............................................................................................................................................ 51 I2C Communications Protocol ................................................................................................................. 51 I2C Terms ................................................................................................................................................. 54 SPI Interface ............................................................................................................................................ 54 10 Assembly ............................................................................................................................................................ 56 Orientation of Axes ............................................................................................................................ 56 Package Dimensions ........................................................................................................................... 57 11 Part Number Package Marking ........................................................................................................................... 59 Document Number: DS-000401 Revision: 1.2 Page 3 of 119 IIM-42652 12 Use Notes ........................................................................................................................................................... 60 Accelerometer Mode Transitions ....................................................................................................... 60 Accelerometer Low Power (LP) Mode Averaging Filter Setting ......................................................... 60 Settings for I2C, I3CSM, and SPI Operation........................................................................................... 60 Notch Filter and Anti-Alias Filter Operation ....................................................................................... 60 external clock input effect on odr ...................................................................................................... 60 INT_ASYNC_RESET Configuration ....................................................................................................... 61 FIFO Timestamp Interval Scaling ........................................................................................................ 61 Supplementary Information for FIFO_HOLD_LAST_DATA_EN ........................................................... 61 Register Values Modification.............................................................................................................. 63 13 Register Map ...................................................................................................................................................... 64 User Bank 0 Register Map .................................................................................................................. 64 User Bank 1 Register Map .................................................................................................................. 65 User Bank 2 Register Map .................................................................................................................. 66 User Bank 3 Register Map .................................................................................................................. 66 User Bank 4 Register Map .................................................................................................................. 66 Register Values Modification.............................................................................................................. 67 14 User Bank 0 Register Map – Descriptions........................................................................................................... 68 DEVICE_CONFIG ................................................................................................................................. 68 DRIVE_CONFIG ................................................................................................................................... 68 INT_CONFIG........................................................................................................................................ 69 FIFO_CONFIG ...................................................................................................................................... 69 TEMP_DATA1 ..................................................................................................................................... 69 TEMP_DATA0 ..................................................................................................................................... 70 ACCEL_DATA_X1................................................................................................................................. 70 ACCEL_DATA_X0................................................................................................................................. 70 ACCEL_DATA_Y1 ................................................................................................................................. 70 ACCEL_DATA_Y0 ................................................................................................................................. 71 ACCEL_DATA_Z1 ................................................................................................................................. 71 ACCEL_DATA_Z0 ................................................................................................................................. 71 GYRO_DATA_X1.................................................................................................................................. 71 GYRO_DATA_X0.................................................................................................................................. 71 GYRO_DATA_Y1 .................................................................................................................................. 72 GYRO_DATA_Y0 .................................................................................................................................. 72 GYRO_DATA_Z1 .................................................................................................................................. 72 GYRO_DATA_Z0 .................................................................................................................................. 72 TMST_FSYNCH .................................................................................................................................... 72 Document Number: DS-000401 Revision: 1.2 Page 4 of 119 IIM-42652 TMST_FSYNCL ..................................................................................................................................... 73 INT_STATUS ........................................................................................................................................ 73 FIFO_COUNTH .................................................................................................................................... 73 FIFO_COUNTL ..................................................................................................................................... 74 FIFO_DATA.......................................................................................................................................... 74 APEX_DATA0 ...................................................................................................................................... 74 APEX_DATA1 ...................................................................................................................................... 74 APEX_DATA2 ...................................................................................................................................... 75 APEX_DATA3 ...................................................................................................................................... 75 APEX_DATA4 ...................................................................................................................................... 76 APEX_DATA5 ...................................................................................................................................... 76 INT_STATUS2 ...................................................................................................................................... 77 INT_STATUS3 ...................................................................................................................................... 77 SIGNAL_PATH_RESET ......................................................................................................................... 77 INTF_CONFIG0 .................................................................................................................................... 78 INTF_CONFIG1 .................................................................................................................................... 79 PWR_MGMT0 ..................................................................................................................................... 80 GYRO_CONFIG0 .................................................................................................................................. 81 ACCEL_CONFIG0 ................................................................................................................................. 82 GYRO_CONFIG1 .................................................................................................................................. 83 GYRO_ACCEL_CONFIG0 ...................................................................................................................... 84 ACCEL_CONFIG1 ................................................................................................................................. 85 TMST_CONFIG .................................................................................................................................... 85 APEX_CONFIG0 ................................................................................................................................... 86 SMD_CONFIG ..................................................................................................................................... 86 FIFO_CONFIG1 .................................................................................................................................... 87 FIFO_CONFIG2 .................................................................................................................................... 87 FIFO_CONFIG3 .................................................................................................................................... 87 FSYNC_CONFIG ................................................................................................................................... 88 INT_CONFIG0...................................................................................................................................... 88 INT_CONFIG1...................................................................................................................................... 89 INT_SOURCE0 ..................................................................................................................................... 89 INT_SOURCE1 ..................................................................................................................................... 90 INT_SOURCE3 ..................................................................................................................................... 90 INT_SOURCE4 ..................................................................................................................................... 91 FIFO_LOST_PKT0 ................................................................................................................................ 91 FIFO_LOST_PKT1 ................................................................................................................................ 91 Document Number: DS-000401 Revision: 1.2 Page 5 of 119 IIM-42652 SELF_TEST_CONFIG ............................................................................................................................ 92 WHO_AM_I ........................................................................................................................................ 92 REG_BANK_SEL ................................................................................................................................... 92 15 User Bank 1 Register Map – Descriptions........................................................................................................... 93 SENSOR_CONFIG0 .............................................................................................................................. 93 GYRO_CONFIG_STATIC2 ..................................................................................................................... 93 GYRO_CONFIG_STATIC3 ..................................................................................................................... 93 GYRO_CONFIG_STATIC4 ..................................................................................................................... 94 GYRO_CONFIG_STATIC5 ..................................................................................................................... 94 GYRO_CONFIG_STATIC6 ..................................................................................................................... 94 GYRO_CONFIG_STATIC7 ..................................................................................................................... 94 GYRO_CONFIG_STATIC8 ..................................................................................................................... 95 GYRO_CONFIG_STATIC9 ..................................................................................................................... 95 GYRO_CONFIG_STATIC10 ................................................................................................................... 95 XG_ST_DATA....................................................................................................................................... 96 YG_ST_DATA....................................................................................................................................... 96 ZG_ST_DATA ....................................................................................................................................... 96 TMSTVAL0 .......................................................................................................................................... 96 TMSTVAL1 .......................................................................................................................................... 97 TMSTVAL2 .......................................................................................................................................... 97 INTF_CONFIG4 .................................................................................................................................... 97 INTF_CONFIG5 .................................................................................................................................... 98 INTF_CONFIG6 .................................................................................................................................... 98 16 User Bank 2 Register Map – Descriptions........................................................................................................... 99 ACCEL_CONFIG_STATIC2 .................................................................................................................... 99 ACCEL_CONFIG_STATIC3 .................................................................................................................... 99 ACCEL_CONFIG_STATIC4 .................................................................................................................... 99 XA_ST_DATA ....................................................................................................................................... 99 YA_ST_DATA ..................................................................................................................................... 100 ZA_ST_DATA ..................................................................................................................................... 100 17 User Bank 3 Register Map – Descriptions......................................................................................................... 101 PU_PD_CONFIG1 .............................................................................................................................. 101 PU_PD_CONFIG2 .............................................................................................................................. 102 18 User Bank 4 Register Map – Descriptions......................................................................................................... 103 FDR_CONFIG ..................................................................................................................................... 103 APEX_CONFIG1 ................................................................................................................................. 103 APEX_CONFIG2 ................................................................................................................................. 104 Document Number: DS-000401 Revision: 1.2 Page 6 of 119 IIM-42652 APEX_CONFIG3 ................................................................................................................................. 105 APEX_CONFIG4 ................................................................................................................................. 106 APEX_CONFIG5 ................................................................................................................................. 107 APEX_CONFIG6 ................................................................................................................................. 108 APEX_CONFIG7 ................................................................................................................................. 109 APEX_CONFIG8 ................................................................................................................................. 109 APEX_CONFIG9 ................................................................................................................................. 109 APEX_CONFIG10 ............................................................................................................................... 110 ACCEL_WOM_X_THR........................................................................................................................ 110 ACCEL_WOM_Y_THR ........................................................................................................................ 111 ACCEL_WOM_Z_THR ........................................................................................................................ 111 INT_SOURCE6 ................................................................................................................................... 111 INT_SOURCE7 ................................................................................................................................... 112 INT_SOURCE8 ................................................................................................................................... 112 INT_SOURCE9 ................................................................................................................................... 113 INT_SOURCE10 ................................................................................................................................. 113 OFFSET_USER0 ................................................................................................................................. 114 OFFSET_USER1 ................................................................................................................................. 114 OFFSET_USER2 ................................................................................................................................. 114 OFFSET_USER3 ................................................................................................................................. 114 OFFSET_USER4 ................................................................................................................................. 115 OFFSET_USER5 ................................................................................................................................. 115 OFFSET_USER6 ................................................................................................................................. 115 OFFSET_USER7 ................................................................................................................................. 115 OFFSET_USER8 ................................................................................................................................. 116 19 Reference ......................................................................................................................................................... 117 20 Revision History ................................................................................................................................................ 118 Document Number: DS-000401 Revision: 1.2 Page 7 of 119 IIM-42652 Table of Figures Figure 1. I2C Bus Timing Diagram ...................................................................................................................................... 15 Figure 2. 4-Wire SPI Bus Timing Diagram ......................................................................................................................... 16 Figure 3. 3-Wire SPI Bus Timing Diagram ......................................................................................................................... 17 Figure 4. RTC Timing Diagram........................................................................................................................................... 18 Figure 5. Pin Out Diagram for IIM-42652 2.5 mm x 3.0 mm x 0.91 mm LGA ................................................................... 21 Figure 6. IIM-42652 Application Schematic (I3CSM / I2C Interface to Host) ...................................................................... 21 Figure 7. IIM-42652 Application Schematic (SPI Interface to Host).................................................................................. 22 Figure 8. IIM-42652 System Block Diagram ...................................................................................................................... 22 Figure 9. IIM-42652 Signal Path ........................................................................................................................................ 26 Figure 10. FIFO Packet Structure ...................................................................................................................................... 38 Figure 11. Maximum FIFO Storage ................................................................................................................................... 41 Figure 12. START and STOP Conditions ............................................................................................................................ 52 Figure 13. Acknowledge on the I2C Bus ............................................................................................................................ 52 Figure 14. Complete I2C Data Transfer ............................................................................................................................. 53 Figure 15. Typical SPI Master/Slave Configuration ........................................................................................................... 55 Figure 16. Orientation of Axes of Sensitivity and Polarity of Rotation ............................................................................. 56 Figure 17. Package Dimensions ........................................................................................................................................ 57 Figure 18. Part Number Package Marking ........................................................................................................................ 59 Table of Tables Table 1. Gyroscope Specifications .................................................................................................................................... 11 Table 2. Accelerometer Specifications............................................................................................................................. 12 Table 3. D.C. Electrical Characteristics .............................................................................................................................. 13 Table 4. A.C. Electrical Characteristics .............................................................................................................................. 14 Table 5. I2C Timing Characteristics.................................................................................................................................... 15 Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) ...................................................................................... 16 Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) ...................................................................................... 17 Table 8. RTC Timing Characteristics .................................................................................................................................. 18 Table 9. Absolute Maximum Ratings ................................................................................................................................ 19 Table 10. Signal Descriptions ............................................................................................................................................ 20 Table 11. Bill of Materials ................................................................................................................................................. 22 Table 12. Standard Power Modes for IIM-42652 ............................................................................................................. 25 Table 13. Signal path parameters ..................................................................................................................................... 26 Table 14. I2C Terms ........................................................................................................................................................... 54 Document Number: DS-000401 Revision: 1.2 Page 8 of 119 IIM-42652 1 INTRODUCTION PURPOSE AND SCOPE This document is a product specification, providing a description, specifications, and design related information on the IIM-42652 SmartIndustrial™ device. The device is housed in a small 2.5 mm x 3 mm x 0.91 mm 14-pin LGA package. PRODUCT OVERVIEW The IIM-42652 is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 2.5 mm x 3 mm x 0.91 mm (14-pin LGA) package. It also features a 2 KB FIFO that can lower the traffic on the serial bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. IIM-42652, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for customers. The gyroscope supports eight programmable full-scale range settings from ±15.625 dps to ±2000 dps, and the accelerometer supports four programmable full-scale range settings from ±2g to ±16g. IIM-42652 also supports external clock input for highly accurate 31 kHz to 50 kHz clocks to reduce system level sensitivity error and reduce ODR sensitivity to temperature and device to device variation. Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I3CSM, I2C, and SPI serial interfaces; a VDD operating range of 1.71V to 3.6V; and a separate VDDIO operating range of 1.71V to 3.6V. The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface supports speeds up to 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), the I2C interface supports speeds up to 1 MHz, and the SPI interface supports speeds up to 24 MHz. IIM-42652 also supports external clock input for highly accurate 31 kHz to 50 kHz clocks to reduce system level sensitivity error, improve orientation measurement from gyroscope data, and reduce ODR sensitivity to temperature and device to device variation. By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of 2.5 mm x 3 mm x 0.91 mm (14-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness by supporting 20,000g shock reliability. APPLICATIONS • • • • • Navigation Orientation measurement Tilt sensing Platform stabilization Robotics Document Number: DS-000401 Revision: 1.2 Page 9 of 119 IIM-42652 2 FEATURES GYROSCOPE FEATURES The triple-axis MEMS gyroscope in the IIM-42652 includes a wide range of features: • • • • • Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with programmable full-scale range of ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec Low Noise (LN) power mode support Digitally-programmable low-pass filters Factory calibrated sensitivity scale factor Self-test ACCELEROMETER FEATURES The triple-axis MEMS accelerometer in IIM-42652 includes a wide range of features: • • • • • Digital-output X-, Y-, and Z-axis accelerometer with programmable full-scale range of ±2g, ±4g, ±8g and ±16g Low Noise (LN) and Low Power (LP) power modes support User-programmable interrupts Wake-on-motion interrupt for low power operation of applications processor Self-test MOTION FEATURES IIM-42652 includes the following motion features, also known as APEX (Advanced Pedometer and Event Detection – neXt gen) • • • • • • Pedometer: tracks step count, also issues step detect interrupt Tilt Detection: issues an interrupt when the tilt angle exceeds 35° for more than a programmable time Tap Detection: issues an interrupt when a tap is detected, along with the tap count Freefall Detection: triggers an interrupt when device freefall is detected and outputs freefall duration Wake on Motion: detects motion when accelerometer data exceeds a programmable threshold Significant Motion Detection: detects significant motion if wake on motion events are detected during a programmable time window ADDITIONAL FEATURES IIM-42652 includes the following additional features: • • • • • • • • • • External clock input supports highly accurate clock input from 31 kHz to 50 kHz, helps to reduce system level sensitivity error 2 KB FIFO buffer enables the applications processor to read the data in bursts User-programmable digital filters for gyroscope, accelerometer, and temperature sensor User configurable internal pull-up/pull-downs included on I/O interfaces to reduce system costs associated with external pull-ups/pull-downs 12.5 MHz I3CSM (data rates up to 12.5 Mbps in SDR mode, 25Mbps in DDR mode) / 1 MHz I2C / 24 MHz SPI slave host interface Digital-output temperature sensor Smallest and thinnest LGA package for Industrial IoT applications: 2.5 mm x 3 mm x 0.91 mm (14-pin LGA) 20,000g shock tolerant MEMS structure hermetically sealed and bonded at wafer level RoHS and Green compliant Document Number: DS-000401 Revision: 1.2 Page 10 of 119 IIM-42652 3 ELECTRICAL CHARACTERISTICS GYROSCOPE SPECIFICATIONS Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES ±2000 º/s ±1000 º/s 2 2 GYROSCOPE SENSITIVITY GYRO_FS_SEL=0 GYRO_FS_SEL =1 Full-Scale Range GYRO_FS_SEL =2 ±500 º/s 2 GYRO_FS_SEL =3 ±250 º/s 2 GYRO_FS_SEL =4 ±125 º/s 2 GYRO_FS_SEL =5 ±62.5 º/s 2 GYRO_FS_SEL =6 ±31.25 º/s 2 GYRO_FS_SEL =7 ±15.625 º/s 2 16 bits 2,6 GYRO_FS_SEL=0 GYRO_FS_SEL =1 16.4 LSB/(º/s) 2 32.8 LSB/(º/s) 2 GYRO_FS_SEL =2 65.5 LSB/(º/s) 2 GYRO_FS_SEL =3 131 LSB/(º/s) 2 GYRO_FS_SEL =4 262 LSB/(º/s) 2 GYRO_FS_SEL =5 524.3 LSB/(º/s) 2 GYRO_FS_SEL =6 1048.6 LSB/(º/s) 2 GYRO_FS_SEL =7 2097.2 LSB/(º/s) 2 Gyroscope ADC Word Length Sensitivity Scale Factor Sensitivity Scale Factor Initial Tolerance 25°C -1 ±0.5 +1 % 1, 5 Sensitivity Scale Factor Variation Over Temperature -40°C to +105°C -0.02 ±0.005 +0.02 %/ºC 3, 5 Nonlinearity Best fit straight line; 25°C -0.2 ±0.1 +0.2 % 3, 5 -3.0 ±1.25 +3.0 % 3, 5 Cross-Axis Sensitivity ZERO-RATE OUTPUT (ZRO) Initial ZRO Tolerance Board-level, 25°C ZRO Variation vs. Temperature -40°C to +105°C -3 ±0.5 +3 º/s 3, 5 -0.025 ±0.02 +0.025 º/s/ºC 3, 5 Rate Noise Spectral Density @ 10 Hz Total RMS Noise 0.0038 0.0052 º/s /√Hz 1, 5 Bandwidth = 100 Hz 0.038 0.052 º/s-rms 4, 5 27 29 KHz 1 500 Hz 2 3979 45 32000 Hz ms Hz 2 3, 5 2 OTHER PARAMETERS Gyroscope Mechanical Frequencies Low Pass Filter Response Gyroscope Start-Up Time Output Data Rate 25 ODR < 1 kHz 5 ODR ≥ 1 kHz Time from gyro enable to gyro drive ready 42 Table 1. Gyroscope Specifications Notes: 1. 2. 3. 4. 5. 6. Tested in production. Guaranteed by design. Derived from validation or characterization of parts, not tested in production. Calculated from Rate Noise Spectral Density. MIN/MAX or MAX specs are derived from characterization data based 3σ calculation. 20-bits data format supported in FIFO, see section 6.1. Document Number: DS-000401 Revision: 1.2 Page 11 of 119 12.5 30 IIM-42652 ACCELEROMETER SPECIFICATIONS Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES ACCELEROMETER SENSITIVITY Full-Scale Range ADC Word Length Sensitivity Scale Factor Sensitivity Scale Factor Initial Tolerance ACCEL_FS_SEL =0 ±16 g ACCEL_FS_SEL =1 ±8 g 2 2 ACCEL_FS_SEL =2 ±4 g 2 ACCEL_FS_SEL =3 ±2 g 2 Output in two’s complement format 16 bits 2, 6 ACCEL_FS_SEL =0 2,048 LSB/g 2 ACCEL_FS_SEL =1 4,096 LSB/g 2 ACCEL_FS_SEL =2 8,192 LSB/g 2 ACCEL_FS_SEL =3 Component-level 16,384 LSB/g 2 Sensitivity Change vs. Temperature -40°C to +105°C Nonlinearity Best Fit Straight Line, ±2g Cross-Axis Sensitivity -1 ±0.5 +1 % 1, 5 -0.025 ±0.005 +0.025 %/ºC 3, 5 -0.2 ±0.1 +0.2 % 3, 5 -2.0 ±1 +2.0 % 3, 5 ZERO-G OUTPUT Initial Tolerance Board-level, all axes Zero-G Level Change vs. Temperature -40°C to +105°C -30 ±20 +30 mg 3, 5 -0.40 ±0.15 +0.40 mg/ºC 3, 5 70 100 µg/√Hz 1, 5 0.70 1.00 mg-rms 4, 5 10 OTHER PARAMETERS Power Spectral Density @ 10 Hz RMS Noise Bandwidth = 100 Hz Low-Pass Filter Response Accelerometer Startup Time Output Data Rate ODR < 1 kHz 5 500 Hz 2 ODR ≥ 1 kHz From sleep mode to valid data 42 3979 20 32000 Hz ms Hz 2 3, 5 2 12.5 Table 2. Accelerometer Specifications Notes: 1. 2. 3. 4. 5. 6. Tested in production. Guaranteed by design. Derived from validation or characterization of parts, not tested in production. Calculated from Power Spectral Density. MIN/MAX or MAX specs are derived from characterization data based 3σ calculation. 20-bits data format supported in FIFO, see section 6.1. Document Number: DS-000401 Revision: 1.2 Page 12 of 119 IIM-42652 ELECTRICAL SPECIFICATIONS D.C. Electrical Characteristics Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES VDD 1.71 1.8 3.6 V 1 VDDIO 1.71 1.8 3.6 V 1 6-Axis Gyroscope + Accelerometer 0.88 0.95 mA 2, 3 3-Axis Accelerometer 0.28 0.35 mA 2, 3 3-Axis Gyroscope 0.73 0.85 mA 2, 3 Full-Chip Sleep Mode At 25ºC 7.5 10 µA 2, 3 Specified Temperature Range TEMPERATURE RANGE Performance parameters are not applicable beyond Specified Temperature Range +105 °C 2 SUPPLY VOLTAGES SUPPLY CURRENTS Low-Noise Mode -40 Table 3. D.C. Electrical Characteristics Notes: 1. 2. 3. Guaranteed by design. Derived from validation or characterization of parts, not tested in production. MIN/MAX or MAX specs are derived from characterization data based 3σ calculation. Document Number: DS-000401 Revision: 1.2 Page 13 of 119 IIM-42652 A.C. Electrical Characteristics Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN SUPPLIES Monotonic ramp. Ramp rate is 10% to 90% of the final value Supply Ramp Time Power Supply Noise Up to 10 kHz Operating Range 25°C Output ADC Resolution ODR Room Temperature Offset Stabilization Time Sensitivity Sensitivity for FIFO data Ambient Start-up time for register read/write From power-up 0.01 10 TEMPERATURE SENSOR With Filter 25°C -40 25 -5 Untrimmed 0 16 132.48 2.07 POWER-ON RESET I2C ADDRESS AP_AD0 = 0 AP_AD0 = 1 I2C ADDRESS TYP MAX UNITS 3 ms 50 mV peak-peak 105 2 3 2 2 3 2 1 1 1 ms 1 0.3*VDDIO V 8000 5 14000 V CI, Input Capacitance < 10 pF Input Leakage Current 100 nA DIGITAL OUTPUT (SDO, INT1, INT2) 0.9*VDDIO RLOAD=1 MΩ; VOL1, LOW-Level Output Voltage RLOAD=1 MΩ; VOL.INT, INT Low-Level Output Voltage Output Leakage Current OPEN=1, 0.3 mA sink Current OPEN=1 tINT, INT Pulse Width int_tpulse_duration= 0, 1 (100us, 8us ) ; V 100 µs -0.5 V 0.3*VDDIO V 0.7*VDDIO VDDIO + 0.5V V 0.1*VDDIO 3 mA sink current 0 VOL=0.4V VOL=0.6V Frequency Variation over Temperature 20+0.1Cb INTERNAL CLOCK SOURCE CLKSEL=`2b00 or gyro inactive; 25°C -3 CLK_SEL=`2b01 and gyro active; 25°C -1.5 V 1 mA mA 100 Cb bus capacitance in pf nA 300 ns +3 % 1 +1.5 % 1 CLK_SEL=`2b00 or gyro inactive; -40°C to +85°C ±3 % 1 CLK_SEL=`2b01 and gyro active; -40oC to +85oC ±2 % 1 Table 4. A.C. Electrical Characteristics Expected results based on design, will be updated after characterization. Not tested in production. Guaranteed by design. Production tested. Document Number: DS-000401 Revision: 1.2 V 0.4 3 6 Output Leakage Current Clock Frequency Initial Tolerance 1 nA 8 Vhys, Hysteresis Notes: 1. 2. 3. V 0.1 I2C I/O (SCL, SDA) VIH, HIGH-Level Input Voltage tof, Output Fall Time from VIHmax to VILmax 1 V 0.1*VDDIO 100 VIL, LOW-Level Input Voltage VOL, LOW-Level Output Voltage IOL, LOW-Level Output Current 1 1101000 1101001 VIL, Low Level Input Voltage VOH, High Level Output Voltage 1 °C LSB bits Hz °C µs LSB/°C LSB/°C DIGITAL INPUTS (FSYNC, SCLK, SDI, CS) 0.7*VDDIO VIH, High Level Input Voltage NOTES Page 14 of 119 IIM-42652 I2C TIMING CHARACTERIZATION Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Parameters Conditions I2C TIMING I2C FAST-MODE PLUS Min Typical fSCL, SCL Clock Frequency Max Units Notes 1 MHz 1 0.26 µs 1 tLOW, SCL Low Period 0.5 µs 1 tHIGH, SCL High Period 0.26 µs 1 tSU.STA, Repeated START Condition Setup Time tHD.STA, (Repeated) START Condition Hold Time 0.26 µs 1 tHD.DAT, SDA Data Hold Time 0 µs 1 tSU.DAT, SDA Data Setup Time 50 ns 1 tr, SDA and SCL Rise Time Cb bus cap. from 10 to 400 pF 120 ns 1 tf, SDA and SCL Fall Time Cb bus cap. from 10 to 400 pF 120 ns 1 tSU.STO, STOP Condition Setup Time 0.5 µs 1 tBUF, Bus Free Time Between STOP and START Condition 0.5 µs 1 Cb, Capacitive Load for each Bus Line pF 1 tVD.DAT, Data Valid Time < 400 0.45 µs 1 tVD.ACK, Data Valid Acknowledge Time 0.45 µs 1 Table 5. I2C Timing Characteristics Notes: 1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets tf SDA tSU.DAT tr 70% 30% 70% 30% tf SCL S SDA SCL tHD.STA tr 70% 30% tHD.DAT 1/fSCL tLOW 1st clock cycle tBUF tHD.STA tSU.STA Sr 70% 30% tSU.STO tVD.ACK 9th clock cycle Figure 1. I2C Bus Timing Diagram Document Number: DS-000401 Revision: 1.2 9th clock cycle tHIGH 70% 30% A continued below at tVD.DAT 70% 30% Page 15 of 119 P S A IIM-42652 SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETERS CONDITIONS MIN TYP MAX UNITS NOTES 24 SPI TIMING fSPC, SCLK Clock Frequency MHz 1 tLOW, SCLK Low Period Default 17 ns 1 tHIGH, SCLK High Period 17 ns 1 tSU.CS, CS Setup Time 39 ns 1 tHD.CS, CS Hold Time 18 ns 1 tSU.SDI, SDI Setup Time 13 ns 1 tHD.SDI, SDI Hold Time 8 ns 1 tVD.SDO, SDO Valid Time Cload = 20 pF tHD.SDO, SDO Hold Time Cload = 20 pF 21.5 3.5 28 tDIS.SDO, SDO Output Disable Time ns 1 ns 1 ns 1 Table 6. 4-Wire SPI Timing Characteristics (24-MHz Operation) Notes: 1. CS SCLK Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets 70% 30% tSU;CS SDI 70% 30% 70% 30% tHIGH tSU;SDI 1/fCLK tRise LSB IN MSB IN MSB OUT 70% 30% Page 16 of 119 tDIS;SDO tHD;SDO Figure 2. 4-Wire SPI Bus Timing Diagram Document Number: DS-000401 Revision: 1.2 tHD;CS tLOW tHD;SDI tVD;SDO SDO tFall LSB OUT IIM-42652 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETERS CONDITIONS MIN TYP MAX UNITS NOTES 24 SPI TIMING fSPC, SCLK Clock Frequency MHz 1 tLOW, SCLK Low Period Default 17 ns 1 tHIGH, SCLK High Period 17 ns 1 tSU.CS, CS Setup Time 39 ns 1 tHD.CS, CS Hold Time 5 ns 1 tSU.SDIO, SDIO Input Setup Time 13 ns 1 tHD.SDIO, SDIO Input Hold Time 8 ns 1 tVD.SDIO, SDIO Output Valid Time Cload = 20 pF tHD.SDIO, SDIO Output Hold Time Cload = 20 pF 18.5 3.5 28 tDIS.SDIO, SDIO Output Disable Time ns 1 ns 1 ns 1 Table 7. 3-Wire SPI Timing Characteristics (24-MHz Operation) Notes: 1. CS SCLK Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets 70% 30% tSU;CS SDIO I O 70% 30% 70% 30% tHIGH tSU;SDIO 1/fCLK tFall tRise tLOW tHD;SDIO LSB IN MSB IN tVD;SDIO MSB OUT 70% 30% Page 17 of 119 tDIS;SDIO tHD;SDIO Figure 3. 3-Wire SPI Bus Timing Diagram Document Number: DS-000401 Revision: 1.2 tHD;CS LSB OUT IIM-42652 RTC (CLKIN) TIMING CHARACTERIZATION Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETERS CONDITIONS MIN TYP MAX UNITS NOTES 31 32 50 kHz 1 µs 1 RTC (CLKIN) TIMING FRTC, RTC Clock Frequency Default tHIGHRTC, RTC Clock High Period 1 tRISERTC, RTC Clock Rise Time 5 500 ns 1 tFALLRTC, RTC Clock Fall Time 5 500 ns 1 Table 8. RTC Timing Characteristics Notes: 1. Based on characterization. Not tested in production. Figure 4. RTC Timing Diagram Document Number: DS-000401 Revision: 1.2 Page 18 of 119 IIM-42652 ABSOLUTE MAXIMUM RATINGS Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. Prolonged exposure to acceleration ranges beyond ±60g may affect device reliability. PARAMETER RATING Supply Voltage, VDD -0.5V to +4V Supply Voltage, VDDIO -0.5V to +4V Input Voltage Level (FSYNC, SCL, SDA) -0.5V to VDDIO + 0.5V Acceleration (Any Axis, unpowered) 20,000g for 0.2 ms Operating Temperature Range -40°C to +105°C Storage Temperature Range -40°C to +125°C 2 kV (HBM); Electrostatic Discharge (ESD) Protection 500V (CDM) JEDEC Class II (2),125°C Latch-up ±100 mA Table 9. Absolute Maximum Ratings Document Number: DS-000401 Revision: 1.2 Page 19 of 119 IIM-42652 4 APPLICATIONS INFORMATION PIN OUT DIAGRAM AND SIGNAL DESCRIPTION PIN NUMBER PIN NAME PIN DESCRIPTION AP_SDO: AP SPI serial data output (4-wire mode); AP_AD0: AP I3CSM / I2C slave address LSB 1 AP_SDO / AP_AD0 2 RESV No Connect or Connect to GND 3 RESV No Connect or Connect to GND 4 INT1 / INT 5 VDDIO 6 GND Power supply ground 7 RESV Connect to GND 8 VDD Power supply voltage 9 INT2 / FSYNC / CLKIN 10 RESV 11 RESV INT1: Interrupt 1 (Note: INT1 can be push-pull or open drain) INT: All interrupts mapped to pin 4 IO power supply voltage By default, pull-up is disabled. Pull-up can be enabled by setting PIN7_PU_EN = 1 (register 0x06h in Bank 3) and it can be disabled by setting PIN7_PU_EN = 0. INT2: Interrupt 2 (Note: INT2 can be push-pull or open drain) FSYNC: Frame sync input; Connect to GND if FSYNC not used CLKIN: External Clock Input No Connect or Connect to GND No Connect or Connect to GND AP_CS AP SPI Chip select (AP SPI interface); Connect to VDDIO if using AP I3CSM / I2C interface 13 AP_SCL / AP_SCLK AP_SCL: AP I3CSM / I2C serial clock; AP_SCLK: AP SPI serial clock AP_SDA / AP_SDIO / AP_SDI AP_SDA: AP I3C / I C serial data; AP_SDIO: AP SPI serial data I/O (3-wire mode); AP_SDI: AP SPI serial data input (4wire mode) SM 2 Table 10. Signal Descriptions Document Number: DS-000401 Revision: 1.2 By default, pull-down is disabled. Pull-down can be enabled by setting PIN9_PD_EN = 1 (register 0x06h in Bank 3). By default, pull-up is enabled. Pull-up can be disabled by setting PIN10_PU_EN = 0 and it can be enabled by setting PIN10_PU_EN = 1 (register 0x06h in Bank 3). By default, pull-up is enabled. Pull-up can be disabled by setting PIN11_PU_EN = 0 and it can be enabled by setting PIN11_PU_EN = 1 (register 0x06h in Bank 3). 12 14 PIN STATUS By default, pull-up/pull-down is disabled. Pull-up can be enabled by setting PIN1_PU_EN = 1 (register 0x0Eh in Bank 3). Pull-down can be enabled by setting PIN1_PD_EN = 1 (register 0x0Eh in Bank 3). Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. By default, pull-up is disabled. Pull-up can be enabled by setting PIN2_PU_EN = 1 (register 0x06h in Bank 3). By default, pull-up is disabled. Pull-up can be enabled by setting PIN3_PU_EN = 1 (register 0x06h in Bank 3). By default, pull-down is disabled. Pull-down can be enabled by setting PIN4_PD_EN = 1 (register 0x06h in Bank 3). Page 20 of 119 By default, pull-up is enabled. Pull-up can be disabled by setting PIN12_PU_EN = 0 (register 0x0Eh in Bank 3). Pull-down can be enabled by setting PIN12_PD_EN = 1 (register 0x0Eh in Bank 3). Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. By default, pull-up/pull-down is disabled. Pull-up can be enabled by setting PIN13_PU_EN = 1 (register 0x0Eh in Bank 3). Pull-down can be enabled by setting PIN13_PD_EN = 1 (register 0x0Eh in Bank 3). Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. By default, pull-up/pull-down is disabled. Pull-up can be enabled by setting PIN14_PU_EN = 1 (register 0x0Eh in Bank 3). Pull-down can be enabled by setting PIN14_PD_EN = 1 (register 0x0Eh in Bank 3). Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. IIM-42652 +Z IIM-42652 +Y Figure 5. Pin Out Diagram for IIM-42652 2.5 mm x 3.0 mm x 0.91 mm LGA TYPICAL OPERATING CIRCUIT 14 13 12 1 RESV 2 RESV 3 INT1 / INT AP_SCL AP_SDA AP_AD0 VDDIO ICM-42688-G IIM-42652 4 11 RESV 10 RESV 9 INT2 / FSYNC / CLKIN 8 5 6 7 VDD RESV GND VDDIO C1, 0.1 µF 1.71 – 3.6VDC C2, 2.2 µF 1.71 – 3.6VDC C3, 10 nF Figure 6. IIM-42652 Application Schematic (I3CSM / I2C Interface to Host) Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required. Document Number: DS-000401 Revision: 1.2 Page 21 of 119 +X IIM-42652 AP_SDO 14 13 12 1 RESV 2 RESV 3 INT1 / INT AP_SCLK AP_SDIO / AP_SDI AP_CS IIM-42652 ICM-42688-G 4 11 RESV 10 RESV 9 INT2 / FSYNC / CLKIN 8 5 6 7 1.71 – 3.6VDC VDD RESV GND VDDIO C1, 0.1 µF C2, 2.2 µF 1.71 – 3.6VDC C3, 10 nF Figure 7. IIM-42652 Application Schematic (SPI Interface to Host) BILL OF MATERIALS FOR EXTERNAL COMPONENTS COMPONENT LABEL SPECIFICATION QUANTITY VDD Bypass Capacitors C1 C2 X7R, 0.1µF ±10% X7R, 2.2µF ±10% 1 1 VDDIO Bypass Capacitor C3 X7R, 10nF ±10% 1 Table 11. Bill of Materials SYSTEM BLOCK DIAGRAM IIM-42652 Figure 8. IIM-42652 System Block Diagram Note: The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options. Document Number: DS-000401 Revision: 1.2 Page 22 of 119 IIM-42652 OVERVIEW The IIM-42652 is comprised of the following key blocks and functions: • • • • • • • • • • • • Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning o 20-bits data format support in FIFO for high-data resolution (see section 6 for details) Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning o 20-bits data format support in FIFO for high-data resolution (see section 6 for details) I3CSM, I2C, and SPI serial communications interfaces to Host Self-Test Clocking Sensor Data Registers FIFO Interrupts Digital-Output Temperature Sensor Bias and LDOs Charge Pump Standard Power Modes THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING The IIM-42652 includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes. When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees per second (dps). THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING The IIM-42652 includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The IIM-42652 architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The full-scale range of the digital output can be adjusted to ±2g, ±4g, ±8g and ±16g. I3CSM, I2C, AND SPI HOST INTERFACE The IIM-42652 communicates to the application processor using an I3CSM, I2C, or SPI serial interface. The IIM-42652 always acts as a slave when communicating to the application processor. SELF-TEST Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can be activated by means of the gyroscope and accelerometer self-test registers. When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response. The self-test response is defined as follows: SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have failed selftest. Document Number: DS-000401 Revision: 1.2 Page 23 of 119 IIM-42652 CLOCKING The IIM-42652 has a flexible clocking scheme, allowing the following internal clock sources to be used for the internal synchronous circuitry. This synchronous circuitry includes signal conditioning, ADCs, and various control circuits and registers. The CLKIN pin on IIM-42652 provides the ability to input an external clock. A highly accurate external clock may be used rather than the internal clock sources, if greater clock accuracy is desired. External clock input supports highly accurate clock input from 31 kHz to 50 kHz, resulting in improvement of the following: • • • • ODR uncertainty due to process, temperature, operating mode (PLL vs. RCOSC), and design limitations. This uncertainty can be as high as ±8% in RCOSC mode and ±1% in PLL mode. The CLKIN, assuming a 50 ppm or better 32.768 kHz source, will improve the ODR accuracy from ±80,000 ppm to ±50 ppm in RCOSC mode, or from ±10,000 ppm to ±50 ppm in PLL mode. System level sensitivity error. Any clock uncertainty directly impacts gyroscope sensitivity at the system level. Sophisticated systems can estimate ODR inaccuracy to some extent, but not to the extent improved by using CLKIN. System-level clock/sensor synchronization. When using CLKIN, the accelerometer and gyroscope are on the same clock as the host. There is no need to continually re-synchronize the sensor data as the sensor sample points and period are in exact alignment with the common system clock. Other applications that benefit from CLKIN include navigation, robotics. Allowable internal sources for generating the internal clock are: a) An internal relaxation oscillator b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source The only setting supporting specified performance in all modes is option b). Option b) is recommended when using the internal clock source. SENSOR DATA REGISTERS The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime. INTERRUPTS Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the interrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1) clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be read from the Interrupt Status register. DIGITAL-OUTPUT TEMPERATURE SENSOR An on-chip temperature sensor and ADC are used to measure the IIM-42652 die temperature. The readings from the ADC can be read from the FIFO or the Sensor Data registers. Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula: Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25 FIFO_TEMP_DATA, temperature data stored in FIFO, can be 8-bit or 16-it quantity. The 8-bit of temperature data stored in FIFO is limited to -40°C to 85°C range, while the 16-bit representation can support the full operating temperature range. It can be converted to degrees centigrade by using the following formula: Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25 Document Number: DS-000401 Revision: 1.2 Page 24 of 119 IIM-42652 BIAS AND LDOS The bias and LDO section generate the internal supply and the reference voltages and currents required by the IIM42652. CHARGE PUMP An on-chip charge pump generates the high voltage required for the MEMS oscillator. STANDARD POWER MODES Table 12 lists the user-accessible power modes for IIM-42652. MODE 1 2 3 4 5 6 NAME Sleep Mode Standby Mode Accelerometer Low-Power Mode Accelerometer Low-Noise Mode Gyroscope Low-Noise Mode 6-Axis Low-Noise Mode GYRO Off Drive On Off Off On On Table 12. Standard Power Modes for IIM-42652 Document Number: DS-000401 Revision: 1.2 Page 25 of 119 ACCEL Off Off Duty-Cycled On Off On IIM-42652 5 SIGNAL PATH The following figure shows a block diagram of the signal path for IIM-42652. ADC Decimation Filter (32kHz) Gyro Only Notch Filter 0 Anti-Alias Filter (AAF) 0 1 1 User Programmable Offset UI Filter Block (order, BW, ODR) Sensor Registers FSR Selection GYRO_NF_DIS AAF_DIS Figure 9. IIM-42652 Signal Path The signal path starts with ADCs for the gyroscope and accelerometer. Other components of the signal path are described in section 5.1 in further detail. SUMMARY OF PARAMETERS USED TO CONFIGURE THE SIGNAL PATH Table 13 shows the parameters that can control the signal path. PARAMETER NAME GYRO_AAF_DIS GYRO_AAF_DELT GYRO_AAF_DELTSQR GYRO_AAF_BITSHIFT ACCEL_AAF_DIS ACCEL_AAF_DELT ACCEL_AAF_DELTSQR ACCEL_AAF_BITSHIFT GYRO_NF_DIS GYRO_X/Y/Z_NF_COSWZ GYRO_X/Y/Z_NF_COSWZ_SEL GYRO_NF_BW_SEL DESCRIPTION Disables the Gyroscope Anti Alias Filter (AAF) Three parameters required to program the gyroscope AAF. This is a 2nd order filter with programmable low pass filter. This is a user programmable filter which can be used to select the desired BW. This filter allows trading off RMS noise vs. latency for a given ODR. Disables the Accelerometer Anti Alias Filter Three parameters required to program the accelerometer AAF. This is a 2nd order filter with programmable low pass filter. This is a user programmable filter which can be used to select the desired BW. This filter allows trading off RMS noise vs. latency for a given ODR. Disables the gyro Notch Filter Factory trimmed parameters, designed to position a Notch at or near the sense peak frequency of Gyro. This allows the user to suppress only sense peak contribution to noise, while still maintaining a low latency high BW/ODR interface from the Sensor. This filter is available only in gyro, and the parameters for X, Y, and Z are chosen independently. Factory trimmed parameter to cancel noise created by sense peak from gyro. This parameter is common to all three axes Table 13. Signal path parameters NOTCH FILTER The Notch Filter is only supported for the gyroscope signal path. The following steps can be used to program the notch filter. Note that the notch filter is specific to each axis in the gyroscope, so the X-, Y-, and Z-axis can be programmed independently. Frequency of Notch Filter (each axis) To operate the Notch filter, two parameters NF_COSWZ, and NF_COSWZ_SEL must be programmed for each gyroscope axis. Parameters NF_COSWZ are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ (register bank 1, register 0x0Fh & register 0x12h), GYRO_Y_NF_COSWZ (register bank 1, register 0x10h & register 0x12h), GYRO_Z_NF_COSWZ (register bank 1, register 0x11h & register 0x12h). Note that the parameters have 9-bit values across two different registers. Document Number: DS-000401 Revision: 1.2 Page 26 of 119 UI Interface IIM-42652 Parameters NF_COSWZ_SEL are defined for each axis of the gyroscope as GYRO_X_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 3), GYRO_Y_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 4), GYRO_Z_NF_COSWZ_SEL (register bank 1, register 0x12h, bit 5). Each value must be calculated using the steps described below and programmed into the corresponding register locations mentioned above. fdesired is the desired frequency of the Notch Filter in kHz. The lower bound for fdesired is 1 kHz, and the upper bound is 3 kHz. Operating the notch filter outside this range is not supported. Step1: COSWZ = cos(2*pi*fdesired/8) Step2: If abs(COSWZ)≤0.875 NF_COSWZ = round[COSWZ*256] NF_COSWZ_SEL = 0 else NF_COSWZ_SEL = 1 if COSWZ > 0.875 NF_COSWZ = round [8*(1-COSWZ)*256] else if COSWZ < -0.875 NF_COSWZ = round [-8*(1+COSWZ)*256] end End Bandwidth of Notch Filter (common to all axes) The notch filter allows the user to control the width of the notch from eight possible values using a 3-bit parameter GYRO_NF_BW_SEL in register bank 1, register 0x13h, bits 6:4. This parameter is common to all three axes. GYRO_NF_BW_SEL NOTCH FILTER BANDWIDTH (HZ) 0 1449 1 680 2 329 3 162 4 80 5 40 6 20 7 10 The notch filter can be selected or bypassed by using the parameter GYRO_NF_DIS in register bank 1, register 0x0Bh, bit 0 as shown below. Document Number: DS-000401 Revision: 1.2 GYRO_NF_DIS FUNCTION 0 Enable notch filter 1 Disable notch filter Page 27 of 119 IIM-42652 ANTI-ALIAS FILTER To program the anti-alias filter for a required bandwidth, use the table below to map the bandwidth to register values as shown: • • • • • • Register bank 2, register 0x03h, bits 6:1, ACCEL_AAF_DELT: Code from 1 to 63 that allows programming the bandwidth for accelerometer anti-alias filter Register bank 2, register 0x04h, bits 7:0 and Bank 2, register 0x05h, bits 3:0, ACCEL_AAF_DELTSQR: Square of the delt value for accelerometer Register bank 2, register 0x05h, bits 7:4, ACCEL_AAF_BITSHIFT: Bitshift value for accelerometer used in hardware implementation Register bank 1, register 0x0Ch, bits 5:0, GYRO_AAF_DELT: Code from 1 to 63 that allows programming the bandwidth for gyroscope anti-alias filter Register bank 1, register 0x0Dh, bits 7:0 and Bank 1, register 0x0Eh, bits 3:0, GYRO_AAF_DELTSQR: Square of the delt value for gyroscope Register bank 1, register 0x0Eh, bits 7:4, GYRO_AAF_BITSHIFT: Bitshift value for gyroscope used in hardware implementation 42 ACCEL_AAF_DELT; GYRO_AAF_DELT 1 ACCEL_AAF_DELTSQR; GYRO_AAF_DELTSQR 1 ACCEL_AAF_BITSHIFT; GYRO_AAF_BITSHIFT 15 84 2 4 13 126 3 9 12 170 4 16 11 213 5 25 10 258 6 36 10 303 7 49 9 348 8 64 9 394 9 81 9 441 10 100 8 488 11 122 8 536 12 144 8 585 13 170 8 634 14 196 7 684 15 224 7 734 16 256 7 785 17 288 7 837 18 324 7 890 19 360 6 943 20 400 6 997 21 440 6 1051 22 488 6 1107 23 528 6 1163 24 576 6 1220 25 624 6 1277 26 680 6 1336 27 736 5 3DB BANDWIDTH (HZ) Document Number: DS-000401 Revision: 1.2 Page 28 of 119 IIM-42652 1395 ACCEL_AAF_DELT; GYRO_AAF_DELT 28 ACCEL_AAF_DELTSQR; GYRO_AAF_DELTSQR 784 ACCEL_AAF_BITSHIFT; GYRO_AAF_BITSHIFT 5 1454 29 848 5 1515 30 896 5 1577 31 960 5 1639 32 1024 5 1702 33 1088 5 1766 34 1152 5 1830 35 1232 5 1896 36 1296 5 1962 37 1376 4 2029 38 1440 4 2097 39 1536 4 2166 40 1600 4 2235 41 1696 4 2306 42 1760 4 2377 43 1856 4 2449 44 1952 4 2522 45 2016 4 2596 46 2112 4 2671 47 2208 4 2746 48 2304 4 2823 49 2400 4 2900 50 2496 4 2978 51 2592 4 3057 52 2720 4 3137 53 2816 3 3217 54 2944 3 3299 55 3008 3 3381 56 3136 3 3464 57 3264 3 3548 58 3392 3 3633 59 3456 3 3718 60 3584 3 3805 61 3712 3 3892 62 3840 3 3979 63 3968 3 3DB BANDWIDTH (HZ) The anti-alias filter can be selected or bypassed for the gyroscope by using the parameter GYRO_AAF_DIS in register bank 1, register 0x0Bh, bit 1 as shown below. Document Number: DS-000401 Revision: 1.2 Page 29 of 119 IIM-42652 GYRO_AAF_DIS FUNCTION 0 Enable gyroscope anti-aliasing filter 1 Disable gyroscope anti-aliasing filter The anti-alias filter can be selected or bypassed for the accelerometer by using the parameter ACCEL_AAF_DIS in register bank 2, register 0x03h, bit 0 as shown below. ACCEL_AAF_DIS FUNCTION 0 Enable accelerometer anti-aliasing filter 1 Disable accelerometer anti-aliasing filter USER PROGRAMMABLE OFFSET Gyroscope and accelerometer offsets can be programmed by the user by using registers OFFSET_USER0, through OFFSET_USER8, in bank 0, registers 0x77h through 0x7Fh (bank 4) as shown below. REGISTER ADDRESS REGISTER NAME BITS 0x77h OFFSET_USER0 7:0 0x78h OFFSET_USER1 0x79h OFFSET_USER2 7:0 0x7Ah OFFSET_USER3 7:0 0x7Bh OFFSET_USER4 0x7Ch OFFSET_USER5 7:0 0x7Dh OFFSET_USER6 7:0 0x7Eh OFFSET_USER7 0x7Fh OFFSET_USER8 3:0 7:4 3:0 7:4 3:0 7:4 7:0 FUNCTION Lower bits of X-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Upper bits of X-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Upper bits of X-accel offset programmed by user. Max value is ±1 g, resolution is 0.5 mg. Lower bits of X-accel offset programmed by user. Max value is ±1 g, resolution is 0.5 mg. Lower bits of Y-accel offset programmed by user. Max value is ±1 g, resolution is 0.5 mg. Upper bits of Y-accel offset programmed by user. Max value is ±1 g, resolution is 0.5 mg. Upper bits of Z-accel offset programmed by user. Max value is ±1 g, resolution is 0.5 mg. Lower bits of Z-accel offset programmed by user. Max value is ±1 g, resolution is 0.5 mg. UI FILTER BLOCK The UI filter block can be programmed to select filter order and bandwidth independently for gyroscope and accelerometer. Gyroscope filter order can be selected by programming the parameter GYRO_UI_FILT_ORD in register bank 0, register 0x51h, bits 3:2, as shown below. Document Number: DS-000401 Revision: 1.2 Page 30 of 119 IIM-42652 GYRO_UI_FILT_ORD FILTER ORDER 00 1st order 01 2nd order 10 3rd order 11 Reserved Accelerometer filter order can be selected by programming the parameter ACCEL_UI_FILT_ORD in register bank 0, register 0x53h, bits 4:3, as shown below. ACCEL_UI_FILT_ORD FILTER ORDER 00 1st order 01 2nd order 10 3rd order 11 Reserved Gyroscope and accelerometer filter 3dB bandwidth can be selected by programming the parameter GYRO_UI_FILT_BW in register bank 0, register 0x52h, bits 3:0, and the parameter ACCEL_UI_FILT_BW in register bank 0, register 0x52h, bits 7:4, as shown below. The values shown in bold correspond to low noise and the values shown in italics correspond to low latency. User can select the appropriate setting based on the application requirements for power and latency. Corresponding Noise Bandwidth (NBW) and Group Delay values are also shown. 1st Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay 3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 1 32000 2 16000 4194.1 3 8000 2096.30 4 4000 1048.10 5 6 2000 524.00 1000 498.30 227.20 188.90 111.00 15 500 249.10 113.60 94.40 55.50 7 200 99.60 90.90 75.50 8 100 49.80 90.90 9 50 24.90 10 25 12.50 11 12.5 12.50 Document Number: DS-000401 Revision: 1.2 0 1 2 3 4 5 6 7 14 15 92.40 59.60 48.80 23.90 262.00 2096.30 46.20 29.80 24.40 11.90 131.00 1048.10 44.40 37.00 23.80 19.50 9.60 104.80 419.20 75.50 44.40 37.00 23.80 19.50 9.60 104.80 209.60 90.90 75.50 44.40 37.00 23.80 19.50 9.60 104.80 104.80 90.90 75.50 44.40 37.00 23.80 19.50 9.60 104.80 52.40 90.90 75.50 44.40 37.00 23.80 19.50 9.60 104.80 52.40 8400.0 Page 31 of 119 IIM-42652 NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 0 1 2 3 4 5 6 7 14 15 1 32000 8831.7 2 16000 4410.6 3 8000 2204.6 4 4000 1102.2 5 6 2000 1000 551.1 230.8 196.3 126.5 108.9 75.8 64.1 34.1 275.6 2204.6 15 500 280.5 115.4 98.2 7 63.3 54.5 37.9 32.1 17.1 137.8 1102.2 200 112.2 92.4 8 78.5 50.6 43.6 30.3 25.7 13.7 110.3 440.9 100 56.1 9 50 28.1 92.4 78.5 50.6 43.6 30.3 25.7 13.7 110.3 220.5 92.4 78.5 50.6 43.6 30.3 25.7 13.7 110.3 110.3 10 25 11 14.1 92.4 78.5 50.6 43.6 30.3 25.7 13.7 110.3 55.2 12.5 14.1 92.4 78.5 50.6 43.6 30.3 25.7 13.7 110.3 55.2 551.1 Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=0 (1st order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 1 32000 0.1 2 16000 0.1 3 8000 0.2 4 4000 0.4 5 6 2000 0.8 1000 0.6 1.8 2.0 2.8 15 500 1.1 3.6 4.0 5.5 7 200 2.7 4.4 5.0 8 100 5.3 4.4 9 50 10.5 10 25 21.0 11 12.5 21.0 Document Number: DS-000401 Revision: 1.2 0 1 2 3 5 6 3.1 4.1 4.7 8.1 1.5 0.2 6.1 8.1 9.3 16.2 3.0 0.4 6.8 7.6 10.2 11.7 20.3 3.8 1.0 5.0 6.8 7.6 10.2 11.7 20.3 3.8 1.9 4.4 5.0 6.8 7.6 10.2 11.7 20.3 3.8 3.8 4.4 5.0 6.8 7.6 10.2 11.7 20.3 3.8 7.5 4.4 5.0 6.8 7.6 10.2 11.7 20.3 3.8 7.5 Page 32 of 119 4 7 14 15 IIM-42652 2nd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay 3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 1 32000 0 1 2 3 4 8400.0 5 6 7 14 15 2 16000 4194.1 3 8000 2096.3 4 4000 1048.1 5 6 2000 524.0 1000 493.3 230.7 191.6 117.5 15 97.1 59.6 48.0 21.3 262.0 2096.3 500 246.7 115.3 95.8 7 200 98.7 92.3 76.6 58.8 48.5 29.8 24.0 10.6 131.0 1048.1 47.0 38.8 23.8 19.2 8.5 104.8 419.2 8 100 49.3 92.3 9 76.6 47.0 38.8 23.8 19.2 8.5 104.8 209.6 50 24.7 92.3 76.6 47.0 38.8 23.8 19.2 8.5 104.8 104.8 10 25 12.3 92.3 76.6 47.0 38.8 23.8 19.2 8.5 104.8 52.4 11 12.5 12.3 92.3 76.6 47.0 38.8 23.8 19.2 8.5 104.8 52.4 NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 1 32000 8831.7 2 16000 4410.6 3 8000 2204.6 4 4000 1102.2 5 6 2000 1000 551.1 223.7 189.9 122.7 15 500 259.6 111.9 95.0 7 200 103.9 89.5 8 100 52.0 9 50 26.0 10 25 11 12.5 Document Number: DS-000401 Revision: 1.2 0 1 2 3 4 5 6 7 14 15 102.8 64.7 52.5 23.7 275.6 2204.6 61.4 51.4 32.4 26.3 11.9 137.8 1102.2 76.0 49.1 41.2 25.9 21.0 9.5 110.3 440.9 89.5 76.0 49.1 41.2 25.9 21.0 9.5 110.3 220.5 89.5 76.0 49.1 41.2 25.9 21.0 9.5 110.3 110.3 13.0 89.5 76.0 49.1 41.2 25.9 21.0 9.5 110.3 55.2 13.0 89.5 76.0 49.1 41.2 25.9 21.0 9.5 110.3 55.2 551.1 Page 33 of 119 IIM-42652 Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=1 (2nd order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 0 1 2 3 4 5 6 1 32000 0.1 2 16000 0.1 3 8000 0.2 4 4000 0.4 5 6 2000 1000 0.7 2.1 2.4 3.2 15 500 1.3 4.1 4.7 7 200 3.3 5.1 8 100 6.5 9 50 12.9 10 25 11 12.5 7 14 15 3.7 5.2 6.1 12.0 1.5 0.2 6.4 7.3 10.4 12.2 24.0 3.0 0.4 5.8 8.0 9.1 12.9 15.3 30.0 3.8 1.0 5.1 5.8 8.0 9.1 12.9 15.3 30.0 3.8 1.9 5.1 5.8 8.0 9.1 12.9 15.3 30.0 3.8 3.8 25.7 5.1 5.8 8.0 9.1 12.9 15.3 30.0 3.8 7.5 25.7 5.1 5.8 8.0 9.1 12.9 15.3 30.0 3.8 7.5 0.8 3rd Order Filter 3dB Bandwidth, Noise Bandwidth (NBW), Group Delay 3dB Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 1 32000 8400.0 2 16000 4194.1 3 8000 2096.3 4 4000 1048.1 5 6 2000 524.0 1000 492.9 234.7 195.8 118.9 15 500 246.4 117.4 97.9 59.5 7 200 98.6 93.9 78.3 8 100 49.3 93.9 9 50 24.6 93.9 10 25 12.3 11 12.5 12.3 Document Number: DS-000401 Revision: 1.2 0 1 2 3 5 6 7 14 15 97.9 60.8 46.8 25.2 262.0 2096.3 48.9 30.4 23.4 12.6 131.0 1048.1 47.6 39.2 24.3 18.7 10.1 104.8 419.2 78.3 47.6 39.2 24.3 18.7 10.1 104.8 209.6 78.3 47.6 39.2 24.3 18.7 10.1 104.8 104.8 93.9 78.3 47.6 39.2 24.3 18.7 10.1 104.8 52.4 93.9 78.3 47.6 39.2 24.3 18.7 10.1 104.8 52.4 Page 34 of 119 4 IIM-42652 NBW Bandwidth (Hz) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 0 1 2 3 4 5 6 7 14 15 1 32000 8831.7 2 16000 4410.6 3 8000 2204.6 4 4000 1102.2 5 6 2000 1000 551.1 221.3 188.5 120.1 100.0 62.9 48.6 26.4 275.6 2204.6 15 500 252.0 110.7 94.3 7 60.1 50.0 31.5 24.3 13.2 137.8 1102.2 200 100.8 88.6 8 75.4 48.1 40.0 25.2 19.5 10.6 110.3 440.9 100 50.4 9 50 25.2 88.6 75.4 48.1 40.0 25.2 19.5 10.6 110.3 220.5 88.6 75.4 48.1 40.0 25.2 19.5 10.6 110.3 110.3 10 25 11 12.6 88.6 75.4 48.1 40.0 25.2 19.5 10.6 110.3 55.2 12.5 12.6 88.6 75.4 48.1 40.0 25.2 19.5 10.6 110.3 55.2 551.1 Group Delay @DC (ms) for GYRO/ACCEL_UI_FILT_ORD=2 (3rd order filter) GYRO/ACCEL_UI_FILT_BW GYRO/ACCEL_ODR ODR(Hz) 1 32000 0.1 2 16000 0.1 3 8000 0.2 4 4000 0.4 5 6 2000 0.8 1000 0.8 2.3 2.7 4.0 4.6 6.6 8.2 14.1 1.5 0.2 15 500 1.6 4.6 5.4 7.9 9.2 13.2 16.3 28.1 3.0 0.4 7 200 4.0 5.8 6.8 9.8 11.4 16.5 20.4 35.2 3.8 1.0 8 100 8.0 5.8 6.8 9.8 11.4 16.5 20.4 35.2 3.8 1.9 9 50 15.9 5.8 6.8 9.8 11.4 16.5 20.4 35.2 3.8 3.8 10 25 31.8 5.8 6.8 9.8 11.4 16.5 20.4 35.2 3.8 7.5 11 12.5 31.8 5.8 6.8 9.8 11.4 16.5 20.4 35.2 3.8 7.5 Document Number: DS-000401 Revision: 1.2 0 1 2 Page 35 of 119 3 4 5 6 7 14 15 IIM-42652 ODR AND FSR SELECTION Gyroscope ODR can be selected by programming the parameter GYRO_ODR in register bank 0, register 0x4Fh, bits 3:0 as shown below. GYRO_ODR GYROSCOPE ODR VALUE 0000 Reserved 0001 32 kHz 0010 16 kHz 0011 8 kHz 0100 4 kHz 0101 2 kHz 0110 1 kHz (default) 0111 200 Hz 1000 100 Hz 1001 50 Hz 1010 25 Hz 1011 12.5 Hz 1100 Reserved 1101 Reserved 1110 Reserved 1111 500 Hz Gyroscope FSR can be selected by programming the parameter GYRO_FS_SEL in register bank 0, register 0x4Fh, bits 7:5 as shown below. GYRO_FS_SEL GYROSCOPE FSR VALUE 000 2000 dps 001 1000 dps 010 500 dps 011 250 dps 100 125 dps 101 62.5 dps 110 31.25 dps 111 15.625 dps Accelerometer ODR can be selected by programming the parameter ACCEL_ODR in register bank 0, register 0x50h, bits 3:0 as shown below. Document Number: DS-000401 Revision: 1.2 Page 36 of 119 IIM-42652 ACCEL_ODR ACCELEROMETER ODR VALUE 0000 Reserved 0001 32 kHz (LN mode) 0010 16 kHz (LN mode) 0011 8 kHz (LN mode) 0100 4 kHz (LN mode) 0101 2 kHz (LN mode) 0110 1 kHz (LN mode) (default) 0111 200 Hz (LP or LN mode) 1000 100 Hz (LP or LN mode) 1001 50 Hz (LP or LN mode) 1010 25 Hz (LP or LN mode) 1011 12.5 Hz (LP or LN mode) 1100 6.25 Hz (LP mode) 1101 3.125 Hz (LP mode) 1110 1.5625 Hz (LP mode) 1111 500 Hz (LP or LN mode) Accelerometer FSR can be selected by programming the parameter ACCEL_FS_SEL in register bank 0, register 0x50h, bits 7:5 as shown below. Document Number: DS-000401 Revision: 1.2 ACCEL_FS_SEL ACCELEROMETER FSR VALUE 000 16g 001 8g 010 4g 011 2g 100 Reserved 101 Reserved 110 Reserved 111 Reserved Page 37 of 119 IIM-42652 6 FIFO The IIM-42652 contains a 2K-byte FIFO register that is accessible via the serial interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. PACKET STRUCTURE The following figure shows the FIFO packet structures supported in IIM-42652. Base data format for gyroscope and accelerometer is 16-bits per element. 20-bits data format support is included in one of the packet structures. When 20-bits data format is used, gyroscope data consists of 19-bits of actual data and the LSB is always set to 0, accelerometer data consists of 18-bits of actual data and the two lowest order bits are always set to 0. When 20-bits data format is used, the only FSR settings that are operational are ±2000 dps for gyroscope and ±16g for accelerometer, even if the FSR selection register settings are configured for other FSR values. The corresponding sensitivity scale factor values are 131 LSB/dps for gyroscope and 8192 LSB/g for accelerometer. Header (1 byte) Header (1 byte) Header (1 byte) Header (1 byte) Accelerometer Data (6 bytes) Gyroscope Data (6 bytes) Accelerometer Data (6 bytes) Accelerometer Data (6 bytes) Temperature Data (1 byte) Temperature Data (1 byte) Gyroscope Data (6 bytes) Gyroscope Data (6 bytes) Temperature Data (1 byte) Temperature Data (2 bytes) TimeStamp (2 bytes) TimeStamp (2 bytes) Packet 1 Packet 2 Packet 3 20-bit Extension (3 bytes) Packet 4 Figure 10. FIFO Packet Structure Due to limitations on the number of bits, 8-bit temperature data stored in FIFO is limited to a -40°C to 85°C range. Either 16-bit temperature data format (FIFO packet 4) or the value from the sensor data registers (TEMP_DATA) must be used to support a temperature measurements range of -40°C to 105°C. The rest of this sub-section describes how individual data is packaged in the different FIFO packet structures. Document Number: DS-000401 Revision: 1.2 Page 38 of 119 IIM-42652 Packet 1: Individual data is packaged in Packet 1 as shown below. BYTE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CONTENT FIFO Header Accel X [15:8] Accel X [7:0] Accel Y [15:8] Accel Y [7:0] Accel Z [15:8] Accel Z [7:0] Temperature[7:0] Packet 2: Individual data is packaged in Packet 2 as shown below. BYTE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CONTENT FIFO Header Gyro X [15:8] Gyro X [7:0] Gyro Y [15:8] Gyro Y [7:0] Gyro Z [15:8] Gyro Z [7:0] Temperature[7:0] Packet 3: Individual data is packaged in Packet 3 as shown below. Document Number: DS-000401 Revision: 1.2 BYTE CONTENT 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F FIFO Header Accel X [15:8] Accel X [7:0] Accel Y [15:8] Accel Y [7:0] Accel Z [15:8] Accel Z [7:0] Gyro X [15:8] Gyro X [7:0] Gyro Y [15:8] Gyro Y [7:0] Gyro Z [15:8] Gyro Z [7:0] Temperature[7:0] TimeStamp[15:8] TimeStamp[7:0] Page 39 of 119 IIM-42652 Packet 4: Individual data is packaged in Packet 4 as shown below. BYTE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 CONTENT FIFO Header Accel X [19:12] Accel X [11:4] Accel Y [19:12] Accel Y [11:4] Accel Z [19:12] Accel Z [11:4] Gyro X [19:12] Gyro X [11:4] Gyro Y [19:12] Gyro Y [11:4] Gyro Z [19:12] Gyro Z [11:4] Temperature[15:8] Temperature[7:0] TimeStamp[15:8] TimeStamp[7:0] Accel X [3:0] Gyro X [3:0] Accel Y [3:0] Gyro Y [3:0] 0x13 Accel Z [3:0] Gyro Z [3:0] FIFO HEADER The following table shows the structure of the 1-byte FIFO header. BIT FIELD ITEM 7 HEADER_MSG 6 HEADER_ACCEL 5 HEADER_GYRO 4 HEADER_20 3:2 HEADER_TIMESTAMP_FSYNC 1 HEADER_ODR_ACCEL 0 HEADER_ODR_GYRO DESCRIPTION 1: FIFO is empty 0: Packet contains sensor data 1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN must be 1 0: Packet does not contain accel sample 1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must be 1 0: Packet does not contain gyro sample 1: Packet has a new and valid sample of extended 20-bit data for gyro and/or accel 0: Packet does not contain a new and valid extended 20-bit data 00: Packet does not contain timestamp or FSYNC time data 01: Reserved 10: Packet contains ODR Timestamp 11: Packet contains FSYNC time, and this packet is flagged as first ODR after FSYNC (only if FIFO_TMST_FSYNC_EN is 1) 1: The ODR for accel is different for this accel data packet compared to the previous accel packet 0: The ODR for accel is the same as the previous packet with accel 1: The ODR for gyro is different for this gyro data packet compared to the previous gyro packet 0: The ODR for gyro is the same as the previous packet with gyro Note at least HEADER_ACCEL or HEADER_GYRO must be set for a sensor data packet to be set. Document Number: DS-000401 Revision: 1.2 Page 40 of 119 IIM-42652 MAXIMUM FIFO STORAGE The maximum number of packets that can be stored in FIFO is a variable quantity depending on the use case. As shown in Figure 12, the physical FIFO size is 2048 bytes. A number of bytes equal to the packet size selected (see section 6.1) is reserved to prevent reading a packet during write operation. Additionally, a read cache 2 packets wide is available. When there is no serial interface operation, the read cache is not available for storing packets, being fed by the serial interface clock. When serial interface operation happens, depending on the operation length and the packet size chosen, either 1 or 2 of the packet entries in read cache may become available for storing packets. In that case the total storage available is up to the maximum number of packets that can be accommodated in 2048 bytes + 1 packet size, depending on the packet size used. Due to the non-deterministic nature of system operation, driver memory allocation should always be the largest size of 2080 bytes. FIFO 2048 Bytes 2 Packet Size Read Cache 2048 Bytes – 1 packet size 1 Packet Size Reserved to prevent reading a packet during write operation Figure 11. Maximum FIFO Storage FIFO CONFIGURATION REGISTERS The following control bits in bank 0, register 0x5Fh determine what data is placed into the FIFO. The values of these bits may change while the FIFO is being filled without corruption of the FIFO. BIT NAME 4 FIFO_HIRES_EN 3 FIFO_TMST_FSYNC_EN 1 FIFO_GYRO_EN 0 FIFO_ACCEL_EN Document Number: DS-000401 Revision: 1.2 FUNCTION 0: Default setting; Sensor data have regular resolution 1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes packet with priority on other setting below 0: FIFO will only contain ODR timestamp information 1: FIFO can also contain FSYNC time and FSYNC tag for one ODR after an FSYNC event 0: Default setting; Gyroscope data not placed into FIFO 1: Enables gyroscope data packets of 6-bytes to be placed in FIFO 0: Default setting; Accelerometer data not placed into FIFO 1: Enables accelerometer data packets of 6-bytes to be placed in FIFO Page 41 of 119 IIM-42652 Configuration register settings above impact FIFO header and FIFO packet size as follows: FIFO_HIRES_EN FIFO_ACCEL_EN FIFO_GYRO_EN 1 1 0 0 0 0 0 X X 1 1 1 0 0 X X 1 1 0 1 0 Document Number: DS-000401 Revision: 1.2 Page 42 of 119 FIFO_TMST_ FSYNC_EN 0 1 0 1 X X X HEADER PACKET SIZE 8’b_0111_10xx 8’b_0111_11xx 8’b_0110_10xx 8’b_0110_11xx 8’b_0100_00xx 8’b_0010_00xx No FIFO writes 20 Bytes 20 Bytes 16 Bytes 16 Bytes 8 Bytes 8 Bytes No FIFO writes IIM-42652 7 PROGRAMMABLE INTERRUPTS The IIM-42652 has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register section. The following configuration options are available for the interrupts: • • • INT1 and INT2 can be push-pull or open drain Level or pulse mode Active high or active low Additionally, IIM-42652 includes In-band Interrupt (IBI) support for the I3CSM interface. Document Number: DS-000401 Revision: 1.2 Page 43 of 119 IIM-42652 8 APEX MOTION FUNCTIONS The APEX (Advanced Pedometer and Event Detection – neXt gen) features of IIM-42652 consist of: • • • • • • Pedometer: tracks step count and issues a step detect interrupt. Tilt Detection: issues an interrupt when the tilt angle exceeds 35 degrees for more than a programmable time. Freefall Detection: triggers an interrupt when device freefall is detected and outputs freefall duration. Tap Detection: issues an interrupt when tap is detected, along with a register containing the tap count. Wake on Motion (WoM): detects motion when accelerometer samples exceed a programmable threshold. This motion event can be used to enable chip operation from sleep mode. Significant Motion Detector (SMD): detects motion if WoM events are detected during a programmable time window (2s or 4s). APEX ODR SUPPORT APEX algorithms are designed to work with the accelerometer for a variety of ODR settings. However, there is a minimum ODR required for each algorithm. The following table shows the relationship between the available accelerometer ODRs and the operation of the APEX algorithms. In order to allow more flexible operation where we can control the ODR of the APEX algorithms independent of the accelerometer ODR, we allow for an additional selection determined by the field DMP_ODR (DMP stands for Digital Motion ProcessorTM, an architectural component of APEX). The tables below show how DMP_ODR should be configured in relation to the accelerometer ODR and the expected performance. ACCEL ODR DMP_ODR PEDOMETER TILT DETECTION FREEFALL DETECTION < 25 Hz X Disabled Disabled Disabled ≥ 25Hz 0 (25 Hz) Low Power Low Power Low Power ≥ 50 Hz 2 (50 Hz) Normal Normal Low Power 100 Hz 3 (100 Hz) Normal (50 Hz) High Performance (50 Hz) Normal 500 Hz 1 (500 Hz) Disabled High Performance (50 Hz) High Performance Document Number: DS-000401 Revision: 1.2 ACCEL ODR TAP DETECTION 200 Hz Low Power 500 Hz Normal 1 kHz High Performance > 1 kHz Disabled Page 44 of 119 IIM-42652 If the accelerometer ODR is set below the minimum DMP ODR (25 Hz), the APEX features cannot be enabled. When the accelerometer ODR needs to be set differently from the DMP ODR, only the integer multiple of DMP ODR for accelerometer sensor ODR is suitable to use with DMP. For example, when the accelerometer ODR is set as 200 Hz, the APEX features can be enabled with choices of 25 Hz, or 50 Hz, depending on the DMP_ODR register setting. DMP ODR should not be changed on the fly. The following sequence should be followed for changing the DMP ODR: 1. 2. 3. 4. 5. Disable Pedometer and Tilt Detection if they are enabled Change DMP ODR Set DMP_INIT_EN for one cycle (Register 0x4Bh in Bank 0) Unset DMP_INIT_EN (Register 0x4Bh in Bank 0) Enable APEX features of interest DMP POWER SAVE MODE DMP Power Save Mode can be enabled or disabled by DMP_POWER_SAVE (Register 0x56h in Bank 0). When the DMP Power Save Mode is enabled, APEX features are enabled only when WOM is detected. WOM must be explicitly enabled for the DMP to work in this mode. When WOM is not detected the APEX features are on pause. If the user does not want to use DMP Power Save Mode they may set DMP_POWER_SAVE = 0, and use APEX functions without WOM detection. PEDOMETER PROGRAMMING • Pedometer configuration parameters 1. LOW_ENERGY_AMP_TH_SEL (Register 0x40h in Bank 4) 2. PED_AMP_TH_SEL (Register 0x41h in Bank 4) 3. PED_STEP_CNT_TH_SEL (Register 0x41h in Bank 4) 4. PED_HI_EN_TH_SEL (Register 0x42h in Bank 4) 5. PED_SB_TIMER_TH_SEL (Register 0x42h in Bank 4) 6. PED_STEP_DET_TH_SEL (Register 0x42h in Bank 4) 7. SENSITIVITY_MODE (Register 0x48h in Bank 4) 8. There are 2 ODR and 2 sensitivity modes ACCEL ODR (DMP_ODR) NORMAL SLOW WALK 25 Hz (0) low power low power and slow walk 50 Hz (2) high performance slow walk • Initialize Sensor in a typical configuration 1. Set accelerometer ODR to 50 Hz (Register 0x50h in Bank 0) 2. Set accelerometer to low power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Eh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode 3. Set DMP ODR = 50 Hz and turn on Pedometer feature (Register 0x56h in Bank 0) 4. Wait 1 millisecond • Initialize APEX hardware 1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0) 2. Wait 1 millisecond 3. Set LOW_ENERGY_AMP_TH_SEL to 10 (Register 0x40h in Bank 4) 4. Set PED_AMP_TH_SEL to 8 (Register 0x41h in Bank 4) 5. Set PED_STEP_CNT_TH_SEL to 5 (Register 0x41h in Bank 4) 6. Set PED_HI_EN_TH_SEL to 1 (Register 0x42h in Bank 4) 7. Set PED_SB_TIMER_TH_SEL to 4 (Register 0x42h in Bank 4) 8. Set PED_STEP_DET_TH_SEL to 2 (Register 0x42h in Bank 4) 9. Set SENSITIVITY_MODE to 0 (Register 0x48h in Bank 4) 10. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0) Document Number: DS-000401 Revision: 1.2 Page 45 of 119 IIM-42652 11. Wait 50 milliseconds 12. Enable STEP detection, source for INT1 by setting bit 5 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for STEP detection, enable STEP detection source by setting bit 5 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1. 13. As freefall and pedometer share the same output register, they cannot run concurrently. Disable freefall by setting FF_ENABLE to 0 (Register 0x56h in Bank 0) 14. Turn on Pedometer feature by setting PED_ENABLE to 1 (Register 0x56h in Bank 0) • Output registers 1. Read interrupt register (Register 0x38h in Bank 0) for STEP_DET_INT 2. If the step count is equal to or greater than 65535 (uint16), the STEP_CNT_OVF_INT (Register 0x38h in Bank 0) will be set to 1. Example:  Take 1 step =>output step count = 65533 (real step count is 65533)  Take 1 step => output step count = 65534 (real step count is 65534)  Take 1 step => output step count = 0 and interrupt is fired (real step count is 65535+0= 65535)  Take 1 step => output step count = 1 (real step count is 65535+1=65536) 3. Read the step count in STEP_CNT (Register 0x31h and 0x32h in Bank 0) 4. Read the step cadence in STEP_CADENCE (Register 0x33h in Bank 0) 5. Read the activity class in ACTIVITY_CLASS (Register 0x34h in Bank 0) TILT DETECTION PROGRAMMING • Tilt Detection configuration parameters 1. TILT_WAIT_TIME (Register 0x43h in Bank 4) This parameter configures how long of a delay after tilt is detected before interrupt is triggered Default is 2 (4s). Range is 0 = 0s, 1 = 2s, 2 = 4s, 3 = 6s For example, setting TILT_WAIT_TIME = 2 is equivalent to 4 seconds for all ODRs • Initialize Sensor in a typical configuration 1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 9 for 50 Hz or 10 for 25 Hz 2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode 3. Set DMP ODR (Register 0x56h in Bank 0) DMP_ODR = 0 for 25 Hz, 2 for 50 Hz 4. Wait 1 millisecond • Initialize APEX hardware 1. Set DMP_MEM_RESET_EN to 1 (Register 0x4Bh in Bank 0) 2. Wait 1 millisecond 3. Set TILT_WAIT_TIME (Register 0x43h in Bank 4) if default value does not meet needs 4. Wait 1 millisecond 5. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0) 6. Enable Tilt Detection, source for INT1 by setting bit 3 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for Tilt Detection, enable Tilt Detection source by setting bit 3 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1. 7. Wait 50 milliseconds 8. Turn on Tilt Detection feature by setting TILT_ENABLE to 1 (Register 0x56h in Bank 0) • Output registers 1. Read interrupt register (Register 0x38h in Bank 0) for TILT_DET_INT Document Number: DS-000401 Revision: 1.2 Page 46 of 119 IIM-42652 FREEFALL DETECTION PROGRAMMING Freefall Detection detects device freefall. It uses a low-g and a high-g detector to detect freefall start and freefall end. It provides a trigger indicating freefall event and the freefall duration. The duration is given in number of samples and can be converted to freefall distance in meters by applying the following formula: FF_DISTANCE = 0.5 * 9.81 * (FF_DUR * DMP_ODR_S)^2 Note: DMP_ODR_S is the duration of DMP_ODR expressed in seconds. • Freefall Detection configuration parameters 1. LOWG_PEAK_TH_SEL (Register 0x44h in Bank 4) 2. LOWG_TIME_TH_SEL (Register 0x44h in Bank 4) 3. LOWG_PEAK_TH_HYST_SEL (Register 0x43h in Bank 4) 4. HIGHG_PEAK_TH_SEL (Register 0x45h in Bank 4) 5. HIGHG_TIME_TH_SEL (Register 0x45h in Bank 4) 6. HIGHG_PEAK_TH_HYST_SEL (Register 0x43h in Bank 4) 7. FF_MIN_DURATION_CM (Register 0x49h in Bank 4) 8. FF_MAX_DURATION_CM (Register 0x49h in Bank 4) 9. FF_DEBOUNCE_DURATION (Register 0x49h in Bank 4) • Initialize Sensor in a typical configuration 1. Set Accel ODR to 500 Hz (Register 0x50h in Bank 0) 2. Set AVG filtering to 1 sample to minimize power consumption (Register 0x52h in Bank 0) ACCEL_UI_FILT_BW = 1 3. Set Accel to Low Power mode (Register 0x4E in Bank 0) ACCEL_MODE[1:0] = 2 4. Set DMP ODR = 500 Hz (Register 0x56 in Bank 0) DMP_ODR[1:0] = 1 • Initialize APEX hardware 1. Set LOWG_PEAK_TH_SEL (Register 0x44h in Bank 4) 2. Set LOWG_TIME_TH_SEL (Register 0x44h in Bank 4) 3. Set LOWG_PEAK_TH_HYST_SEL (Register 0x43 in Bank4) 4. Set HIGHG_PEAK_TH_SEL (Register 0x45h in Bank 4) 5. Set HIGHG_TIME_TH_SEL (Register 0x45h in Bank 4) 6. Set HIGHG_PEAK_TH_HYST_SEL (Register 0x43h in Bank4) 7. Set FF_DEBOUNCE_DURATION (Register 0x49h in Bank 4) 8. Set FF_MIN_DURATION_CM (Register 0x49h in Bank 4) 9. Set FF_MAX_DURATION_CM (Register 0x49h in Bank 4) 10. Set DMP_MEM_RESET_EN to 1 if DMP is started for the first time after reset (Register 0x4Bh in Bank 0) 11. Wait 1 millisecond 12. Set DMP_INIT_EN to 1 (Register 0x4Bh in Bank 0) 13. Enable FREEFALL detection, source for INT1 by setting bit 1 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for FREEFALL detection, enable FREEFALL detection source by setting bit 1 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1. 14. Wait 50 milliseconds 15. As freefall and pedometer share the same output register, they cannot run concurrently. Disable pedometer by setting PED_ENABLE to 0 (Register 0x56h in Bank 0) 16. Set FF_ENABLE to 1 (Register 0x56h in Bank 0) • Output registers 1. Read interrupt register (Register 0x38h in Bank 0) for FF_DET_INT Document Number: DS-000401 Revision: 1.2 Page 47 of 119 IIM-42652 2. • Read the freefall duration (Registers 0x31h and 0x32h in Bank 0) Note: As freefall and pedometer share the same output register, they cannot be run concurrently. TAP DETECTION PROGRAMMING • Tap Detection configuration parameters 1. TAP_TMAX (Register 0x47h in Bank 4) 2. TAP_TMIN (Register 0x47h in Bank 4) 3. TAP_TAVG (Register 0x47h in Bank 4) 4. TAP_MIN_JERK_THR (Register 0x46h in Bank 4) 5. TAP_MAX_PEAK_TOL (Register 0x46h in Bank 4) 6. TAP_ENABLE (Register 0x56h in Bank 0) • Initialize Sensor in a typical configuration 1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 15 for 500 Hz (ODR of 200Hz or 1kHz may also be used) 2. Set power modes and filter configurations as shown below  For ODR up to 500 Hz, set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and ACCEL_LP_CLK_SEL = 0, (Register 0x4Dh in Bank 0) for low power mode Set filter settings as follows: ACCEL_DEC2_M2_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW = 4 (Register 0x52h in Bank 0) • For ODR of 1 kHz, set Accel to Low Noise mode (Register 0x4Eh in Bank 0) ACCEL_MODE =1 Set filter settings as follows: ACCEL_UI_FILT_ORD = 2 (Register 0x53h in Bank 0); ACCEL_UI_FILT_BW = 0 (Register 0x52h in Bank 0) 3. Wait 1 millisecond • Initialize APEX hardware 1. Set TAP_TMAX to 2 (Register 0x47h in Bank 4) 2. Set TAP_TMIN to 3 (Register 0x47h in Bank 4) 3. Set TAP_TAVG to 3 (Register 0x47h in Bank 4) 4. Set TAP_MIN_JERK_THR to 17 (Register 0x46h in Bank 4) 5. Set TAP_MAX_PEAK_TOL to 2 (Register 0x46h in Bank 4) 6. Wait 1 millisecond 7. Enable TAP source for INT1 by setting bit 0 in register INT_SOURCE6 (Register 0x4Dh in Bank 4) to 1. Or if INT2 is selected for TAP, enable TAP source by setting bit 0 in register INT_SOURCE7 (Register 0x4Eh in Bank 4) to 1. 8. Wait 50 milliseconds 9. Turn on TAP feature by setting TAP_ENABLE to 1 (Register 0x56h in Bank 0) • Output registers 1. Read interrupt register (Register 0x38h in Bank 0) for TAP_DET_INT 2. Read the tap count in TAP_NUM (Register 0x7Bh in Bank 0) 3. Read the tap axis in TAP_AXIS (Register 0x7Bh in Bank 0) 4. Read the polarity of tap pulse in TAP_DIR (Register 0x7Bh in Bank 0) WAKE ON MOTION PROGRAMMING • Wake on Motion configuration parameters 1. WOM_X_TH (Register 0x4Ah in Bank 4) Document Number: DS-000401 Revision: 1.2 Page 48 of 119 IIM-42652 2. 3. 4. 5. 6. WOM_Y_TH (Register 0x4Bh in Bank 4) WOM_Z_TH (Register 0x4Ch in Bank 4) WOM_INT_MODE (Register 0x57h in Bank 0) WOM_MODE (Register 0x57h in Bank 0) SMD_MODE (Register 0x57h in Bank 0) • Initialize Sensor in a typical configuration 1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 9 for 50 Hz 2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode 3. Wait 1 millisecond • Initialize APEX hardware 1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4) 2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4) 3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4) 4. Wait 1 millisecond 5. Enable all 3 axes as WOM sources for INT1 by setting bits 2:0 in register INT_SOURCE1 (Register 0x66h in Bank 0) to 1. Or if INT2 is selected for WOM, enable all 3 axes as WOM sources by setting bits 2:0 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1. 6. Wait 50 milliseconds 7. Turn on WOM feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 1 (Register 0x56h in Bank 0) • Output registers 1. Read interrupt register (Register 0x37h in Bank 0) for WOM_X_INT 2. Read interrupt register (Register 0x37h in Bank 0) for WOM_Y_INT 3. Read interrupt register (Register 0x37h in Bank 0) for WOM_Z_INT SIGNIFICANT MOTION DETECTION PROGRAMMING • Significant Motion Detection configuration parameters 1. WOM_X_TH (Register 0x4Ah in Bank 4) 2. WOM_Y_TH (Register 0x4Bh in Bank 4) 3. WOM_Z_TH (Register 0x4Ch in Bank 4) 4. WOM_INT_MODE (Register 0x57h in Bank 0) 5. WOM_MODE (Register 0x57h in Bank 0) 6. SMD_MODE (Register 0x57h in Bank 0) • Initialize Sensor in a typical configuration 1. Set accelerometer ODR (Register 0x50h in Bank 0) ACCEL_ODR = 9 for 50 Hz 2. Set Accel to Low Power mode (Register 0x4Eh in Bank 0) ACCEL_MODE = 2 and (Register 0x4Dh in Bank 0), ACCEL_LP_CLK_SEL = 0, for low power mode 3. Wait 1 millisecond Document Number: DS-000401 Revision: 1.2 Page 49 of 119 IIM-42652 • Initialize APEX hardware 1. Set WOM_X_TH to 98 (Register 0x4Ah in Bank 4) 2. Set WOM_Y_TH to 98 (Register 0x4Bh in Bank 4) 3. Set WOM_Z_TH to 98 (Register 0x4Ch in Bank 4) 4. Wait 1 millisecond 5. Enable SMD source for INT1 by setting bit 3 in register INT_SOURCE1 (Register 0x66h in Bank 0) to 1. Or if INT2 is selected for SMD, enable SMD source by setting bit 3 in register INT_SOURCE4 (Register 0x69h in Bank 0) to 1. 6. Wait 50 milliseconds 7. Turn on SMD feature by setting WOM_INT_MODE to 0, WOM_MODE to 1, SMD_MODE to 3 (Register 0x56h in Bank 0) • Output registers 1. Read interrupt register (Register 0x37h in Bank 0) for SMD_INT Document Number: DS-000401 Revision: 1.2 Page 50 of 119 IIM-42652 9 DIGITAL INTERFACE I3CSM, I2C, AND SPI SERIAL INTERFACES The internal registers and memory of the IIM-42652 can be accessed using I3CSM at 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I2C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire mode. Pin assignments for serial interfaces are described in Section 4.1. I3CSM INTERFACE I3CSM is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3CSM is intended to improve upon the I2C interface, while preserving backward compatibility. I3CSM carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides the higher data rates, simpler pads, and lower power of SPI. I3CSM adds higher throughput for a given frequency, in-band interrupts (from slave to master), dynamic addressing. IIM-42652 supports the following features of I3CSM: • • • • • • • SDR data rate up to 12.5 Mbps DDR data rate up to 25 Mbps Dynamic address allocation In-band Interrupt (IBI) support Support for asynchronous timing control mode 0 Error detection (CRC and/or Parity) Common Command Code (CCC) The IIM-42652 always operates as an I3CSM slave device when communicating to the system processor, which thus acts as the I3CSM master. I3CSM master controls an active pullup resistance on SDA, which it can enable and disable. The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3CSM master. I2C INTERFACE I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master. The IIM-42652 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz. The slave address of the IIM-42652 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level on pin AP_AD0. This allows two IIM-42652s to be connected to the same I2C bus. When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address of the other should be b1101001 (pin AP_AD0 is logic high). I2C COMMUNICATIONS PROTOCOL START (S) and STOP (P) Conditions Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below). Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition. Document Number: DS-000401 Revision: 1.2 Page 51 of 119 IIM-42652 SDA SCL S P START condition STOP condition Figure 12. START and STOP Conditions Data Format / Acknowledge I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse. If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready and releases the clock line (refer to Figure 14). DATA OUTPUT BY TRANSMITTER (SDA) not acknowledge DATA OUTPUT BY RECEIVER (SDA) acknowledge SCL FROM MASTER 1 2 8 9 clock pulse for acknowledgement START condition Figure 13. Acknowledge on the I2C Bus Communications After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the exception of start and stop conditions. Document Number: DS-000401 Revision: 1.2 Page 52 of 119 IIM-42652 SDA SCL 1–7 8 8 1–7 9 9 1–7 8 9 S P START ADDRESS condition R/W DATA ACK DATA ACK ACK STOP condition Figure 14. Complete I2C Data Transfer To write the internal IIM-42652 registers, the master transmits the start condition (S), followed by the I2C address and the write bit (0). At the 9th clock cycle (when the clock is high), the IIM-42652 acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the IIM-42652 acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the IIM-42652 automatically increments the register address and loads the data to the appropriate register. The following figures show single and two-byte write sequences. Single-Byte Write Sequence Master Slave S AD+W RA ACK DATA ACK P ACK Burst Write Sequence Master Slave S AD+W RA ACK DATA ACK DATA ACK P ACK To read the internal IIM-42652 registers, the master sends a start condition, followed by the I2C address and a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the IIM-42652, the master transmits a start signal followed by the slave address and read bit. As a result, the IIM-42652 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The following figures show single and two-byte read sequences. Single-Byte Read Sequence Master Slave S AD+W RA ACK S AD+R ACK NACK ACK P DATA Burst Read Sequence Master Slave S AD+W Document Number: DS-000401 Revision: 1.2 RA ACK S ACK AD+R ACK ACK Page 53 of 119 DATA NACK DATA P IIM-42652 I2C TERMS SIGNAL S AD W R ACK NACK RA DATA P DESCRIPTION Start Condition: SDA goes from high to low while SCL is high Slave I2C address Write bit (0) Read bit (1) Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle Not-Acknowledge: SDA line stays high at the 9th clock cycle IIM-42652 internal register address Transmit or received data Stop condition: SDA going from low to high while SCL is high Table 14. I2C Terms SPI INTERFACE The IIM-42652 supports 3-wire or 4-wire SPI for the host interface. The IIM-42652 always operates as a Slave device during standard Master-Slave SPI operation. With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input (SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master. CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices. SPI Operational Features 1. Data is delivered MSB first and LSB last 2. Data is latched on the rising edge of SCLK 3. Data should be transitioned on the falling edge of SCLK 4. The maximum frequency of SCLK is 24 MHz 5. SPI read operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits contain the Register Address. In cases of multiple-byte Reads, data is two or more bytes: SPI Address format MSB R/W A6 A5 A4 A3 A2 A1 LSB A0 D1 LSB D0 SPI Data format MSB D7 D6 D5 D4 D3 D2 6. SPI write operations are completed in 16 clock cycles (two bytes). The first byte contains the SPI Address, and the second byte contains the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Write (0) operation. The following 7 bits contain the Register Address. 7. Supports Single or Burst Reads and Single Writes. Document Number: DS-000401 Revision: 1.2 Page 54 of 119 IIM-42652 SCLK SPI Master SDIO CS1 nCS SPI Slave 1 CS2 SCLK SDIO nCS SPI Slave 2 Figure 15. Typical SPI Master/Slave Configuration Document Number: DS-000401 Revision: 1.2 Page 55 of 119 IIM-42652 10 ASSEMBLY This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) devices packaged in LGA package. ORIENTATION OF AXES Figure 16 shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure. +Z +Y +Z +Y +X +X Figure 16. Orientation of Axes of Sensitivity and Polarity of Rotation Document Number: DS-000401 Revision: 1.2 Page 56 of 119 IIM-42652 PACKAGE DIMENSIONS 14 Lead LGA (2.5x3x0.91) mm NiAu pad finish Figure 17. Package Dimensions Document Number: DS-000401 Revision: 1.2 Page 57 of 119 IIM-42652 DIMENSIONS IN MILLIMETERS Total Thickness Substrate Thickness Mold Thickness Body Size Lead Width Lead Length Lead Pitch Lead Count Edge Pin Center to Center Body Center to Contact Pin Package Edge Tolerance Mold Flatness Coplanarity Document Number: DS-000401 Revision: 1.2 SYMBOLS A A1 A2 MIN 0.85 NOM 0.91 0.105 0.8 MAX 0.97 REF REF D 2.5 BSC E 3 BSC W 0.2 0.25 0.3 L e n 0.425 0.475 0.5 14 0.525 BSC D1 1.5 BSC E1 SD aaa bbb ddd 1 0.25 0.1 0.2 0.08 BSC BSC Page 58 of 119 IIM-42652 11 PART NUMBER PACKAGE MARKING The part number package marking for IIM-42652 devices is summarized below: PART NUMBER IIM-42652 PART NUMBER PACKAGE MARKING I4652 TOP VIEW Part Number Lot Traceability Code I4652 I4265 XXXXXX YYWW Y Y = Year Code W W = Work Week Figure 18. Part Number Package Marking Document Number: DS-000401 Revision: 1.2 Page 59 of 119 IIM-42652 12 USE NOTES ACCELEROMETER MODE TRANSITIONS When transitioning from accelerometer Low Power (LP) mode to accelerometer Low Noise (LN) mode, if ODR is 6.25 Hz or lower, software should change ODR to a value of 12.5 Hz or higher, because accelerometer LN mode does not support ODR values below 12.5 Hz. When transitioning from accelerometer LN mode to accelerometer LP mode, if ODR is greater than 500 Hz, software should change ODR to a value of 500 Hz or lower, because accelerometer LP mode does not support ODR values above 500 Hz. ACCELEROMETER LOW POWER (LP) MODE AVERAGING FILTER SETTING Software drivers provided with the device use Averaging Filter setting of 16x. This setting is recommended for meeting Android noise requirements in LP mode, and to minimize accelerometer offset variation when transitioning from LP to Low Noise (LN) mode. 1x averaging filter can be used by following the setting configuration shown in section 14.38. SETTINGS FOR I2C, I3CSM, AND SPI OPERATION Upon bootup the device comes up in SPI mode. The following settings should be used for I2C, I3CSM, and SPI operation. Scenario 1: INT1/INT2 pins are used for interrupt assertion in I3CSM mode. REGISTER FIELD I2C Driver Setting SPI Driver Setting 1 0 0 I3CSM Driver Setting 1 1 0 I3C_EN (bit 4, register INTF_CONFIG6, address 0x7C, bank 1) I3C_SDR_EN (bit 0, register INTF_CONFIG6, address 0x7C, bank 1) I3C_DDR_EN (bit 1, register INTF_CONFIG6, address 0x7C, bank 1) I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A, bank 1) I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address 0x13, bank 0) SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address 0x13, bank 0) 0 0 0 1 0 0 1 3 5 REGISTER FIELD I2C Driver Setting SPI Driver Setting I3C_EN (bit 4, register INTF_CONFIG6, address 0x7C, bank 1) I3C_SDR_EN (bit 0, register INTF_CONFIG6, address 0x7C, bank 1) I3C_DDR_EN (bit 1, register INTF_CONFIG6, address 0x7C, bank 1) I3C_BUS_MODE (bit 6, register INTF_CONFIG4, address 0x7A, bank 1) I2C_SLEW_RATE (bits 5:3, register DRIVE_CONFIG, address 0x13, bank 0) SPI_SLEW_RATE (bits 2:0, register DRIVE_CONFIG, address 0x13, bank 0) 1 0 0 I3CSM Driver Setting 1 1 1 0 0 0 1 0 0 1 5 5 1 1 1 Scenario 2: IBI is used for interrupt assertion in I3CSM mode. 1 1 1 NOTCH FILTER AND ANTI-ALIAS FILTER OPERATION Use of Notch Filter and Anti-Alias Filter is supported only for Low Noise (LN) mode operation. The host is responsible for keeping the UI path in LN mode while Notch Filter and Anti-Alias Filter are turned on. EXTERNAL CLOCK INPUT EFFECT ON ODR ODR values supported by the device scale with external clock frequency, if external clock input is used. The ODR values shown in the datasheet are supported with external clock input frequency of 32 kHz. For any other external clock input frequency, these ODR values will scale by a factor of (External clock value in kHz / 32). For example, if an external clock frequency of 32.768 kHz is used, instead of ODR value of 500 Hz, it will be 500 * (32.768 / 32) = 512 Hz. Document Number: DS-000401 Revision: 1.2 Page 60 of 119 IIM-42652 INT_ASYNC_RESET CONFIGURATION For register INT_CONFIG1 (bank 0 register 0x64) bit 4 INT_ASYNC_RESET, user should change setting to 0 from default setting of 1, for proper INT1 and INT2 pin operation. FIFO TIMESTAMP INTERVAL SCALING When RTC_MODE =1 (bank 0 register 0x4D bit2) and register INTF_CONFIG5 (bank 1 register 0x7B) bit 2:1 (PIN9_FUNCTION) is set to 10 for CLKIN input; THEN If TMST_RES = 0 (corresponding to timestamp resolution of 1 µs), timestamp interval reported in FIFO requires scaling by a factor of 32.768/RTC Frequency. For example, when ODR = 1 kHz, RTC Frequency 32 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO toggles between 976 and 977. After scaling 976.5 * 32.768/32 = 1000 μs. ELSE If TMST_RES = 1 (corresponding to timestamp resolution of 1 RTC clock period), timestamp interval reported in FIFO requires scaling by a factor of RTC clock period. For example, when ODR = 1 kHz, RTC Frequency 32 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO is 32. After scaling 1/32kHz*32 = 1000 μs. If TMST_RES = 0 (corresponding to timestamp resolution of 1µs), timestamp interval reported in FIFO requires scaling by a factor of 32/30. For example, when ODR = 1 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO toggles between 937 and 938. After scaling 937.5 * 32/30 = 1000 μs. If TMST_RES = 1 (corresponding to timestamp resolution of 16 µs), timestamp interval reported in FIFO requires scaling by a factor of 16*32/30. For example, when ODR = 1 kHz, the true timestamp interval should be 1000 μs. But the value in FIFO toggles between 58 and 59. After scaling 58.5 * 16* 32/30 = 1000 μs. ELSE Timestamp interval reported in FIFO requires scaling by a factor of 32/30. For example, when ODR = 1 kHz, the true timestamp interval should be 1000 µs. But the value in FIFO toggles between 937 and 938 µs. After scaling 937.5 * 32/30 = 1000 µs. SUPPLEMENTARY INFORMATION FOR FIFO_HOLD_LAST_DATA_EN This section contains supplementary information for using register field FIFO_HOLD_LAST_DATA_EN (bit 7) of register INTF_CONFIG0 (address 0x4C, bank 0). Document Number: DS-000401 Revision: 1.2 Page 61 of 119 IIM-42652 The following table shows the values in FIFO: 16-BIT FIFO PACKET FIFO_HOLD_LAST_DATA_EN 0 (Insert Invalid code) 1 (“copy last valid” mode: No invalid code insertion) Valid sample All values in: {-32766 to +32767} Invalid sample -32768 Valid sample All values in: {-32768 to +32767} Invalid sample 20-BIT FIFO PACKET Gyro: All Even numbers in {-524256 to +524286} Example: {-524256, -524254, -524252, -524250 …..+524284, +524286} Accel: Every Other Even number in {-524256 to +524284} Example: {-524256, -524252, -524248, -524244 …..+524280, +524284} -524288 Gyro: All Even numbers in {-524288 to +524286} Example: {-524288, -524286, -524284, -524282 …..+524284, +524286 } Accel: Every Other Even number in {-524288 to +524284} Example: {-524288, -524284, -524280 …..+524280, +524284} Copy last valid sample The following table shows the values in sense registers on reset: Power On Reset till First Sample FIFO_HOLD_LAST_DATA_EN = 0 FIFO_HOLD_LAST_DATA_EN = 1 Accel/Gyro/Temperature Sensor = -32768 Accel/Gyro/Temperature Sensor = 0 The following table shows the values in sense registers after first sample is received. As shown in the table, the combination of FIFO_HOLD_LAST_DATA_EN and FSYNC Tag determine the range of values read for valid samples and invalid samples. FIFO_HOLD_LAST_DATA_EN 0 (Insert Invalid code) 1 (“copy last valid” mode: No invalid code insertion) Valid sample Invalid sample Valid sample Document Number: DS-000401 Revision: 1.2 Invalid sample FSYNC Enabled on one Sensor Other Sensor Not Sensor selected for FSYNC Tag selected for FSYNC tagging FSYNC tagged FSYNC not tagged All values in: All ODD values in: All EVEN values in: All values in: {-32766 to +32767} {-32765 to +32767} {-32766 to {-32766 to +32767} +32766} Registers do not receive invalid samples. Registers hold last valid sample until new one arrives All values in: All ODD values in: All EVEN values in: All values in: {-32768 to +32767} {-32767 to +32767} {-32768 to {-32768 to +32767} +32766} Registers do not receive invalid samples. Registers hold last valid sample until new one arrives FSYNC tag disabled Page 62 of 119 IIM-42652 REGISTER VALUES MODIFICATION The only register settings that user can modify during sensor operation are for ODR selection, FSR selection, and sensor mode changes (register parameters GYRO_ODR, ACCEL_ODR, GYRO_FS_SEL, ACCEL_FS_SEL, GYRO_MODE, ACCEL_MODE). User must not modify any other register values during sensor operation. The following procedure must be used for other register values modification. • • • Turn Accel and Gyro Off Modify register values Turn Accel and/or Gyro On Document Number: DS-000401 Revision: 1.2 Page 63 of 119 IIM-42652 13 REGISTER MAP This section lists the register map for the IIM-42652, for user banks 0, 1, 2, 4. USER BANK 0 REGISTER MAP Addr (Hex) Addr (Dec.) Register Name Serial I/F 11 17 DEVICE_CONFIG R/W 13 19 DRIVE_CONFIG R/W 14 20 Bit7 Bit6 Bit5 - INT_CONFIG Bit4 Bit3 Bit2 SPI_MODE - I2C_SLEW_RATE - INT2_DRIVE_ CIRCUIT INT2_MODE Bit0 SOFT_RESET_ CONFIG SPI_SLEW_RATE INT2_POLARI TY 16 22 FIFO_CONFIG R/W 1D 29 TEMP_DATA1_UI SYNCR 1E 30 TEMP_DATA0_UI SYNCR TEMP_DATA[7:0] 1F 31 ACCEL_DATA_X1_UI SYNCR ACCEL_DATA_XI[15:8] 20 32 ACCEL_DATA_X0_UI SYNCR ACCEL_DATA_X[7:0] 21 33 ACCEL_DATA_Y1_UI SYNCR ACCEL_DATA_Y[15:8] 22 34 ACCEL_DATA_Y0_UI SYNCR ACCEL_DATA_YI[7:0] 23 35 ACCEL_DATA_Z1_UI SYNCR ACCEL_DATA_Z[15:8] 24 36 ACCEL_DATA_Z0_UI SYNCR ACCEL_DATA_Z[7:0] 25 37 GYRO_DATA_X1_UI SYNCR GYRO _DATA_XI[15:8] 26 38 GYRO _DATA_X0_UI SYNCR GYRO _DATA_X[7:0] 27 39 GYRO _DATA_Y1_UI SYNCR GYRO _DATA_Y[15:8] 28 40 GYRO _DATA_Y0_UI SYNCR GYRO _DATA_YI[7:0] 29 41 GYRO _DATA_Z1_UI SYNCR GYRO_DATA_ZI[15:8] 2A 42 GYRO _DATA_Z0_UI SYNCR GYRO_DATA_ZI[7:0] 2B 43 TMST_FSYNCH SYNCR TMST_FSYNC_DATA[15:8] 2C 44 TMST_FSYNCL SYNCR TMST_FSYNC_DATA[7:0] 2D 45 INT_STATUS R/C 2E 46 FIFO_COUNTH R FIFO_COUNT[15:8] 2F 47 FIFO_COUNTL R FIFO_COUNT[7:0] 30 48 FIFO_DATA R FIFO_DATA 31 49 APEX_DATA0 SYNCR STEP_CNT[7:0] / FF_DUR[7:0] 32 50 APEX_DATA1 SYNCR STEP_CNT[15:8] / FF_DUR[15:8] 33 51 APEX_DATA2 R 34 52 APEX_DATA3 R 35 53 APEX_DATA4 R 36 54 APEX_DATA5 R 37 55 INT_STATUS2 R/C FIFO_MODE INT1_MODE INT1_DRIVE_ CIRCUIT INT1_POLARI TY FIFO_THS_IN T FIFO_FULL_I NT AGC_RDY_IN T TEMP_DATA[15:8] - FSYNC_INT PLL_RDY_INT RESET_DONE _INT DATA_RDY_I NT STEP_CADENCE - DMP_IDLE - TAP_NUM - ACTIVITY_CLASS TAP_AXIS TAP_DIR DOUBLE_TAP_TIMING - - SMD_INT WOM_Z_INT WOM_Y_INT WOM_X_INT STEP_DET_IN T STEP_CNT_O VF_INT TILT_DET_IN T - FF_DET_INT TAP_DET_INT ABORT_AND _RESET TMST_STROB E FIFO_FLUSH - 38 56 INT_STATUS3 R/C 4B 75 SIGNAL_PATH_RESET W/C - DMP_INIT_E N DMP_MEM_ RESET_EN - 4C 76 INTF_CONFIG0 R/W FIFO_HOLD_L AST_DATA_E N FIFO_COUNT _REC FIFO_COUNT _ENDIAN SENSOR_DAT A_ENDIAN 4D 77 INTF_CONFIG1 R/W 4E 78 PWR_MGMT0 R/W 4F 79 GYRO_CONFIG0 R/W GYRO_UI_FS_SEL - 50 80 ACCEL_CONFIG0 R/W ACCEL_UI_FS_SEL - 51 81 GYRO_CONFIG1 R/W TEMP_FILT_BW - 52 82 GYRO_ACCEL_CONFIG0 R/W ACCEL_UI_FILT_BW 53 83 ACCEL_CONFIG1 R/W - Document Number: DS-000401 Revision: 1.2 Bit1 ACCEL_LP_CL K_SEL - - TEMP_DIS IDLE RTC_MODE CLKSEL GYRO_MODE ACCEL_MODE GYRO_ODR ACCEL_ODR GYRO_UI_FILT_ORD GYRO_DEC2_M2_ORD GYRO_UI_FILT_BW ACCEL_UI_FILT_ORD Page 64 of 119 UI_SIFS_CFG ACCEL_DEC2_M2_ORD - IIM-42652 Addr (Hex) Addr (Dec.) Register Name Serial I/F Bit7 Bit6 Bit5 Bit4 - Bit3 Bit2 Bit1 Bit0 TMST_TO_RE GS_EN TMST_RES TMST_DELTA _EN TMST_FSYNC _EN TMST_EN TILT_ENABLE - FF_ENABLE DMP_ODR WOM_INT_ MODE WOM_MODE SMD_MODE FIFO_TMST_F SYNC_EN FIFO_TEMP_ EN 54 84 TMST_CONFIG R/W 56 86 APEX_CONFIG0 R/W 57 87 SMD_CONFIG R/W 5F 95 FIFO_CONFIG1 R/W 60 96 FIFO_CONFIG2 R/W 61 97 FIFO_CONFIG3 R/W 62 98 FSYNC_CONFIG R/W 63 99 INT_CONFIG0 R/W 64 100 INT_CONFIG1 R/W - INT_TPULSE_ DURATION INT_TDEASSE RT_DISABLE INT_ASYNC_ RESET 65 101 INT_SOURCE0 R/W - UI_FSYNC_IN T1_EN PLL_RDY_INT 1_EN RESET_DONE _INT1_EN 66 102 INT_SOURCE1 R/W - I3C_PROTOC OL_ERROR_I NT1_EN 68 104 INT_SOURCE3 R/W - UI_FSYNC_IN T2_EN 69 105 INT_SOURCE4 R/W - I3C_PROTOC OL_ERROR_I NT2_EN 6C 108 FIFO_LOST_PKT0 R 6D 109 FIFO_LOST_PKT1 R 70 112 SELF_TEST_CONFIG R/W 75 117 WHO_AM_I R 76 118 REG_BANK_SEL R/W DMP_POWE R_SAVE TAP_ENABLE PED_ENABLE - FIFO_RESUM E_PARTIAL_R D - FIFO_WM_G T_TH FIFO_HIRES_ EN FIFO_GYRO_ EN FIFO_ACCEL_ EN FIFO_WM[7:0] - FIFO_WM[11:8] FSYNC_UI_SEL - FSYNC_UI_FL AG_CLEAR_S EL - UI_DRDY_INT_CLEAR FIFO_THS_INT_CLEAR PLL_RDY_INT 2_EN RESET_DONE _INT2_EN - FSYNC_POLA RITY FIFO_FULL_INT_CLEAR - UI_DRDY_INT 1_EN FIFO_THS_IN T1_EN FIFO_FULL_I NT1_EN UI_AGC_RDY _INT1_EN SMD_INT1_E N WOM_Z_INT 1_EN WOM_Y_INT 1_EN WOM_X_INT 1_EN UI_DRDY_INT 2_EN FIFO_THS_IN T2_EN FIFO_FULL_I NT2_EN UI_AGC_RDY _INT2_EN SMD_INT2_E N WOM_Z_INT 2_EN WOM_Y_INT 2_EN WOM_X_INT 2_EN EN_GZ_ST EN_GY_ST EN_GX_ST FIFO_LOST_PKT_CNT[15:8] FIFO_LOST_PKT_CNT[7:0] ACCEL_ST_P OWER EN_AZ_ST EN_AY_ST EN_AX_ST WHOAMI - BANK_SEL USER BANK 1 REGISTER MAP Addr (Hex) Addr (Dec.) Register Name Serial I/F 03 03 SENSOR_CONFIG0 R/W 0B 11 GYRO_CONFIG_STATIC2 R/W Bit7 Bit6 - Bit5 Bit4 Bit3 Bit2 ZG_DISABLE YG_DISABLE XG_DISABLE ZA_DISABLE - 0C 12 GYRO_CONFIG_STATIC3 R/W 0D 13 GYRO_CONFIG_STATIC4 R/W 0E 14 GYRO_CONFIG_STATIC5 R/W 0F 15 GYRO_CONFIG_STATIC6 R/W GYRO_X_NF_COSWZ[7:0] 10 16 GYRO_CONFIG_STATIC7 R/W GYRO_Y_NF_COSWZ[7:0] 11 17 GYRO_CONFIG_STATIC8 R/W 12 18 GYRO_CONFIG_STATIC9 R/W 13 19 GYRO_CONFIG_STATIC10 R/W - Bit0 YA_DISABLE XA_DISABLE GYRO_AAF_D IS GYRO_NF_DI S GYRO_AAF_DELT GYRO_AAF_DELTSQR[7:0] GYRO_AAF_BITSHIFT GYRO_AAF_DELTSQR[11:8] GYRO_Z_NF_COSWZ[7:0] GYRO_Z_NF_ COSWZ_SEL[ 0] - - GYRO_Y_NF_ COSWZ_SEL[ 0] GYRO_X_NF_ COSWZ_SEL[ 0] GYRO_NF_BW_SEL GYRO_Z_NF_ COSWZ[8] GYRO_Y_NF_ COSWZ[8] GYRO_HPF_BW_IND 5F 95 XG_ST_DATA R/W XG_ST_DATA 60 96 YG_ST_DATA R/W YG_ST_DATA 61 97 ZG_ST_DATA R/W ZG_ST_DATA 62 98 TMSTVAL0 R TMST_VALUE[7:0] 63 99 TMSTVAL1 R 64 100 TMSTVAL2 R Document Number: DS-000401 Revision: 1.2 Bit1 TMST_VALUE[15:8] - Page 65 of 119 TMST_VALUE[19:16] GYRO_X_NF_ COSWZ[8] GYRO_HPF_O RD_IND IIM-42652 Addr (Hex) Addr (Dec.) Register Name Serial I/F 7A 122 INTF_CONFIG4 R/W 7B 123 INTF_CONFIG5 R/W 7C 124 INTF_CONFIG6 R/W Bit7 Bit6 - I3C_BUS_MO DE Bit5 Bit4 Bit3 Bit2 - ASYNCTIME0 _DIS Bit1 Bit0 SPI_AP_4WIR E - PIN9_FUNCTION - - I3C_EN I3C_IBI_BYTE _EN I3C_IBI_EN I3C_DDR_EN I3C_SDR_EN Bit4 Bit3 Bit2 Bit1 Bit0 USER BANK 2 REGISTER MAP Addr (Hex) Addr (Dec.) Register Name Serial I/F Bit7 03 03 ACCEL_CONFIG_STATIC2 R/W - 04 04 ACCEL_CONFIG_STATIC3 R/W 05 05 ACCEL_CONFIG_STATIC4 R/W 3B 59 XA_ST_DATA R/W XA_ST_DATA 3C 60 YA_ST_DATA R/W YA_ST_DATA 3D 61 ZA_ST_DATA R/W ZA_ST_DATA Bit6 Bit5 ACCEL_AAF_ DIS ACCEL_AAF_DELT ACCEL_AAF_DELTSQR[7:0] ACCEL_AAF_BITSHIFT ACCEL_AAF_DELTSQR[11:8] USER BANK 3 REGISTER MAP Addr (Hex) Addr (Dec.) Register Name Serial I/F Bit7 PIN7_PU_EN Bit6 06 06 PU_PD_CONFIG1 R/W PIN11_PU_E N 0E 14 PU_PD_CONFIG2 R/W PIN1_PU_EN Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - PIN9_PD_EN PIN10_PU_E N PIN3_PU_EN PIN2_PU_EN PIN4_PD_EN PIN1_PD_EN PIN12_PU_E N PIN12_PD_E N PIN14_PU_E N PIN14_PD_E N PIN13_PU_E N PIN13_PD_E N Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USER BANK 4 REGISTER MAP Addr (Hex) Addr (Dec.) Register Name Serial I/F Bit7 09 40 09 FDR_CONFIG R/W - 64 APEX_CONFIG1 R/W LOW_ENERGY_AMP_TH_SEL 41 65 APEX_CONFIG2 R/W PED_AMP_TH_SEL 42 66 APEX_CONFIG3 R/W 43 67 APEX_CONFIG4 R/W 44 68 APEX_CONFIG5 R/W LOWG_PEAK_TH_SEL LOWG_TIME_TH_SEL 45 69 APEX_CONFIG6 R/W HIGHG_PEAK_TH_SEL HIGHG_TIME_TH_SEL 46 70 APEX_CONFIG7 R/W 47 71 APEX_CONFIG8 R/W 48 72 APEX_CONFIG9 R/W FDR_SEL DMP_POWER_SAVE_TIME_SEL PED_STEP_CNT_TH_SEL PED_STEP_DET_TH_SEL PED_SB_TIMER_TH_SEL TILT_WAIT_TIME_SEL PED_HI_EN_TH_SEL LOWG_PEAK_TH_HYST_SEL HIGHG_PEAK_TH_HYST_SEL TAP_MIN_JERK_THR - TAP_TMAX TAP_MAX_PEAK_TOL TAP_TAVG TAP_TMIN SENSITIVITY_ MODE - 49 73 APEX_CONFIG10 R/W 4A 74 ACCEL_WOM_X_THR R/W FF_MIN_DURATION_CM WOM_X_TH FF_MAX_DURATION_CM 4B 75 ACCEL_WOM_Y_THR R/W WOM_Y_TH 4C 76 ACCEL_WOM_Z_THR R/W FF_DEBOUNCE_DURATION WOM_Z_TH 4D 77 INT_SOURCE6 R/W - STEP_DET_IN T1_EN 4E 78 INT_SOURCE7 R/W - STEP_DET_IN T2_EN STEP_CNT_O FL_INT2_EN TILT_DET_IN T2_EN - FREEFALL_DE T_INT2_EN TAP_DET_INT 2_EN 4F 79 INT_SOURCE8 R/W - FSYNC_IBI_E N PLL_RDY_IBI_ EN UI_DRDY_IBI _EN FIFO_THS_IBI _EN FIFO_FULL_IB I_EN AGC_RDY_IBI _EN 50 80 INT_SOURCE9 R/W SMD_IBI_EN WOM_Z_IBI_ EN WOM_Y_IBI_ EN WOM_X_IBI_ EN - 51 81 INT_SOURCE10 R/W STEP_CNT_O FL_IBI_EN TILT_DET_IBI _EN - FREEFALL_DE T_IBI_EN TAP_DET_IBI _EN 77 119 OFFSET_USER0 R/W Document Number: DS-000401 Revision: 1.2 I3C_PROTOC OL_ERROR_I BI_EN - - STEP_DET_IB I_EN STEP_CNT_O FL_INT1_EN TILT_DET_IN T1_EN - FREEFALL_DE T_INT1_EN TAP_DET_INT 1_EN GYRO_X_OFFUSER[7:0] Page 66 of 119 IIM-42652 Addr (Hex) Addr (Dec.) Register Name Serial I/F 78 120 OFFSET_USER1 R/W 79 121 OFFSET_USER2 R/W 7A 122 OFFSET_USER3 R/W 7B 123 OFFSET_USER4 R/W 7C 124 OFFSET_USER5 R/W 7D 125 OFFSET_USER6 R/W 7E 126 OFFSET_USER7 R/W 7F 127 OFFSET_USER8 R/W Bit7 Bit6 Bit5 Bit4 Bit3 GYRO_Y_OFFUSER[11:8] Bit2 Bit1 GYRO_X_OFFUSER[11:8] GYRO_Y_OFFUSER[7:0] GYRO_Z_OFFUSER[7:0] ACCEL_X_OFFUSER[11:8] GYRO_Z_OFFUSER[11:8] ACCEL_X_OFFUSER[7:0] ACCEL_Y_OFFUSER[7:0] ACCEL_Z_OFFUSER[11:8] ACCEL_Y_OFFUSER[11:8] ACCEL_Z_OFFUSER[7:0] Detailed register descriptions are provided in the sections that follow. Please note the following regarding Clock Domain for each register: • Clock Domain: SCLK_UI means that the register is controlled from the UI interface Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used to determine the default value of reserved register fields, and unless otherwise noted this default value must be maintained even if the values of other register fields are modified by the user. REGISTER VALUES MODIFICATION The only register settings that user can modify during sensor operation are for ODR selection, FSR selection, and sensor mode changes (register parameters GYRO_ODR, ACCEL_ODR, GYRO_FS_SEL, ACCEL_FS_SEL, GYRO_MODE, ACCEL_MODE). User must not modify any other register values during sensor operation. The following procedure must be used for register values modification: • Turn Accel and Gyro Off • Modify register values • Turn Accel and/or Gyro On Document Number: DS-000401 Revision: 1.2 Page 67 of 119 Bit0 IIM-42652 14 USER BANK 0 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within USR Bank 0. Note: The device powers up in sleep mode. DEVICE_CONFIG Name: DEVICE_CONFIG Address: 17 (11h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:5 4 SPI_MODE 3:1 0 SOFT_RESET_CONFIG FUNCTION Reserved SPI mode selection 0: Mode 0 and Mode 3 (default) 1: Mode 1 and Mode 2 Reserved Software reset configuration 0: Normal (default) 1: Enable reset After writing 1 to this bitfield, wait 1ms for soft reset to be effective, before attempting any other register access DRIVE_CONFIG Name: DRIVE_CONFIG Address: 19 (13h) Serial IF: R/W Reset value: 0x05 Clock Domain: SCLK_UI BIT NAME 7:6 - 5:3 I2C_SLEW_RATE 2:0 SPI_SLEW_RATE Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved Controls slew rate for output pin 14 in I2C mode only 000: 20ns-60ns 001: 12ns-36ns 010: 6ns-18ns 011: 4ns-12ns 100: 2ns-6ns 101: < 2ns 110: Reserved 111: Reserved Controls slew rate for output pin 14 in SPI or I3CSM mode, and for all other output pins 000: 20ns-60ns 001: 12ns-36ns 010: 6ns-18ns 011: 4ns-12ns 100: 2ns-6ns 101: < 2ns 110: Reserved 111: Reserved Page 68 of 119 IIM-42652 INT_CONFIG Name: INT_CONFIG Address: 20 (14h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 INT2_MODE 4 INT2_DRIVE_CIRCUIT 3 INT2_POLARITY 2 INT1_MODE 1 INT1_DRIVE_CIRCUIT 0 INT1_POLARITY FUNCTION Reserved INT2 interrupt mode 0: Pulsed mode 1: Latched mode INT2 drive circuit 0: Open drain 1: Push pull INT2 interrupt polarity 0: Active low (default) 1: Active high INT1 interrupt mode 0: Pulsed mode 1: Latched mode INT1 drive circuit 0: Open drain 1: Push pull INT1 interrupt polarity 0: Active low (default) 1: Active high FIFO_CONFIG Name: FIFO_CONFIG Address: 22 (16h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 FIFO_MODE 5:0 - FUNCTION 00: Bypass Mode (default) 01: Stream-to-FIFO Mode 10: STOP-on-FULL Mode 11: STOP-on-FULL Mode Reserved TEMP_DATA1 Name: TEMP_DATA1 Address: 29 (1Dh) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 TEMP_DATA[15:8] Document Number: DS-000401 Revision: 1.2 FUNCTION Upper byte of temperature data Page 69 of 119 IIM-42652 TEMP_DATA0 Name: TEMP_DATA0 Address: 30 (1Eh) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 TEMP_DATA[7:0] FUNCTION Lower byte of temperature data Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula: Temperature in Degrees Centigrade = (TEMP_DATA / 132.48) + 25 FIFO_TEMP_DATA, temperature data stored in FIFO, can be 8-bit or 16-it quantity. The 8-bit of temperature data stored in FIFO is limited to -40°C to 85°C range, while the 16-bit representation can support the full operating temperature range. It can be converted to degrees centigrade by using the following formula: Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2.07) + 25 ACCEL_DATA_X1 Name: ACCEL_DATA_X1 Address: 31 (1Fh) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_DATA_X[15:8] FUNCTION Upper byte of Accel X-axis data ACCEL_DATA_X0 Name: ACCEL_DATA_X0 Address: 32 (20h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_DATA_X[7:0] FUNCTION Lower byte of Accel X-axis data ACCEL_DATA_Y1 Name: ACCEL_DATA_Y1 Address: 33 (21h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_DATA_Y[15:8] Document Number: DS-000401 Revision: 1.2 FUNCTION Upper byte of Accel Y-axis data Page 70 of 119 IIM-42652 ACCEL_DATA_Y0 Name: ACCEL_DATA_Y0 Address: 34 (22h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_DATA_Y[7:0] FUNCTION Lower byte of Accel Y-axis data ACCEL_DATA_Z1 Name: ACCEL_DATA_Z1 Address: 35 (23h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_DATA_Z[15:8] FUNCTION Upper byte of Accel Z-axis data ACCEL_DATA_Z0 Name: ACCEL_DATA_Z0 Address: 36 (24h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_DATA_Z[7:0] FUNCTION Lower byte of Accel Z-axis data GYRO_DATA_X1 Name: GYRO_DATA_X1 Address: 37 (25h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_DATA_X[15:8] FUNCTION Upper byte of Gyro X-axis data GYRO_DATA_X0 Name: GYRO_DATA_X0 Address: 38 (26h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_DATA_X[7:0] Document Number: DS-000401 Revision: 1.2 FUNCTION Lower byte of Gyro X-axis data Page 71 of 119 IIM-42652 GYRO_DATA_Y1 Name: GYRO_DATA_Y1 Address: 39 (27h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_DATA_Y[15:8] FUNCTION Upper byte of Gyro Y-axis data GYRO_DATA_Y0 Name: GYRO_DATA_Y0 Address: 40 (28h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_DATA_Y[7:0] FUNCTION Lower byte of Gyro Y-axis data GYRO_DATA_Z1 Name: GYRO_DATA_Z1 Address: 41 (29h) Serial IF: SYNCR Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_DATA_Z[15:8] FUNCTION Upper byte of Gyro Z-axis data GYRO_DATA_Z0 Name: GYRO_DATA_Z0 Address: 42 (2Ah) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_DATA_Z[7:0] FUNCTION Lower byte of Gyro Z-axis data TMST_FSYNCH Name: TMST_FSYNCH Address: 43 (2Bh) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 TMST_FSYNC_DATA[15:8] Document Number: DS-000401 Revision: 1.2 FUNCTION Stores the upper byte of the time delta from the rising edge of FSYNC to the latest ODR until the UI Interface reads the FSYNC tag in the status register Page 72 of 119 IIM-42652 TMST_FSYNCL Name: TMST_FSYNCL Address: 44 (2Ch) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 TMST_FSYNC_DATA[7:0] FUNCTION Stores the lower byte of the time delta from the rising edge of FSYNC to the latest ODR until the UI Interface reads the FSYNC tag in the status register INT_STATUS Name: INT_STATUS Address: 45 (2Dh) Serial IF: R/C Reset value: 0x10 Clock Domain: SCLK_UI BIT NAME 7 6 UI_FSYNC_INT 5 PLL_RDY_INT 4 RESET_DONE_INT 3 DATA_RDY_INT 2 FIFO_THS_INT 1 FIFO_FULL_INT 0 AGC_RDY_INT FUNCTION Reserved This bit automatically sets to 1 when a UI FSYNC interrupt is generated. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when a PLL Ready interrupt is generated. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when software reset is complete. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when the FIFO buffer reaches the threshold value. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when the FIFO buffer is full. The bit clears to 0 after the register has been read. This bit automatically sets to 1 when an AGC Ready interrupt is generated. The bit clears to 0 after the register has been read. FIFO_COUNTH Name: FIFO_COUNTH Address: 46 (2Eh) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 FIFO_COUNT[15:8] Document Number: DS-000401 Revision: 1.2 FUNCTION High Bits, count indicates the number of records or bytes available in FIFO according to FIFO_COUNT_REC setting. Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH and FIFO_COUNTL. Page 73 of 119 IIM-42652 FIFO_COUNTL Name: FIFO_COUNTL Address: 47 (2Fh) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 FIFO_COUNT[7:0] FUNCTION Low Bits, count indicates the number of records or bytes available in FIFO according to FIFO_COUNT_REC setting. Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL. FIFO_DATA Name: FIFO_DATA Address: 48 (30h) Serial IF: R Reset value: 0xFF Clock Domain: SCLK_UI BIT NAME 7:0 FIFO_DATA FUNCTION FIFO data port APEX_DATA0 Name: APEX_DATA0 Address: 49 (31h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME STEP_CNT[7:0] (when Pedometer is enabled) 7:0 FF_DUR[7:0] (when Freefall Detection is enabled) FUNCTION Pedometer Output: Lower byte of Step Count measured by pedometer Lower byte of Freefall Duration APEX_DATA1 Name: APEX_DATA1 Address: 50 (32h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME STEP_CNT[15:8] (when Pedometer is enabled) 7:0 FF_DUR[15:8] (when Freefall Detection is enabled) Document Number: DS-000401 Revision: 1.2 FUNCTION Pedometer Output: Upper byte of Step Count measured by pedometer Upper byte of Freefall Duration Page 74 of 119 IIM-42652 APEX_DATA2 Name: APEX_DATA2 Address: 51 (33h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 STEP_CADENCE FUNCTION Pedometer Output: Walk/run cadency in number of samples. Format is u6.2. e.g. At 50Hz ODR and 2Hz walk frequency, the cadency is 25 samples. The register will output 100. APEX_DATA3 Name: APEX_DATA3 Address: 52 (34h) Serial IF: R Reset value: 0x04 Clock Domain: SCLK_UI BIT NAME 7:3 2 1:0 DMP_IDLE ACTIVITY_CLASS Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Indicates DMP is running 1: Indicates DMP is idle Pedometer Output: Detected activity 00: Unknown 01: Walk 10: Run 11: Reserved Page 75 of 119 IIM-42652 APEX_DATA4 Name: APEX_DATA4 Address: 53 (35h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:5 4:3 TAP_NUM 2:1 TAP_AXIS 0 TAP_DIR FUNCTION Reserved Tap Detection Output: Number of taps in the current Tap event 00: No tap 01: Single tap 10: Double tap 11: Reserved Tap Detection Output: Represents the accelerometer axis on which tap energy is concentrated 00: X-axis 01: Y-axis 10: Z-axis 11: Reserved Tap Detection Output: Polarity of tap pulse 0: Current accelerometer value – Previous accelerometer value is a positive value 1: Current accelerometer value – Previous accelerometer value is a negative value or zero APEX_DATA5 Name: APEX_DATA5 Address: 54 (36h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 - 5:0 DOUBLE_TAP_TIMING Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved DOUBLE_TAP_TIMING measures the time interval between the two taps when double tap is detected. It counts every 16 accelerometer samples as one unit between the 2 tap pulses. Therefore, the value is related to the accelerometer ODR. Time in seconds = DOUBLE_TAP_TIMING * 16 / ODR For example, if the accelerometer ODR is 500 Hz, and the DOUBLE_TAP_TIMING register reading is 6, the time interval value is 6*16/500 = 0.192 seconds. Page 76 of 119 IIM-42652 INT_STATUS2 Name: INT_STATUS2 Address: 55 (37h) Serial IF: R/C Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 3 SMD_INT 2 WOM_Z_INT 1 WOM_Y_INT 0 WOM_X_INT FUNCTION Reserved Significant Motion Detection Interrupt, clears on read Wake on Motion Interrupt on Z-axis, clears on read Wake on Motion Interrupt on Y-axis, clears on read Wake on Motion Interrupt on X-axis, clears on read INT_STATUS3 Name: INT_STATUS3 Address: 56 (38h) Serial IF: R/C Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 STEP_DET_INT 4 STEP_CNT_OVF_INT 3 TILT_DET_INT 2 1 FF_DET_INT 0 TAP_DET_INT FUNCTION Reserved Step Detection Interrupt, clears on read Step Count Overflow Interrupt, clears on read Tilt Detection Interrupt, clears on read Reserved Freefall Interrupt, clears on read Tap Detection Interrupt, clears on read SIGNAL_PATH_RESET Name: SIGNAL_PATH_RESET Address: 75 (4Bh) Serial IF: W/C Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 6 DMP_INIT_EN 5 DMP_MEM_RESET_EN 4 3 ABORT_AND_RESET 2 TMST_STROBE 1 0 FIFO_FLUSH - Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved When this bit is set to 1, the DMP is enabled When this bit is set to 1, the DMP memory is reset Reserved When this bit is set to 1, the signal path is reset by restarting the ODR counter and signal path controls When this bit is set to 1, the time stamp counter is latched into the time stamp register. This is a write on clear bit. When set to 1, FIFO will get flushed. Reserved Page 77 of 119 IIM-42652 INTF_CONFIG0 Name: INTF_CONFIG0 Address: 76 (4Ch) Serial IF: R/W Reset value: 0x30 Clock Domain: SCLK_UI BIT NAME FUNCTION Setting this bit to 0: In order to signal an invalid sample, and to differentiate it from a valid sample based on values only: Sense Registers: • Do not receive invalid samples. They hold the last valid sample. Repeated reading before new sample received will yield copies of the last valid sample. • Valid samples of values -32768, -32767 are replaced with -32766 • FSYNC Tagging can modify the least significant bit and further limit values (see section 12.8). 7 FIFO_HOLD_LAST_DATA_EN FIFO: • 16-bit FIFO packet: Same as Sense Registers, except: o FSYNC tagging is not applied to data in FIFO. • 20-bit FIFO packet: o Invalid samples are indicated with the value -524288 o Valid samples in {-524288 to -524258} are replaced by 524256 o Valid Gyro samples: All Even numbers in { -524256 to +524286} o Valid Accel samples: All numbers divisible by 4 in {-524256 to +524284} o FSYNC tagging is not applied to data in FIFO. Setting this bit to 1: Sense registers: • Do not receive invalid samples. They hold the last valid sample. Repeated reading before new sample received will yield copies of the last valid sample. • FSYNC Tagging can modify the least significant bit and further limit values (see section 12.8). FIFO: • Invalid sample will get copy of last valid sample • 16-bit FIFO packet: Same as Sense Registers, except: o FSYNC tagging is not applied to data in FIFO. • 20-bit FIFO packet: o Valid Gyro samples: All Even numbers in {-524288 to +524286} o - Valid Accel samples: All numbers divisible by 4 in {-524288 to +524284} Document Number: DS-000401 Revision: 1.2 Page 78 of 119 IIM-42652 Name: INTF_CONFIG0 Address: 76 (4Ch) Serial IF: R/W Reset value: 0x30 Clock Domain: SCLK_UI BIT NAME 6 FIFO_COUNT_REC 5 FIFO_COUNT_ENDIAN 4 SENSOR_DATA_ENDIAN 3:2 - 1:0 UI_SIFS_CFG FUNCTION 0: FIFO count is reported in bytes 1: FIFO count is reported in records (1 record = 16 bytes for header + gyro + accel + temp sensor data + time stamp, or 8 bytes for header + gyro/accel + temp sensor data) 0: FIFO count is reported in Little Endian format 1: FIFO count is reported in Big Endian format (default) 0: Sensor data is reported in Little Endian format 1: Sensor data is reported in Big Endian format (default) Reserved 0x: Reserved 10: Disable SPI 11: Disable I2C Invalid Data Generation: FIFO/Sense Registers may contain invalid data under the following conditions: a) From power on reset to first ODR sample of any sensor (accel, gyro, temp sensor) b) When any sensor is disabled (accel, gyro, temp sensor) c) When accel and gyro are enabled with different ODRs. In this case, the sensor with lower ODR will generate invalid samples when it has no new data. Invalid data can take special values or can hold last valid sample received. For -32768 to be used as a flag for invalid accel/gyro samples, the valid accel/gyro sample range is limited in such case as well. Bit 7 of INTF_CONFIG0 controls what values invalid (and valid) samples can take as shown above. INTF_CONFIG1 Name: INTF_CONFIG1 Address: 77 (4Dh) Serial IF: R/W Reset value: 0x91 Clock Domain: SCLK_UI BIT NAME 7:4 3 ACCEL_LP_CLK_SEL 2 RTC_MODE 1:0 CLKSEL Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Accelerometer LP mode uses Wake Up oscillator clock 1: Accelerometer LP mode uses RC oscillator clock 0: No input RTC clock is required 1: RTC clock input is required 00: Always select internal RC oscillator 01: Select PLL when available, else select RC oscillator (default) 10: Reserved 11: Disable all clocks Page 79 of 119 IIM-42652 PWR_MGMT0 Name: PWR_MGMT0 Address: 78 (4Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 TEMP_DIS 4 IDLE 3:2 1:0 GYRO_MODE ACCEL_MODE FUNCTION Reserved 0: Temperature sensor is enabled (default) 1: Temperature sensor is disabled If this bit is set to 1, the RC oscillator is powered on even if Accel and Gyro are powered off. Nominally this bit is set to 0, so when Accel and Gyro are powered off, the chip will go to OFF state, since the RC oscillator will also be powered off 00: Turns gyroscope off (default) 01: Places gyroscope in Standby Mode 10: Reserved 11: Places gyroscope in Low Noise (LN) Mode Gyroscope needs to be kept ON for a minimum of 45ms. When transitioning from OFF to any of the other modes, do not issue any register writes for 200µs. 00: Turns accelerometer off (default) 01: Turns accelerometer off 10: Places accelerometer in Low Power (LP) Mode 11: Places accelerometer in Low Noise (LN) Mode When transitioning from OFF to any of the other modes, do not issue any register writes for 200µs. Document Number: DS-000401 Revision: 1.2 Page 80 of 119 IIM-42652 GYRO_CONFIG0 Name: GYRO_CONFIG0 Address: 79 (4Fh) Serial IF: R/W Reset value: 0x06 Clock Domain: SCLK_UI BIT NAME 7:5 4 3:0 GYRO_FS_SEL - GYRO_ODR Document Number: DS-000401 Revision: 1.2 FUNCTION Full scale select for gyroscope UI interface output 000: ±2000dps (default) 001: ±1000dps 010: ±500dps 011: ±250dps 100: ±125dps 101: ±62.5dps 110: ±31.25dps 111: ±15.625dps Reserved Gyroscope ODR selection for UI interface output 0000: Reserved 0001: 32kHz 0010: 16kHz 0011: 8kHz 0100: 4kHz 0101: 2kHz 0110: 1kHz (default) 0111: 200Hz 1000: 100Hz 1001: 50Hz 1010: 25Hz 1011: 12.5Hz 1100: Reserved 1101: Reserved 1110: Reserved 1111: 500Hz Page 81 of 119 IIM-42652 ACCEL_CONFIG0 Name: ACCEL_CONFIG0 Address: 80 (50h) Serial IF: R/W Reset value: 0x06 Clock Domain: SCLK_UI BIT NAME 7:5 4 3:0 ACCEL_FS_SEL - ACCEL_ODR Document Number: DS-000401 Revision: 1.2 FUNCTION Full scale select for accelerometer UI interface output 000: ±16g (default) 001: ±8g 010: ±4g 011: ±2g 100: Reserved 101: Reserved 110: Reserved 111: Reserved Reserved Accelerometer ODR selection for UI interface output 0000: Reserved 0001: 32kHz 0010: 16kHz 0011: 8kHz (LN mode) 0100: 4kHz (LN mode) 0101: 2kHz (LN mode) 0110: 1kHz (LN mode) (default) 0111: 200Hz (LP or LN mode) 1000: 100Hz (LP or LN mode) 1001: 50Hz (LP or LN mode) 1010: 25Hz (LP or LN mode) 1011: 12.5Hz (LP or LN mode) 1100: 6.25Hz (LP mode) 1101: 3.125Hz (LP mode) 1110: 1.5625Hz (LP mode) 1111: 500Hz (LP or LN mode) Page 82 of 119 IIM-42652 GYRO_CONFIG1 Name: GYRO_CONFIG1 Address: 81 (51h) Serial IF: R/W Reset value: 0x16 Clock Domain: SCLK_UI BIT NAME 7:5 4 TEMP_FILT_BW - 3:2 GYRO_UI_FILT_ORD 1:0 GYRO_DEC2_M2_ORD Document Number: DS-000401 Revision: 1.2 FUNCTION Sets the bandwidth of the temperature signal DLPF 000: DLPF BW = 4000Hz; DLPF Latency = 0.125ms (default) 001: DLPF BW = 170Hz; DLPF Latency = 1ms 010: DLPF BW = 82Hz; DLPF Latency = 2ms 011: DLPF BW = 40Hz; DLPF Latency = 4ms 100: DLPF BW = 20Hz; DLPF Latency = 8ms 101: DLPF BW = 10Hz; DLPF Latency = 16ms 110: DLPF BW = 5Hz; DLPF Latency = 32ms 111: DLPF BW = 5Hz; DLPF Latency = 32ms Reserved Selects order of GYRO UI filter 00: 1st Order 01: 2nd Order 10: 3rd Order 11: Reserved Selects order of GYRO DEC2_M2 Filter 00: Reserved 01: Reserved 10: 3rd Order 11: Reserved Page 83 of 119 IIM-42652 GYRO_ACCEL_CONFIG0 Name: GYRO_ACCEL_CONFIG0 Address: 82 (52h) Serial IF: R/W Reset value: 0x11 Clock Domain: SCLK_UI BIT NAME 7:4 3:0 ACCEL_UI_FILT_BW GYRO_UI_FILT_BW Document Number: DS-000401 Revision: 1.2 FUNCTION LN Mode: Bandwidth for Accel LPF 0 BW=ODR/2 1 BW=max(400Hz, ODR)/4 (default) 2 BW=max(400Hz, ODR)/5 3 BW=max(400Hz, ODR)/8 4 BW=max(400Hz, ODR)/10 5 BW=max(400Hz, ODR)/16 6 BW=max(400Hz, ODR)/20 7 BW=max(400Hz, ODR)/40 8 to 13: Reserved 14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2 runs at max(400Hz, ODR) 15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2 runs at max(200Hz, 8*ODR) LP Mode: 0 Reserved 1 1x AVG filter (default) 2 to 5 Reserved 6 16x AVG filter 7 to 15 Reserved LN Mode: Bandwidth for Gyro LPF 0 BW=ODR/2 1 BW=max(400Hz, ODR)/4 (default) 2 BW=max(400Hz, ODR)/5 3 BW=max(400Hz, ODR)/8 4 BW=max(400Hz, ODR)/10 5 BW=max(400Hz, ODR)/16 6 BW=max(400Hz, ODR)/20 7 BW=max(400Hz, ODR)/40 8 to 13: Reserved 14 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2 runs at max(400Hz, ODR) 15 Low Latency option: Trivial decimation @ ODR of Dec2 filter output. Dec2 runs at max(200Hz, 8*ODR) Page 84 of 119 IIM-42652 ACCEL_CONFIG1 Name: ACCEL_CONFIG1 Address: 83 (53h) Serial IF: R/W Reset value: 0x0D Clock Domain: SCLK_UI BIT NAME 7:5 4:3 ACCEL_UI_FILT_ORD 2:1 ACCEL_DEC2_M2_ORD 0 - FUNCTION Reserved Selects order of ACCEL UI filter 00: 1st Order 01: 2nd Order 10: 3rd Order 11: Reserved Order of Accelerometer DEC2_M2 filter 00: Reserved 01: Reserved 10: 3rd order 11: Reserved Reserved TMST_CONFIG Name: TMST_CONFIG Address: 84 (54h) Serial IF: R/W Reset value: 0x23 Clock Domain: SCLK_UI BIT NAME 7:5 4 TMST_TO_REGS_EN 3 TMST_RES 2 TMST_DELTA_EN 1 TMST_FSYNC_EN 0 TMST_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: TMST_VALUE[19:0] read always returns 0s 1: TMST_VALUE[19:0] read returns timestamp value Time Stamp resolution: When set to 0 (default), time stamp resolution is 1 µs. When set to 1: If RTC is disabled, resolution is 16 µs. If RTC is enabled, resolution is 1 RTC clock period Time Stamp delta enable: When set to 1, the time stamp field contains the measurement of time since the last occurrence of ODR. Time Stamp register FSYNC enable (default). When set to 1, the contents of the Timestamp feature of FSYNC is enabled. The user also needs to select FIFO_TMST_FSYNC_EN in order to propagate the timestamp value to the FIFO. 0: Time Stamp register disable 1: Time Stamp register enable (default) Page 85 of 119 IIM-42652 APEX_CONFIG0 Name: APEX_CONFIG0 Address: 86 (56h) Serial IF: R/W Reset value: 0x82 Clock Domain: SCLK_UI BIT NAME 7 DMP_POWER_SAVE 6 TAP_ENABLE 5 PED_ENABLE 4 TILT_ENABLE 3 - 2 FF_ENABLE 1:0 DMP_ODR FUNCTION 0: DMP power save mode not active 1: DMP power save mode active (default) 0: Tap Detection not enabled 1: Tap Detection enabled when accelerometer ODR is set to one of the ODR values supported by Tap Detection (200Hz, 500Hz, 1kHz) 0: Pedometer not enabled 1: Pedometer enabled 0: Tilt Detection not enabled 1: Tilt Detection enabled Reserved 0: Freefall Detection not enabled 1: Freefall Detection enabled 00: 25Hz 01: 500 Hz 10: 50Hz 11: 100 Hz SMD_CONFIG Name: SMD_CONFIG Address: 87 (57h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 3 WOM_INT_MODE 2 WOM_MODE 1:0 SMD_MODE Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Set WoM interrupt on the OR of all enabled accelerometer thresholds 1: Set WoM interrupt on the AND of all enabled accelerometer threshold 0: Initial sample is stored. Future samples are compared to initial sample 1: Compare current sample to previous sample 00: SMD disabled 01: WOM mode 10: SMD short (1 sec wait) An SMD event is detected when two WOM are detected 1 sec apart 11: SMD long (3 sec wait) An SMD event is detected when two WOM are detected 3 sec apart Page 86 of 119 IIM-42652 FIFO_CONFIG1 Name: FIFO_CONFIG1 Address: 95 (5Fh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 6 FIFO_RESUME_PARTIAL_RD 5 FIFO_WM_GT_TH 4 FIFO_HIRES_EN 3 2 1 0 FIFO_TMST_FSYNC_EN FIFO_TEMP_EN FIFO_GYRO_EN FIFO_ACCEL_EN FUNCTION Reserved 0: Partial FIFO read disabled, requires re-reading of the entire FIFO 1: FIFO read can be partial, and resume from last read point Trigger FIFO watermark interrupt on every ODR (DMA write) if FIFO_COUNT ≥ FIFO_WM_TH 0: Default setting; Sensor data have regular resolution 1: Sensor data in FIFO will have extended resolution enabling the 20 Bytes packet Must be set to 1 for all FIFO use cases when FSYNC is used Enable temperature sensor packets to go to FIFO Enable gyroscope packets to go to FIFO Enable accelerometer packets to go to FIFO FIFO_CONFIG2 Name: FIFO_CONFIG2 Address: 96 (60h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 FIFO_WM[7:0] FUNCTION Lower bits of FIFO watermark. Generate interrupt when the FIFO reaches or exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_REC setting. Interrupt only fires once. This register should be set to non-zero value, before choosing this interrupt source. FIFO_CONFIG3 Name: FIFO_CONFIG3 Address: 97 (61h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 3:0 FIFO_WM[11:8] Note: Do not set FIFO_WM to value 0. Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved Upper bits of FIFO watermark. Generate interrupt when the FIFO reaches or exceeds FIFO_WM size in bytes or records according to FIFO_COUNT_REC setting. Interrupt only fires once. This register should be set to non-zero value, before choosing this interrupt source. Page 87 of 119 IIM-42652 FSYNC_CONFIG Name: FSYNC_CONFIG Address: 98 (62h) Serial IF: R/W Reset value: 0x10 Clock Domain: SCLK_UI BIT NAME 7 - 6:4 FSYNC_UI_SEL 3:2 - 1 FSYNC_UI_FLAG_CLEAR_SE L 0 FSYNC_POLARITY FUNCTION Reserved 000: Do not tag FSYNC flag 001: Tag FSYNC flag to TEMP_OUT LSB 010: Tag FSYNC flag to GYRO_XOUT LSB 011: Tag FSYNC flag to GYRO_YOUT LSB 100: Tag FSYNC flag to GYRO_ZOUT LSB 101: Tag FSYNC flag to ACCEL_XOUT LSB 110: Tag FSYNC flag to ACCEL_YOUT LSB 111: Tag FSYNC flag to ACCEL_ZOUT LSB Reserved 0: FSYNC flag is cleared when UI sensor register is updated 1: FSYNC flag is cleared when UI interface reads the sensor register LSB of FSYNC tagged axis 0: Start from Rising edge of FSYNC pulse to measure FSYNC interval 1: Start from Falling edge of FSYNC pulse to measure FSYNC interval INT_CONFIG0 Name: INT_CONFIG0 Address: 99 (63h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5:4 UI_DRDY_INT_CLEAR 3:2 FIFO_THS_INT_CLEAR 1:0 FIFO_FULL_INT_CLEAR Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved Data Ready Interrupt Clear Option (latched mode) 00: Clear on Status Bit Read (default) 01: Clear on Status Bit Read 10: Clear on Sensor Register Read 11: Clear on Status Bit Read AND on Sensor Register read FIFO Threshold Interrupt Clear Option (latched mode) 00: Clear on Status Bit Read (default) 01: Clear on Status Bit Read 10: Clear on FIFO data 1Byte Read 11: Clear on Status Bit Read AND on FIFO data 1 byte read FIFO Full Interrupt Clear Option (latched mode) 00: Clear on Status Bit Read (default) 01: Clear on Status Bit Read 10: Clear on FIFO data 1Byte Read 11: Clear on Status Bit Read AND on FIFO data 1 byte read Page 88 of 119 IIM-42652 INT_CONFIG1 Name: INT_CONFIG1 Address: 100 (64h) Serial IF: R/W Reset value: 0x10 Clock Domain: SCLK_UI BIT NAME 7 6 INT_TPULSE_DURATION 5 INT_TDEASSERT_DISABLE 4 INT_ASYNC_RESET 3:0 - FUNCTION Reserved Interrupt pulse duration 0: Interrupt pulse duration is 100µs. Use only if ODR < 4kHz. (Default) 1: Interrupt pulse duration is 8 µs. Required if ODR ≥ 4kHz, optional for ODR < 4kHz. Interrupt de-assertion duration 0: The interrupt de-assertion duration is set to a minimum of 100µs. Use only if ODR < 4kHz. (Default) 1: Disables de-assert duration. Required if ODR ≥ 4kHz, optional for ODR < 4kHz. User should change setting to 0 from default setting of 1, for proper INT1 and INT2 pin operation Reserved INT_SOURCE0 Name: INT_SOURCE0 Address: 101 (65h) Serial IF: R/W Reset value: 0x10 Clock Domain: SCLK_UI BIT NAME 7 6 UI_FSYNC_INT1_EN 5 PLL_RDY_INT1_EN 4 RESET_DONE_INT1_EN 3 UI_DRDY_INT1_EN 2 FIFO_THS_INT1_EN 1 FIFO_FULL_INT1_EN 0 UI_AGC_RDY_INT1_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: UI FSYNC interrupt not routed to INT1 1: UI FSYNC interrupt routed to INT1 0: PLL ready interrupt not routed to INT1 1: PLL ready interrupt routed to INT1 0: Reset done interrupt not routed to INT1 1: Reset done interrupt routed to INT1 0: UI data ready interrupt not routed to INT1 1: UI data ready interrupt routed to INT1 0: FIFO threshold interrupt not routed to INT1 1: FIFO threshold interrupt routed to INT1 0: FIFO full interrupt not routed to INT1 1: FIFO full interrupt routed to INT1 0: UI AGC ready interrupt not routed to INT1 1: UI AGC ready interrupt routed to INT1 Page 89 of 119 IIM-42652 INT_SOURCE1 Name: INT_SOURCE1 Address: 102 (66h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 I3C_PROTOCOL_ERROR_IN 6 T1_EN 5:4 3 SMD_INT1_EN 2 WOM_Z_INT1_EN 1 WOM_Y_INT1_EN 0 WOM_X_INT1_EN FUNCTION Reserved 0: I3CSM protocol error interrupt not routed to INT1 1: I3CSM protocol error interrupt routed to INT1 Reserved 0: SMD interrupt not routed to INT1 1: SMD interrupt routed to INT1 0: Z-axis WOM interrupt not routed to INT1 1: Z-axis WOM interrupt routed to INT1 0: Y-axis WOM interrupt not routed to INT1 1: Y-axis WOM interrupt routed to INT1 0: X-axis WOM interrupt not routed to INT1 1: X-axis WOM interrupt routed to INT1 INT_SOURCE3 Name: INT_SOURCE3 Address: 104 (68h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 6 UI_FSYNC_INT2_EN 5 PLL_RDY_INT2_EN 4 RESET_DONE_INT2_EN 3 UI_DRDY_INT2_EN 2 FIFO_THS_INT2_EN 1 FIFO_FULL_INT2_EN 0 UI_AGC_RDY_INT2_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: UI FSYNC interrupt not routed to INT2 1: UI FSYNC interrupt routed to INT2 0: PLL ready interrupt not routed to INT2 1: PLL ready interrupt routed to INT2 0: Reset done interrupt not routed to INT2 1: Reset done interrupt routed to INT2 0: UI data ready interrupt not routed to INT2 1: UI data ready interrupt routed to INT2 0: FIFO threshold interrupt not routed to INT2 1: FIFO threshold interrupt routed to INT2 0: FIFO full interrupt not routed to INT2 1: FIFO full interrupt routed to INT2 0: UI AGC ready interrupt not routed to INT2 1: UI AGC ready interrupt routed to INT2 Page 90 of 119 IIM-42652 INT_SOURCE4 Name: INT_SOURCE4 Address: 105 (69h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 I3C_PROTOCOL_ERROR_IN 6 T2_EN 5:4 3 SMD_INT2_EN 2 WOM_Z_INT2_EN 1 WOM_Y_INT2_EN 0 WOM_X_INT2_EN FUNCTION Reserved 0: I3CSM protocol error interrupt not routed to INT2 1: I3CSM protocol error interrupt routed to INT2 Reserved 0: SMD interrupt not routed to INT2 1: SMD interrupt routed to INT2 0: Z-axis WOM interrupt not routed to INT2 1: Z-axis WOM interrupt routed to INT2 0: Y-axis WOM interrupt not routed to INT2 1: Y-axis WOM interrupt routed to INT2 0: X-axis WOM interrupt not routed to INT2 1: X-axis WOM interrupt routed to INT2 FIFO_LOST_PKT0 Name: FIFO_LOST_PKT0 Address: 108 (6Ch) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 FIFO_LOST_PKT_CNT[7:0] FUNCTION Low byte, number of packets lost in the FIFO FIFO_LOST_PKT1 Name: FIFO_LOST_PKT1 Address: 109 (6Dh) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 FIFO_LOST_PKT_CNT[15:8] Document Number: DS-000401 Revision: 1.2 FUNCTION High byte, number of packets lost in the FIFO Page 91 of 119 IIM-42652 SELF_TEST_CONFIG Name: SELF_TEST_CONFIG Address: 112 (70h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 6 ACCEL_ST_POWER 5 4 3 2 1 0 EN_AZ_ST EN_AY_ST EN_AX_ST EN_GZ_ST EN_GY_ST EN_GX_ST FUNCTION Reserved Set to 1 for accel self-test Otherwise set to 0; Set to 0 after self-test is completed Enable Z-accel self-test Enable Y-accel self-test Enable X-accel self-test Enable Z-gyro self-test Enable Y-gyro self-test Enable X-gyro self-test WHO_AM_I Name: WHO_AM_I Address: 117 (75h) Serial IF: R Reset value: 0x6F Clock Domain: SCLK_UI BIT NAME 7:0 WHOAMI FUNCTION Register to indicate to user which device is being accessed Description: This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the register is 0x6F. This is different from the I2C address of the device as seen on the slave I2C controller by the applications processor. REG_BANK_SEL Note: This register is accessible from all register banks Name: REG_BANK_SEL Address: 118 (76h) Serial IF: R/W Reset value: 0x00 Clock Domain: ALL BIT NAME 7:3 - 2:0 BANK_SEL Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved Register bank selection 000: Bank 0 (default) 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101: Reserved 110: Reserved 111: Reserved Page 92 of 119 IIM-42652 15 USER BANK 1 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within USR Bank 1. SENSOR_CONFIG0 Name: SENSOR_CONFIG0 Address: 03 (03h) Serial IF: R/W Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:6 5 ZG_DISABLE 4 YG_DISABLE 3 XG_DISABLE 2 ZA_DISABLE 1 YA_DISABLE 0 XA_DISABLE FUNCTION Reserved 0: Z gyroscope is on 1: Z gyroscope is disabled 0: Y gyroscope is on 1: Y gyroscope is disabled 0: X gyroscope is on 1: X gyroscope is disabled 0: Z accelerometer is on 1: Z accelerometer is disabled 0: Y accelerometer is on 1: Y accelerometer is disabled 0: X accelerometer is on 1: X accelerometer is disabled GYRO_CONFIG_STATIC2 Name: GYRO_CONFIG_STATIC2 Address: 11 (0Bh) Serial IF: R/W Reset value: 0xA0 Clock Domain: SCLK_UI BIT NAME 7:2 1 GYRO_AAF_DIS 0 GYRO_NF_DIS FUNCTION Reserved 0: Enable Anti-Aliasing/Low Pass Filter 1: Disable Anti-Aliasing/Low Pass Filter 0: Enable Notch Filter 1: Disable Notch Filter GYRO_CONFIG_STATIC3 Name: GYRO_CONFIG_STATIC3 Address: 12 (0Ch) Serial IF: R/W Reset value: 0x0D Clock Domain: SCLK_UI BIT NAME 7:6 5:0 GYRO_AAF_DELT Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved Controls bandwidth of the gyroscope anti-alias filter See section 5.3 for details Page 93 of 119 IIM-42652 GYRO_CONFIG_STATIC4 Name: GYRO_CONFIG_STATIC4 Address: 13 (0Dh) Serial IF: R/W Reset value: 0xAA Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_AAF_DELTSQR[7:0] FUNCTION Controls bandwidth of the gyroscope anti-alias filter See section 5.3 for details GYRO_CONFIG_STATIC5 Name: GYRO_CONFIG_STATIC5 Address: 14 (0Eh) Serial IF: R/W Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7:4 GYRO_AAF_BITSHIFT 3:0 GYRO_AAF_DELTSQR[11:8] FUNCTION Controls bandwidth of the gyroscope anti-alias filter See section 5.3 for details Controls bandwidth of the gyroscope anti-alias filter See section for details GYRO_CONFIG_STATIC6 Name: GYRO_CONFIG_STATIC6 Address: 15 (0Fh) Serial IF: R/W Reset value: 0xXX (Factory trimmed on an individual device basis) Clock Domain: SCLK_UI BIT NAME FUNCTION Used for gyroscope X-axis notch filter frequency selection 7:0 GYRO_X_NF_COSWZ[7:0] See section 5.1 for details GYRO_CONFIG_STATIC7 Name: GYRO_CONFIG_STATIC7 Address: 16 (10h) Serial IF: R/W Reset value: 0xXX (Factory trimmed on an individual device basis) Clock Domain: SCLK_UI BIT NAME FUNCTION Used for gyroscope Y-axis notch filter frequency selection 7:0 GYRO_Y_NF_COSWZ[7:0] See section 5.1 for details Document Number: DS-000401 Revision: 1.2 Page 94 of 119 IIM-42652 GYRO_CONFIG_STATIC8 Name: GYRO_CONFIG_STATIC8 Address: 17 (11h) Serial IF: R/W Reset value: 0xXX (Factory trimmed on an individual device basis) Clock Domain: SCLK_UI BIT NAME FUNCTION Used for gyroscope Z-axis notch filter frequency selection 7:0 GYRO_Z_NF_COSWZ[7:0] See section 5.1 for details GYRO_CONFIG_STATIC9 Name: GYRO_CONFIG_STATIC9 Address: 18 (12h) Serial IF: R/W Reset value: 0xXX (Factory trimmed on an individual device basis) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:6 Reserved Used for gyroscope Z-axis notch filter frequency selection 5 GYRO_Z_NF_COSWZ_SEL[0] See section 5.1 for details Used for gyroscope Y-axis notch filter frequency selection 4 GYRO_Y_NF_COSWZ_SEL[0] See section 5.1 for details Used for gyroscope X-axis notch filter frequency selection 3 GYRO_X_NF_COSWZ_SEL[0] See section 5.1 for details Used for gyroscope Z-axis notch filter frequency selection 2 GYRO_Z_NF_COSWZ[8] See section 5.1 for details Used for gyroscope Y-axis notch filter frequency selection 1 GYRO_Y_NF_COSWZ[8] See section 5.1 for details Used for gyroscope X-axis notch filter frequency selection 0 GYRO_X_NF_COSWZ[8] See section 5.1 for details GYRO_CONFIG_STATIC10 Name: GYRO_CONFIG_STATIC10 Address: 19 (13h) Serial IF: R/W Reset value: 0x11 Clock Domain: SCLK_UI BIT NAME 7 6:4 GYRO_NF_BW_SEL 3:1 GYRO_HPF_BW_IND 0 GYRO_HPF_ORD_IND Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved Selects bandwidth for gyroscope notch filter See section 5.1 for details Selects HPF 3dB cutoff frequency bandwidth See section 5.6 for details Selects HPF filter order (see section 5.6 for details) 0: 1st order HPF 1: 2nd order HPF Page 95 of 119 IIM-42652 XG_ST_DATA Name: XG_ST_DATA Address: 95 (5Fh) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:0 XG_ST_DATA X-gyro self-test data YG_ST_DATA Name: YG_ST_DATA Address: 96 (60h) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:0 YG_ST_DATA Y-gyro self-test data ZG_ST_DATA Name: ZG_ST_DATA Address: 97 (61h) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:0 ZG_ST_DATA Z-gyro self-test data TMSTVAL0 Name: TMSTVAL0 Address: 98 (62h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 TMST_VALUE[7:0] Document Number: DS-000401 Revision: 1.2 FUNCTION When TMST_STROBE is programmed, the current value of the internal counter is latched to this register. Allows the full 20-bit precision of the time stamp to be read back. Page 96 of 119 IIM-42652 TMSTVAL1 Name: TMSTVAL1 Address: 99 (63h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 TMST_VALUE[15:8] FUNCTION When TMST_STROBE is programmed, the current value of the internal counter is latched to this register. Allows the full 20-bit precision of the time stamp to be read back. TMSTVAL2 Name: TMSTVAL2 Address: 100 (64h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 3:0 TMST_VALUE[19:16] FUNCTION Reserved When TMST_STROBE is programmed, the current value of the internal counter is latched to this register. Allows the full 20-bit precision of the time stamp to be read back. INTF_CONFIG4 Name: INTF_CONFIG4 Address: 122 (7Ah) Serial IF: R/W Reset value: 0x03 Clock Domain: SCLK_UI BIT NAME 7 6 5:2 I3C_BUS_MODE - 1 SPI_AP_4WIRE 0 - Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Device is on a bus with I2C and I3CSM devices 1: Device is on a bus with I3CSM devices only Reserved 0: AP interface uses 3-wire SPI mode 1: AP interface uses 4-wire SPI mode (default) Reserved Page 97 of 119 IIM-42652 INTF_CONFIG5 Name: INTF_CONFIG5 Address: 123 (7Bh) Serial IF: R/W Reset value: 0x20 Clock Domain: SCLK_UI BIT NAME 7:3 2:1 0 PIN9_FUNCTION - FUNCTION Reserved Selects among the following functionalities for pin 9 00: INT2 01: FSYNC 10: CLKIN 11: Reserved Reserved INTF_CONFIG6 Name: INTF_CONFIG6 Address: 124 (7Ch) Serial IF: R/W Reset value: 0x5F Clock Domain: SCLK_UI BIT NAME 7 6:5 ASYNCTIME0_DIS - 4 I3C_EN 3 I3C_IBI_BYTE_EN 2 I3C_IBI_EN 1 I3C_DDR_EN 0 I3C_SDR_EN Document Number: DS-000401 Revision: 1.2 FUNCTION 0: I3CSMAsynchronous Mode 0 timing control is enabled 1: I3CSM Asynchronous Mode 0 timing control is disabled Reserved 0: I3CSM slave not enabled 1: I3CSM slave enabled 0: I3CSM IBI payload function not enabled 1: I3CSM IBI payload function enabled 0: I3CSM IBI function not enabled 1: I3CSM IBI function enabled 0: I3CSM DDR mode not enabled 1: I3CSM DDR mode enabled 0: I3CSM SDR mode not enabled 1: I3CSM SDR mode enabled Page 98 of 119 IIM-42652 16 USER BANK 2 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within USR Bank 2. ACCEL_CONFIG_STATIC2 Name: ACCEL_CONFIG_STATIC2 Address: 03 (03h) Serial IF: R/W Reset value: 0x30 Clock Domain: SCLK_UI BIT NAME 7 6:1 0 ACCEL_AAF_DELT ACCEL_AAF_DIS FUNCTION Reserved Controls bandwidth of the accelerometer anti-alias filter See section 5.2 for details 0: Enable accelerometer anti-aliasing filter 1: Disable accelerometer anti-aliasing filter ACCEL_CONFIG_STATIC3 Name: ACCEL_CONFIG_STATIC3 Address: 04 (04h) Serial IF: R/W Reset value: 0x40 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_AAF_DELTSQR[7:0] FUNCTION Controls bandwidth of the accelerometer anti-alias filter See section 5.2 for details ACCEL_CONFIG_STATIC4 Name: ACCEL_CONFIG_STATIC4 Address: 05 (05h) Serial IF: R/W Reset value: 0x62 Clock Domain: SCLK_UI BIT NAME 7:4 ACCEL_AAF_BITSHIFT 3:0 ACCEL_AAF_DELTSQR[11:8] FUNCTION Controls bandwidth of the accelerometer anti-alias filter See section 5.2 for details Controls bandwidth of the accelerometer anti-alias filter See section 5.2 for details XA_ST_DATA Name: XA_ST_DATA Address: 59 (3Bh) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:0 XA_ST_DATA X-accel self-test data Document Number: DS-000401 Revision: 1.2 Page 99 of 119 IIM-42652 YA_ST_DATA Name: YA_ST_DATA Address: 60 (3Ch) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:0 YA_ST_DATA Y-accel self-test data ZA_ST_DATA Name: ZA_ST_DATA Address: 61 (3Dh) Serial IF: R/W Reset value: 0xXX (The value in this register indicates the self-test output generated during manufacturing tests) Clock Domain: SCLK_UI BIT NAME FUNCTION 7:0 ZA_ST_DATA Z-accel self-test data Document Number: DS-000401 Revision: 1.2 Page 100 of 119 IIM-42652 17 USER BANK 3 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within USR Bank 3. PU_PD_CONFIG1 Name: PU_PD_CONFIG1 Address: 06 (06h) Serial IF: R/W Reset value: 0x80 Clock Domain: SCLK_UI BIT NAME 7 PIN11_PU_EN 6 PIN7_PU_EN 5 - 4 PIN9_PD_EN 3 PIN10_PU_EN 2 PIN3_PU_EN 1 PIN2_PU_EN 0 PIN4_PD_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Pull-up control for pin 11 0: Pull-up is disabled 1: Pull-up is enabled Pull-up control for pin 7 if triple interface mode is used. Must be set to 0 if single/dual interface mode is used. 0: Pull-up is disabled 1: Pull-up is enabled Reserved Pull-down control for pin 9 in single/dual interface mode. Must be set to 0 if triple interface mode is used. 0: Pull-down is disabled 1: Pull-down is enabled Pull-up control for pin 10 0: Pull-up is disabled 1: Pull-up is enabled Pull-up control for pin 3 0: Pull-up is disabled 1: Pull-up is enabled Pull-up control for pin 2 0: Pull-up is disabled 1: Pull-up is enabled Pull-down control for pin 4 0: Pull-down is disabled 1: Pull-down is enabled Page 101 of 119 IIM-42652 PU_PD_CONFIG2 Name: PU_PD_CONFIG2 Address: 14 (0Eh) Serial IF: R/W Reset value: 0x20 Clock Domain: SCLK_UI BIT NAME 7 PIN1_PU_EN 6 PIN1_PD_EN 5 PIN12_PU_EN 4 PIN12_PD_EN 3 PIN14_PU_EN 2 PIN14_PD_EN 1 PIN13_PU_EN 0 PIN13_PD_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Pull-up control for pin 1. See bit 6 description for pull-down control for pin 1. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-up is disabled 1: Pull-up is enabled Pull-down control for pin 1. See bit 7 description for pull-up control for pin 1. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-down is disabled 1: Pull-down is enabled Pull-up control for pin 12. See bit 4 description for pull-down control for pin 12. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-up is disabled 1: Pull-up is enabled Pull-down control for pin 12. See bit 5 description for pull-up control for pin 12. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-down is disabled 1: Pull-down is enabled Pull-up control for pin 14. See bit 2 description for pull-down control for pin 14. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-up is disabled 1: Pull-up is enabled Pull-down control for pin 14. See bit 3 description for pull-up control for pin 14. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-down is disabled 1: Pull-down is enabled Pull-up control for pin 13. See bit 0 description for pull-down control for pin 13. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-up is disabled 1: Pull-up is enabled Pull-down control for pin 13. See bit 1 description for pull-up control for pin 13. Note that both pull-up and pull-down must not be simultaneously enabled for the same pin. 0: Pull-down is disabled 1: Pull-down is enabled Page 102 of 119 IIM-42652 18 USER BANK 4 REGISTER MAP – DESCRIPTIONS This section describes the function and contents of each register within USR Bank 4. FDR_CONFIG Name: FDR_CONFIG Address: 09 (09h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7 - 6:0 FDR_SEL FUNCTION Reserved FIFO packet rate decimation factor. Sets the number of discarded FIFO packets. Valid range is 0 to 127. User must disable sensors when initializing FDR_SEL value or making changes to it. 0000000: Decimation is disabled, all packets are sent to FIFO 0000001: 1 packet out of 2 is sent to FIFO 0000010: 1 packet out of 3 is sent to FIFO 0000011: 1 packet out of 4 is sent to FIFO … 1111111: 1 packet out of 128 is sent to FIFO APEX_CONFIG1 Name: APEX_CONFIG1 Address: 64 (40h) Serial IF: R/W Reset value: 0xA2 Clock Domain: SCLK_UI BIT NAME 7:4 LOW_ENERGY_AMP_TH_SEL 3:0 DMP_POWER_SAVE_TIME_SEL Document Number: DS-000401 Revision: 1.2 FUNCTION Pedometer Low Energy mode amplitude threshold selection Use default value 1010b When the DMP is in power save mode, it is awakened by the WOM and will wait for a certain duration before going back to sleep. This bitfield configures this duration. 0000: 0 seconds 0001: 4 seconds 0010: 8 seconds 0011: 12 seconds 0100: 16 seconds 0101: 20 seconds 0110: 24 seconds 0111: 28 seconds 1000: 32 seconds 1001: 36 seconds 1010: 40 seconds 1011: 44 seconds 1100: 48 seconds 1101: 52 seconds 1110: 56 seconds 1111: 60 seconds Page 103 of 119 IIM-42652 APEX_CONFIG2 Name: APEX_CONFIG2 Address: 65 (41h) Serial IF: R/W Reset value: 0x85 Clock Domain: SCLK_UI BIT NAME 7:4 PED_AMP_TH_SEL 3:0 PED_STEP_CNT_TH_SEL Document Number: DS-000401 Revision: 1.2 FUNCTION Pedometer amplitude threshold selection Use default value 1000b Pedometer step count detection window Use default value 0101b 0000: 0 steps 0001: 1 step 0010: 2 steps 0011: 3 steps 0100: 4 steps 0101: 5 steps (default) 0110: 6 steps 0111: 7 steps 1000: 8 steps 1001: 9 steps 1010: 10 steps 1011: 11 steps 1100: 12 steps 1101: 13 steps 1110: 14 steps 1111: 15 steps Page 104 of 119 IIM-42652 APEX_CONFIG3 Name: APEX_CONFIG3 Address: 66 (42h) Serial IF: R/W Reset value: 0x51 Clock Domain: SCLK_UI BIT NAME 7:5 PED_STEP_DET_TH_SEL 4:2 PED_SB_TIMER_TH_SEL 1:0 PED_HI_EN_TH_SEL Document Number: DS-000401 Revision: 1.2 FUNCTION Pedometer step detection threshold selection Use default value 010b 000: 0 steps 001: 1 step 010: 2 steps (default) 011: 3 steps 100: 4 steps 101: 5 steps 110: 6 steps 111: 7 steps Pedometer step buffer timer threshold selection Use default value 100b 000: 0 samples 001: 1 sample 010: 2 samples 011: 3 samples 100: 4 samples (default) 101: 5 samples 110: 6 samples 111: 7 samples Pedometer high energy threshold selection Use default value 01b Page 105 of 119 IIM-42652 APEX_CONFIG4 Name: APEX_CONFIG4 Address: 67 (43h) Serial IF: R/W Reset value: 0xA4 Clock Domain: SCLK_UI BIT NAME 7:6 TILT_WAIT_TIME_SEL 5:3 LOWG_PEAK_TH_HYST_SEL 2:0 HIGHG_PEAK_TH_HYST_SEL Document Number: DS-000401 Revision: 1.2 FUNCTION Configures duration of delay after tilt is detected before interrupt is triggered 00: 0s 01: 2s 10: 4s (default) 11: 6s This threshold is added to the LOWG peak threshold after the initial threshold is met. The threshold values corresponding to parameter values are shown below: 000: 31mgee 001: 63mgee 010: 94mgee 011: 125mgee 100: 156mgee (default) 101: 188mgee 110: 219mgee 111: 250mgee This threshold is added to the HIGHG peak threshold after the initial threshold is met. The threshold values corresponding to parameter values are shown below: 000: 31mgee 001: 63mgee 010: 94mgee 011: 125mgee 100: 156mgee (default) 101: 188mgee 110: 219mgee 111: 250mgee Page 106 of 119 IIM-42652 APEX_CONFIG5 Name: APEX_CONFIG5 Address: 68 (44h) Serial IF: R/W Reset value: 0x8C Clock Domain: SCLK_UI BIT NAME 7:3 LOWG_PEAK_TH_SEL 2:0 LOWG_TIME_TH_SEL FUNCTION This parameter defines the threshold for accelerometer values below which the algorithm considers it has entered low-g state. The threshold values corresponding to parameter values are shown below: 00000: 31mgee 00001: 63mgee 00010: 94mgee 00011: 125mgee 00100: 156mgee 00101: 188mgee 00110: 219mgee 00111: 250mgee 01000: 281mgee 01001: 313mgee 01010: 344mgee 01011: 375mgee 01100: 406mgee 01101: 438mgee 01110: 469mgee 01111: 500mgee 10000: 531mgee 10001: 563mgee (default) 10010: 594mgee 10011: 625mgee 10100: 656mgee 10101: 688mgee 10110: 719mgee 10111: 750mgee 11000: 781mgee 11001: 813mgee 11010: 844mgee 11011: 875mgee 11100: 906mgee 11101: 938mgee 11110: 969mgee 11111: 1000mgee This parameter defines the number of samples for which the device should stay in low-g before triggering interrupt. Number of samples = LOWG_TIME_TH_SEL + 1 Default value is 4 (i.e. 5 samples) Document Number: DS-000401 Revision: 1.2 Page 107 of 119 IIM-42652 APEX_CONFIG6 Name: APEX_CONFIG6 Address: 69 (45h) Serial IF: R/W Reset value: 0x5C Clock Domain: SCLK_UI BIT NAME 7:3 HIGHG_PEAK_TH_SEL 2:0 HIGHG_TIME_TH_SEL Document Number: DS-000401 Revision: 1.2 FUNCTION This parameter defines the threshold for accelerometer values above which the algorithm considers it has entered high-g state. The threshold values corresponding to parameter values are shown below: 00000: 250mgee 00001: 500mgee 00010: 750mgee 00011: 1000mgee 00100: 1250mgee 00101: 1500mgee 00110: 1750mgee 00111: 2000mgee 01000: 2250mgee 01001: 2500mgee 01010: 2750mgee 01011: 3000mgee 01100: 3250mgee 01101: 3500mgee 01110: 3750mgee 01111: 4000mgee 10000: 4250mgee 10001: 4500mgee 10010: 4750mgee 10011: 5000mgee 10100: 5250mgee 10101: 5500mgee 10110: 5750mgee 10111: 6000mgee 11000: 6250mgee 11001: 6500mgee 11010: 6750mgee 11011: 7000mgee 11100: 7250mgee 11101: 7500mgee 11110: 7750mgee 11111: 8000mgee This parameter defines the number of samples for which the device should stay in high-g before triggering interrupt. Number of samples = HIGHG_TIME_TH_SEL + 1 Default value is 4 (i.e. 5 samples) Page 108 of 119 IIM-42652 APEX_CONFIG7 Name: APEX_CONFIG7 Address: 70 (46h) Serial IF: R/W Reset value: 0x45 Clock Domain: SCLK_UI BIT NAME 7:2 TAP_MIN_JERK_THR 1:0 TAP_MAX_PEAK_TOL FUNCTION Tap Detection minimum jerk threshold Use default value 010001b Tap Detection maximum peak tolerance Use default value 01b APEX_CONFIG8 Name: APEX_CONFIG8 Address: 71 (47h) Serial IF: R/W Reset value: 0x5B Clock Domain: SCLK_UI BIT NAME 7 6:5 TAP_TMAX 4:3 TAP_TAVG 2:0 TAP_TMIN FUNCTION Reserved Tap measurement window (number of samples) Use default value 10b Tap energy measurement window (number of samples) Use default value 11b Single tap window (number of samples) Use default value 011b APEX_CONFIG9 Name: APEX_CONFIG9 Address: 72 (48h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:1 0 SENSITIVITY_MODE Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Low power mode at accelerometer ODR 25 Hz; High performance mode at accelerometer ODR ≥ 50 Hz 1: Low power and slow walk mode at accelerometer ODR 25 Hz; Slow walk mode at accelerometer ODR ≥ 50 Hz Page 109 of 119 IIM-42652 APEX_CONFIG10 Name: APEX_CONFIG10 Address: 73 (49h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:5 FF_MIN_DURATION_CM 4:2 FF_MAX_DURATION_CM 1:0 FF_DEBOUNCE_DURATION FUNCTION This parameter defines the minimum freefall length that the algorithm should report. Freefalls smaller than this value are ignored. Freefall lengths corresponding to parameter values are shown below: 000: 13cm (default) 001: 19cm 010: 28cm 011: 38cm 100: 50cm 101: 64cm 110: 78cm 111: 95cm This parameter defines the maximum freefall length that the algorithm should report. Freefalls longer than this value are ignored. Freefall lengths corresponding to parameter values are shown below: 000: 113cm (default) 001: 154cm 010: 201cm 011: 255cm 100: 314cm 101: 380cm 110: 452cm 111: 531cm This parameter defines the time during which low-g and high-g events are not taken into account after a high-g event. It helps to avoid detecting bounces as free fall. Debounce durations corresponding to parameter values are shown below: 00: 0s 01: 1s 10: 2s 11: 3s ACCEL_WOM_X_THR Name: ACCEL_WOM_X_THR Address: 74 (4Ah) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 WOM_X_TH Document Number: DS-000401 Revision: 1.2 FUNCTION Threshold value for the Wake on Motion Interrupt for X-axis accelerometer WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9mg Page 110 of 119 IIM-42652 ACCEL_WOM_Y_THR Name: ACCEL_WOM_Y_THR Address: 75 (4Bh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 WOM_Y_TH FUNCTION Threshold value for the Wake on Motion Interrupt for Y-axis accelerometer WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9mg ACCEL_WOM_Z_THR Name: ACCEL_WOM_Z_THR Address: 76 (4Ch) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 WOM_Z_TH FUNCTION Threshold value for the Wake on Motion Interrupt for Z-axis accelerometer WoM thresholds are expressed in fixed “mg” independent of the selected Range [0g : 1g]; Resolution 1g/256=~3.9mg INT_SOURCE6 Name: INT_SOURCE6 Address: 77 (4Dh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 STEP_DET_INT1_EN 4 STEP_CNT_OFL_INT1_EN 3 TILT_DET_INT1_EN 2 - 1 FREEFALL_DET_INT1_EN 0 TAP_DET_INT1_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Step detect interrupt not routed to INT1 1: Step detect interrupt routed to INT1 0: Step count overflow interrupt not routed to INT1 1: Step count overflow interrupt routed to INT1 0: Tilt detect interrupt not routed to INT1 1: Tile detect interrupt routed to INT1 Reserved 0: Freefall detect interrupt not routed to INT1 1: Freefall detect interrupt routed to INT1 0: Tap detect interrupt not routed to INT1 1: Tap detect interrupt routed to INT1 Page 111 of 119 IIM-42652 INT_SOURCE7 Name: INT_SOURCE7 Address: 78 (4Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 STEP_DET_INT2_EN 4 STEP_CNT_OFL_INT2_EN 3 TILT_DET_INT2_EN 2 - 1 FREEFALL_DET_INT2_EN 0 TAP_DET_INT2_EN FUNCTION Reserved 0: Step detect interrupt not routed to INT2 1: Step detect interrupt routed to INT2 0: Step count overflow interrupt not routed to INT2 1: Step count overflow interrupt routed to INT2 0: Tilt detect interrupt not routed to INT2 1: Tile detect interrupt routed to INT2 Reserved 0: Freefall detect interrupt not routed to INT2 1: Freefall detect interrupt routed to INT2 0: Tap detect interrupt not routed to INT2 1: Tap detect interrupt routed to INT2 INT_SOURCE8 Name: INT_SOURCE8 Address: 79 (4Fh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 FSYNC_IBI_EN 4 PLL_RDY_IBI_EN 3 UI_DRDY_IBI_EN 2 FIFO_THS_IBI_EN 1 FIFO_FULL_IBI_EN 0 AGC_RDY_IBI_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: FSYNC interrupt not routed to IBI 1: FSYNC interrupt routed to IBI 0: PLL ready interrupt not routed to IBI 1: PLL ready interrupt routed to IBI 0: UI data ready interrupt not routed to IBI 1: UI data ready interrupt routed to IBI 0: FIFO threshold interrupt not routed to IBI 1: FIFO threshold interrupt routed to IBI 0: FIFO full interrupt not routed to IBI 1: FIFO full interrupt routed to IBI 0: AGC ready interrupt not routed to IBI 1: AGC ready interrupt routed to IBI Page 112 of 119 IIM-42652 INT_SOURCE9 Name: INT_SOURCE9 Address: 80 (50h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME I3C_PROTOCOL_ERROR_IBI 7 _EN 6:5 4 SMD_IBI_EN 3 WOM_Z_IBI_EN 2 WOM_Y_IBI_EN 1 WOM_X_IBI_EN 0 - FUNCTION 0: I3CSM protocol error interrupt not routed to IBI 1: I3CSM protocol error interrupt routed to IBI Reserved 0: SMD interrupt not routed to IBI 1: SMD interrupt routed to IBI 0: Z-axis WOM interrupt not routed to IBI 1: Z-axis WOM interrupt routed to IBI 0: Y-axis WOM interrupt not routed to IBI 1: Y-axis WOM interrupt routed to IBI 0: X-axis WOM interrupt not routed to IBI 1: X-axis WOM interrupt routed to IBI Reserved INT_SOURCE10 Name: INT_SOURCE10 Address: 81 (51h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:6 5 STEP_DET_IBI_EN 4 STEP_CNT_OFL_IBI_EN 3 TILT_DET_IBI_EN 2 - 1 FREEFALL_DET_IBI_EN 0 TAP_DET_IBI_EN Document Number: DS-000401 Revision: 1.2 FUNCTION Reserved 0: Step detect interrupt not routed to IBI 1: Step detect interrupt routed to IBI 0: Step count overflow interrupt not routed to IBI 1: Step count overflow interrupt routed to IBI 0: Tilt detect interrupt not routed to IBI 1: Tile detect interrupt routed to IBI Reserved 0: Freefall detect interrupt not routed to IBI 1: Freefall detect interrupt routed to IBI 0: Tap detect interrupt not routed to IBI 1: Tap detect interrupt routed to IBI Page 113 of 119 IIM-42652 OFFSET_USER0 Name: OFFSET_USER0 Address: 119 (77h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_X_OFFUSER[7:0] FUNCTION Lower bits of X-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. OFFSET_USER1 Name: OFFSET_USER1 Address: 120 (78h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 GYRO_Y_OFFUSER[11:8] 3:0 GYRO_X_OFFUSER[11:8] FUNCTION Upper bits of Y-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Upper bits of X-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. OFFSET_USER2 Name: OFFSET_USER2 Address: 121 (79h) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_Y_OFFUSER[7:0] FUNCTION Lower bits of Y-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. OFFSET_USER3 Name: OFFSET_USER3 Address: 122 (7Ah) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 GYRO_Z_OFFUSER[7:0] Document Number: DS-000401 Revision: 1.2 FUNCTION Lower bits of Z-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. Page 114 of 119 IIM-42652 OFFSET_USER4 Name: OFFSET_USER4 Address: 123 (7Bh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 ACCEL_X_OFFUSER[11:8] 3:0 GYRO_Z_OFFUSER[11:8] FUNCTION Upper bits of X-accel offset programmed by user. Max value is ±1g, resolution is 0.5 mg. Upper bits of Z-gyro offset programmed by user. Max value is ±64 dps, resolution is 1/32 dps. OFFSET_USER5 Name: OFFSET_USER5 Address: 124 (7Ch) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_X_OFFUSER[7:0] FUNCTION Lower bits of X-accel offset programmed by user. Max value is ±1g, resolution is 0.5mg. OFFSET_USER6 Name: OFFSET_USER6 Address: 125 (7Dh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_Y_OFFUSER[7:0] FUNCTION Lower bits of Y-accel offset programmed by user. Max value is ±1g, resolution is 0.5mg. OFFSET_USER7 Name: OFFSET_USER7 Address: 126 (7Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:4 ACCEL_Z_OFFUSER[11:8] 3:0 ACCEL_Y_OFFUSER[11:8] Document Number: DS-000401 Revision: 1.2 FUNCTION Upper bits of Z-accel offset programmed by user. Max value is ±1g, resolution is 0.5mg. Upper bits of Y-accel offset programmed by user. Max value is ±1g, resolution is 0.5mg. Page 115 of 119 IIM-42652 OFFSET_USER8 Name: OFFSET_USER8 Address: 127 (7Fh) Serial IF: R/W Reset value: 0x00 Clock Domain: SCLK_UI BIT NAME 7:0 ACCEL_Z_OFFUSER[7:0] Document Number: DS-000401 Revision: 1.2 FUNCTION Lower bits of Z-accel offset programmed by user. Max value is ±1g, resolution is 0.5 mg. Page 116 of 119 IIM-42652 19 REFERENCE Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information: • Manufacturing Recommendations o Assembly Guidelines and Recommendations o PCB Design Guidelines and Recommendations o MEMS Handling Instructions o ESD Considerations o Reflow Specification o Storage Specifications o Package Marking Specification o Tape & Reel Specification o Reel & Pizza Box Label o Packaging o Representative Shipping Carton Label • Compliance o Environmental Compliance o DRC Compliance o Compliance Declaration Disclaimer Document Number: DS-000401 Revision: 1.2 Page 117 of 119 IIM-42652 20 REVISION HISTORY REVISION DATE REVISION DESCRIPTION 01/07/2021 1.0 Initial release Updated anti-aliasing filter reference in Chapter 15.3, 15.4 and 15.5 from Chapter 5.2 to Chapter 5.3. Chapter 15.1 reset Value 0xB0 changed to 0x80 07/27/2021 1.1 Remove the FIFO_WM_EN reference on sections 14.46 & 14.47 Updated section 12.7 “FIFO Timestamp Interval Scaling” Added section 12.9 on register value modification Updated bit 3 description on Section 14.4 10/01/2021 1.2 Document Number: DS-000401 Revision: 1.2 Updated Sections 14.43, 17.1, 17.2 Updated SmartIndustrial formatting Page 118 of 119 IIM-42652 This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights. Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment. ©2021 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other cocmpany and product names may be trademarks of the respective companies with which they are associated. ©2021 InvenSense. All rights reserved. Document Number: DS-000401 Revision: 1.2 Page 119 of 119