TC71EPA

1 TC70/71 MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP FEATURES s Maximum Functional Integration: Precision Power Supply Monitor, Watchdog Timer, External RESET Override, Threshold Detector and Battery Backup Controller in an 8-Pin Package Generates Power-on RESET and Guards Against Unstable Processor Operation Resulting from Power "Brown-out" Automatically Halts and Restarts an Out-ofControl Microprocessor Output Can be Wire-ORed, or Hooked to Manual RESET Pushbutton Switch Watchdog Disable Pin for Easier Prototyping (TC70) Voltage Monitor for Power Fail or Low Battery Warning (TC71) Available in 8-Pin Plastic DIP or 8-Pin SOIC Packages Cost Effective 2 3 4 5 6 7 GENERAL DESCRIPTION The TC70/71 is a fully-integrated power supply monitor, watchdog and battery backup circuit in a space-saving 8-pin package. When power is initially applied, the TC70/71 holds the processor in its reset state for a minimum of 500msec after VCC is in tolerance to ensure stable system start-up. After start-up, processor sanity is monitored by the on-board watchdog circuit. The processor must provide periodic highto-low level transitions to the TC70/71 to verify proper execution. Should the processor fail to supply this signal within the specified timeout period, an out-of-control processor is indicated and the TC70/71 issues a momentary processor reset as a result. The TC70 also features a watchdog disable pin to facilitate system test and debug. The output of the TC70/71 can be wire-ORed to a pushbutton switch (or electronic signal) to reset the processor. When connected to a push-button switch, the TC70/71 provides contact debounce. The integrated battery backup circuit on-board the TC70/ 71 converts CMOS RAM into nonvolatile memory by first write-protecting, then switching the VCC line of the RAM over to an external battery. The TC71 incorporates an additional 1.3V threshold detector for power fail warning, low battery detection or to monitor power supply voltages other than +5V. s s s s s s s TYPICAL APPLICATIONS s s s s All Microprocessor-based Systems Test Equipment Instrumentation Set-Top Boxes FUNCTIONAL BLOCK DIAGRAM ORDERING INFORMATION VCC CEI (TC70) VBATT BATTERY BACK-UP CONTROL VCCO CEO (TC70) PF (TC71) Part No. TC70COA TC70CPA TC70EOA TC70EPA TC71COA TC71CPA TC71EOA TC71EPA Package 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin Plastic DIP Temp. Range 0°C to +70°C 0°C to +70°C – 40°C to +85°C – 40°C to +85°C 0°C to +70°C 0°C to +70°C – 40°C to +85°C – 40°C to +85°C VREF1 WDD (TC70) WATCHDOG TIMER ∆V DETECTOR RS VREF2 DELAY TIMER GND VREF3 TDI (TC71) TDO (TC71) TC70/71 PIN CONFIGURATIONS (DIP and SOIC) VCCO VCC GND CEI 1 2 3 4 8 7 VBATT RS WDD CEO VCCO VCC GND TDI 1 2 3 4 8 7 VBATT RS PF TDO TC70 TC71 6 5 6 5 8 TC70/71-1 11/18/96 TELCOM SEMICONDUCTOR, INC. 5-7 MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP TC70/71 ABSOLUTE MAXIMUM RATINGS* Voltage (Any Pin) with Respect to Ground ................................ GND – 0.3 to VCC + 0.3V Operating Temperature Range ............... – 40°C to +85°C Storage Temperature Range ................ – 65°C to +150°C Lead Temperature (Soldering, 10 sec) ................. +300°C *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: Recommended DC Operations: TA = TMIN to TMAX, unless otherwise specified. Symbol VCC VIH VIH VIL Parameter Supply Voltage Input HIGH Level Input HIGH Level Input LOW Level Test Conditions Note 1 CEI, WDD (Note 1) RS (Note 1) CEI, WDD, RS (Note 1) Min 4.5 2.5 2.2 — Typ 5.0 — — — Max 5.5 — — 0.8 Unit V V V V ELECTRICAL CHARACTERISTICS: DC: TA = TMIN to TMAX, VCC = 4.5V to 5.5V, unless otherwise specified. Symbol ICC1 ICC2 IIH IIL IIH ISTBY ISTBY Parameter Operating Current Operating Current in Battery Backup Mode Input Leakage Input Leakage Input Leakage Battery Standby Current Battery Standby Current Test Conditions Notes 2, 3 VCC = 0; VBATT = 2.8V; (Note 3) CEI CEI RS 5.5V > VCC > VBATT + 0.2V 5.5V > VCC > VBATT + 0.2V TA = 25°C Min — — — — — – 1.0 – 0.1 Typ 5 0.01 4 1 1 — — Max 6.5 0.20 7 — — 0.02 0.02 Unit mA µA µA µA µA µA µA ELECTRICAL CHARACTERISTICS: DC: Power Supply Monitor, EXT. RESET and Watchdog: TA = TMIN to TMAX, VCC = 4.5V to 5.5V, unless otherwise specified. Symbol IOL IOH WDDI VSTH VSTL VCCTRIP Parameter Output Current 0.4V (RS, TDO, CEO, PF Pins) Output Current 2.4V (TDO, CEO, PF Pins) WDD Input Current RS Strobe (HIGH) Level RS Strobe (LOW) Level VCC Trip Point Test Conditions VOL = 0.4V VOH = 2.4V WDD = GND WDD = VCC Figure 3 (Note 1) Figure 3 (Note 1) (Note 1) 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C Min 2 2 – 120 — VDD – 0.5 2.2 4.25 4.20 Typ 5 3 — — — — — Max — — — 25 — VDD – 1.8 4.49 4.49 Unit mA mA µA V V ELECTRICAL CHARACTERISTICS: DC: Battery Backup and Threshold Detector: TA = TMIN to TMAX, VCC = 4.5V to 5.5V, unless otherwise specified. Symbol VOUT1 VOUT2 5-8 Parameter VCCO Output Voltage VOUT in Battery Backup Mode Test Conditions Min Typ Max — — — Unit V V IOUT = 1mA VCC – 0.3 VCC – 0.1 IOUT = 50mA VCC – 0.5 VCC – 0.20 IOUT = 250µA, VCC < VBATT – 0.2, VBATT = 2.8V VBATT – 0.1 VBATT – 0.02 TELCOM SEMICONDUCTOR, INC. MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP 1 TC70/71 ELECTRICAL CHARACTERISTICS: (Cont.) DC: Battery Backup and Threshold Detector: TA = TMIN to TMAX, VCC = 4.5V to 5.5V, unless otherwise specified. Symbol IOUT1 IOUT2 VSW VHYST VOHCEO VTDI ITDI VTDI (HYST) Parameter VCCO Output Current VCCO Output Current in Battery Backup Mode Battery Switchover Threshold (VCC Falling) Battery Switchover Hysteresis CEO Output Voltage in Battery Backup Mode Threshold Detector Trip Voltage Threshold Detector Input Current Threshold Detector Hysteresis Test Conditions VCC = 4.5V, VCCO = 3.5V VCCO = VBATT – 0.3V VBATT = 2.8V Min 50 500 — — VBATT – 0.2 1.2 Typ 100 — VBATT – 0.01 20 — — — 10 Max — — — — — 1.4 +25 — Unit mA µA V mV V V nA mV 2 3 4 5 6 7 VCC < VBATT – 0.2, VBATT = 2.8V IOH = 10µA TA = 25°C –25 — ELECTRICAL CHARACTERISTICS: AC: Power Supply Monitor, EXT. RESET and Watchdog: TA = TMIN to TMAX, VCC = 4.5V to 5.5V, unless otherwise specified. Symbol tPBH tRST tST tTD tRPD Parameter PB Hold Time Reset Active Time RS STROBE Pulsewidth Watchdog Timeout Period VCC Detect to RS LOW Test Conditions Figure 4 (Note 4) Figure 6 Figure 3 Figure 3 Figure 6 Min 20 500 500 500 — Typ — — — 700 — Max — 900 — 900 100 Unit msec msec nsec msec nsec ELECTRICAL CHARACTERISTICS: AC: Battery Backup and Threshold Detector: TA = TMIN to TMAX, VCC = 4.5V to 5.5V, unless otherwise specified. Symbol tPD Parameter CE Propagational Delay Test Conditions Figure 7 Min — Typ — Max 50 Unit nsec ELECTRICAL CHARACTERISTICS: AC: TA = TMIN to TMAX. Symbol tF tR NOTES: 1. 2. 3 4. Parameter VCC Fall Time From 4.25V to 3.0V VCC Rise Time From 3.0V to 4.25V Test Conditions Figure 5 (Note 1) Figure 5 (Note 1) Min 10 0 Typ — — Max — — Unit µsec µsec All voltages referenced to ground. No output load. Measured with VCCO and CEO open. The RS output must be held low for a minimum of 20msec to guarantee a reset. 8 TELCOM SEMICONDUCTOR, INC. 5-9 TC70 TC71 PIN DESCRIPTION Pin No (TC70) 1 2 3 4 – 5 – MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP Pin No (TC71) 1 2 3 – 4 – 5 Symbol VCCO VCC GND CEI TDI CEO TDO Description VCC Output. The higher of VCC or VBATT is internally switched to this output. Connect to VCC if VBATT and VCCO are not used. VCC Input. +5V power supply. GND Input. Ground. Chip enable input. Chip enable to static RAM or other device to be battery backed-up. Connect to ground if VCCO is not used. Threshold detector input. When the voltage on threshold detector input (TDI) is less than 1.3V, threshold detector output (TDO) goes low. Chip enable output. This line goes low only when CEI is low and VCC is above the RESET threshold. Threshold detector output. TDO goes low when TDI is less than 1.3V and VCC is greater than VBATT. (The threshold detector is turned off when VCC is less than VBATT. Watchdog disable input. Grounding this line disables the watchdog timer (no RESET pulses are generated after the watchdog timer times out). This input is provided to facilitate system debug. This input is internally pulled-up and can be left open, or tied to VCC for normal watchdog operation. Power fail output. This line goes low when VCC is below 4.5V nominal. It is used to write-protect the external device to be battery backed. RESET/STORE (Bidirectional). An open drain with pull-up (in output mode) that goes active if: 1. VCC falls below 4.5V nominal 2. If pulled low by an external electronic signal or switch closure 3. If the watchdog is not strobed within the minimum watchdog timeout period 4. During power-up and power down In the input mode, RS is a negative edge triggered input that resets the watchdog timer when pulled to ground through a 10kΩ, 5% tolerance resistor. Backup battery input. Connect to ground if battery backup is not used. 6 – WDD – 7 6 7 PF RS 8 8 VBATT DETAILED DESCRIPTION Precision Power Supply Monitor The RS pin is immediately driven low any time VCC is below 4.5V nominal. The processor is held in its reset state during power-up and power-down. RS remains low for a minimum of 500msec after VCC is within tolerance to allow the power supply and processor to stabilize. Watchdog Timer The processor drives the RS pin with an input/output (I/O) line in series with a voltage divider to VDD. Pulling the bottom of this divider low results in an internal voltage change (strobe) sufficient to reset the watchdog timer, but above the VIL input threshold of the processor RESET input. The processor must continuously apply strobes in this manner within a set period to verify proper software execution. A momentary reset (500msec minimum) is generated if a hardware or software failure keeps RS from being 5-10 strobed within the watchdog timeout period. This action typically initiates the processor's power-up routine. If the interruption persists, new reset pulses are generated each timeout period until RS is strobed. The timeout period is typically 700msec. It is often difficult to debug a system while the watchdog is continuously generating reset pulses. For example, the watchdog must be disabled when the system is operated with an in-circuit emulator (ICE). The watchdog disable input (TC70) is provided for system debugging, (or if the watchdog timer on-board the processor is to be used). Grounding WDD disables the watchdog (all other functions remain intact). For normal watchdog operation, WDD can be tied to VDD. The software routine that drives the RS strobe must be in a section of the program that executes frequently enough so the time between toggles is less than one watchdog timeout period. The strobe signal can be derived from microprocessor address, data and/or control signals. Typical circuit examples are shown in Figure 1. TELCOM SEMICONDUCTOR, INC. MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP 1 TC70 TC71 Resistor Value Selection The values of R1 and R2 must be chosen to ensure a valid low strobe level (VSTL) on RS when the processor I/O line is low. The use of 10kΩ, ±5% tolerance resistors are recommended. These values result in a nominal strobe level of 2.83V on RS (min/max of 2.43V/3.24V, assuming VDD = 5.0V ±10%). Other resistor values can be used, so long as the additive tolerances of the power supply and resistor values result in a strobe that falls within VSTH and VSTL under all additive tolerance conditions. data corruption during power up and power down. The battery switchover circuit compares VCC to the VBATT input and connects VCCO to whichever is higher. Switchover (VSW) occurs when VCC is 10mV below VBATT as VCC falls, and when VCC is 10mV more than VBATT as VCC rises. The battery switchover comparator has 20mV of hysteresis to prevent switch chattering if VCC falls very slowly. 2 3 4 5 6 7 Integrated Battery Backup (TC71) The TC71 differs from the TC70 in that it has a Power Fail (PF) output instead of a gated chip enable (CEI, CEO). PF must be externally gated with the decode for the CMOS RAM or other device to be battery-backed. (Many CMOS RAMs have both CE and CE enables. In this case, the PF output can be connected directly to the CE input of the RAM). PF is high as long as VCC is greater than 4.5V nominal. When VCC falls below 4.5V nominal, PF is driven low. Battery switchover for the TC71 is otherwise identical to that of the TC70. External Override Reset Control A built-in debounce circuit allows a pushbutton switch (or other electronic reset signal) to be wire-ORed to RS as an external reset override (Figure 4). The external reset signal is required to be an active low signal of at least 20msec in duration. Internally, this input is timed to provide a minimum reset pulse width output of 500msec. Threshold Detector The TC71 issues a low-true output on the TDO pin any time the TDI pin is less than 1.3V and VCC is greater than VBATT. The voltage to be monitored is connected to the TDI input through a simple resistor divider. The threshold detector can be used to generate an early power fail warning if the unregulated DC input to the +5V regulator is available for monitoring. Supply Monitor Noise Sensitivity The TC70/71 is optimized for fast response to negativegoing changes in VDD. Systems with an inordinate amount of electrical noise on VDD (such as systems using relays), may require a 0.1µF bypass capacitor to reduce detection sensitivity. This capacitor should be installed as close to the TC70/71 as possible to keep the capacitor lead length short. Integrated Battery Backup (TC70) The CEO line (TC70) drives the CE input of a CMOS RAM or other device to be battery-backed. CEO follows CEI as long as VCC is greater than 4.5V nominal. If VCC falls below 4.5V nominal, CEO is driven to the potential of VCCO thus write protecting the RAM and preventing accidental TYPICAL APPLICATIONS Figure 1 shows a full feature implementation of the TC70; Figure 2 shows the TC71. Resistors R1 and R2 of Figure 2 set the trip point voltage for the early power fail warning circuit using the TC71 threshold detector. WDD +5V VCC VCCO CEO VCC CE CMOS RAM TC70 VBATT +3V LI BATTERY GND CEI +5V R1 10K ADDRESS DECODER R2 13K ADDRESS RS I/O RESET PROCESSOR RESET Figure 1. TC70 Typical Application 8 5-11 TELCOM SEMICONDUCTOR, INC. TC70 TC71 MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP RECTIFIER FILTER CAP WDD TC55RP REGULATOR R3 VCC TDI TC71 VCC AC IN VCCO PF VCC CE CE ADDRESS DECODER ADDRESS NMI R4 13K I/O RESET CMOS RAM TDO R3 10K VCC R4 VBATT 3V LI GND RS RESET Figure 2. TC71 Typical Application PROCESSOR tST RS VSTH (MIN) VSTL (MAX) VSTL (MIN) tTD PB CLOSED PB OPEN RS tPBH VIH VIL Note: tTD is the maximum elapsed time between strobes which will keep the watchdog timer from forcing RS LOW. (A STROBE is defined as a high-to-low transition from VSTH to VSTL). tRST Figure 3. Watchdog Strobe Figure 4. RS Override Reset 5-12 TELCOM SEMICONDUCTOR, INC. MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP 1 TC70 TC71 tR tF VCC 4.25V VCC 4.25V 2 3 VOH 3.0V RS tRPD tRST VOL 4 Figure 5. Power Up/Down Slew Rate Figure 6. Power Up/Down Reset Timing VIH CEI CEI VIL VBATT-0.2V 5 6 4.25V 3.0V tF VBATT- 0.2V VIH CEO tPD tPD CEO 4.25V 3.0V VCC tR VCC Figure 7. Battery Backup (Power-Up) Figure 8. Battery Backup (Power-Down) 7 8 TELCOM SEMICONDUCTOR, INC. 5-13