TS80C51U2

TS80C51U2 TS83C51U2 TS87C51U2 Double UART 8-bit CMOS Microcontroller, 0-60 MHz 1. Description TEMIC TS80C51U2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C51U2 retains all features of the TEMIC 80C51 with extended ROM/EPROM capacity (16 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/ counters. In addition, the TS80C51U2 has a second UART, enhanced functions on both UART, enhanced timer 2, a hardware watchdog timer, a dual data pointer, a baud rate generator and a X2 speed improvement mechanism. The fully static design of the TS80C51U2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51U2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 2. Features q 80C52 Compatible • 8051 pin and instruction compatible • Four 8-bit I/O ports • Three 16-bit timer/counters • 256 bytes scratchpad RAM q q Asynchronous port reset Interrupt Structure with • 7 Interrupt sources • 4 level priority interrupt system q Full duplex Enhanced UARTs • Framing error detection • Automatic address recognition q High-Speed Architecture • 40 MHz @ 5V, 30MHz @ 3V • X2 Speed Improvement capability (6 clocks/ machine cycle) 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V) q q Low EMI (inhibit ALE) Power Control modes • Idle mode • Power-down mode • Power-off Flag q q q q q second UART Baud Rate Generator Dual Data Pointer On-chip ROM/EPROM (16K-bytes) Programmable Clock Out and Up/Down Timer/ Counter 2 Hardware Watchdog Timer (One-time enabled with Reset-Out) q q q Once mode (On-chip Emulation) Power supply: 4.5-5.5V, 2.7-5.5V Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44 (window), CDIL40 (window) q q 3. The second UART In this document, UART_0 will make reference to the first UART (present in all TEMIC Semiconductors C51 derivatives) and UART_1 will make reference to the second UART, only present in the TS80C51U2 part. The second UART (UART_1) can be seen as an alternate function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or P1.7 for TXD1) or can be connected to (pin6 or pin12) Rev. C - Aug. 24, 1999 1 TS80C51U2 TS83C51U2 TS87C51U2 and (pin28 or pin34) of 44-pin package (see Pin configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the clock source. This common internal baud rate generator can be used independently by each UART or both as clock source allowing to program various speeds. The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer 2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive buffered, meaning they can start reception of a second byte before a previously received byte has been read from the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate receive register. The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability. The UART_1 also comes with Frame error detection, similar to the UART_0. 2 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 1. Memory size PDIL40 PLCC44 VQFP44 1.4 TS80C51U2 TS83C51U2 TS87C51U2 ROM (bytes) 0 16k 0 EPROM (bytes) 0 0 16k 4. Block Diagram T2EX RxD1 (3) RxD TxD TxD1 (3) Vcc Vss T2 (1) (2) (2) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/VPP RD WR (2) (2) Timer 0 Timer 1 INT Ctrl UART_0 RAM 256x8 (1) ROM /EPROM 16Kx8 Timer2 UART_1 C51 CORE IB-bus Parallel I/O Ports Port 0 Port 1 Port 2 Port 3 WatchDog (2) (2) RESET T0 T1 (2) (2) P1 P2 INT0 INT1 P0 P3 (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): See pin description Rev. C - Aug. 24, 1999 3 TS80C51U2 TS83C51U2 TS87C51U2 5. SFR Mapping The Special Function Registers (SFRs) of the TS80C51U2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers for UART_0: SADDR_0, SADEN_0, SBUF_0, SCON_0 • Serial I/O port registers for UART_1: SADDR_1, SADEN_1, SBUF_1, SCON_1 • Baud Rate Generator registers: BRL, BDRCON, BDRCON_1 • Power and clock control registers: PCON • HDW Watchdog Timer Reset: WDTRST, WDTPRG • Interrupt system registers: IE, IP, IPH • Others: AUXR, CKCON Table 2. All SFRs with their address and their reset value Bit addressable 0/8 1/9 2/A 3/B Non Bit addressable 4/C 5/D 6/E 7/F F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h PSW 0000 0000 T2CON 0000 0000 SCON_1 0000 0000 IP X000 0000 P3 1111 1111 IE 0X00 0000 P2 1111 1111 SCON_0 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR 00XX XXX0 CKCON XXXX XXX0 PCON 00X1 0000 7/F SBUF_0 XXXX XXXX SADDR_0 0000 0000 SADDR_1 0000 0000 AUXR1 XXXX XXX0 BRL 0000 0000 BDRCON 0XXX 0000 BDRCON_1 0X00 00XX WDTRST XXXX XXXX WDTPRG XXXX X000 T2MOD XXXX XX00 SBUF_1 XXXX XXXX SADEN_0 0000 0000 SADEN_1 0000 0000 IPH X000 0000 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 ACC 0000 0000 B 0000 0000 FFh F7h EFh E7h DFh D7h CFh C7h BFh B7h AFh A7h 9Fh 97h 8Fh 87h reserved 4 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 6. Pin Configuration P1.2/RxD_1 P1.3/TxD_1 P1.1/T2EX P1.1 / T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P0.0 / A0 P0.1 / A1 P0.2 / A2 P0.3 / A3 P0.4 / A4 P0.5 / A5 P0.6 / A6 P0.7 / A7 EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 P1.5 P1.6/RxD_1 P1.7/TxD_1 RST P3.0/RxD_0 RxD_1 P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 P1.4 P0.2/AD2 P0.3/AD3 39 38 37 36 35 34 33 32 31 30 29 P0.0/AD0 P0.1/AD1 P1.0 / T2 1 40 VCC VSS1/NIC* P1.0/T2 2 6 5 4 3 1 44 43 42 41 40 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP TxD_1 ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 PDIL/ CDIL40 PLCC/CQPJ 44 18 19 20 21 22 23 24 25 26 27 28 P3.6/WR NIC* P2.0/A8 XTAL2 XTAL1 P2.2/A10 P2.3/A11 P2.4/A12 P3.7/RD P2.1/A9 VSS P1.3/TxD_1 P1.2/RxD_1 VSS1/NIC* P1.1/T2EX P0.0/AD0 P0.1/AD1 P0.2/AD2 44 43 42 41 40 39 38 37 36 35 34 P1.5 1 2 3 4 5 6 7 8 9 10 11 P0.3/AD3 P1.0/T2 VCC P1.4 P1.6/RxD_1 P1.7/TxD_1 RST P3.0/RxD_0 RxD_1 P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP VQFP44 1.4 TxD_1 ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 12 13 14 15 16 17 18 19 20 21 22 XTAL1 NIC* P2.0/A8 XTAL2 P2.3/A11 P2.4/A12 P2.1/A9 VSS P2.2/A10 P3.6/WR P3.7/RD *NIC: No Internal Connection Refer to paragraph 6.6 for accurate RxD_1 and TxD_1 pin location, depending on AUXR register configuration. Rev. C - Aug. 24, 1999 5 TS80C51U2 TS83C51U2 TS87C51U2 Table 3. Pin Description for 40/44 pin packages MNEMONIC VSS Vss1 VCC P0.0-P0.7 PIN NUMBER DIL 20 LCC 22 1 44 43-36 VQFP 1.4 16 39 38 37-30 TYPE I I I I/O NAME AND FUNCTION Ground: 0V reference Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and powerdown operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for TSC8x54/58 Port 1 include: T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control Depending on values of (M1UA_1, M0UA_1) bits located into AUXR register, the UART_1 pins are alternate functins of P1 with two possible locations. First location: P1.2: RxD_1, serial input port for UART_1 P1.3: TxD_1, serial output port for UART_1 Second location: P1.6: RxD_1, serial input port for UART_1 P1.7: TxD_1, serial output port for UART_1 Refer to paragraph 6.6 Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. RxD_0 (P3.0): Serial input port for UART_0 TxD_0 (P3.1): Serial output port for UART_0 INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe 40 39-32 P1.0-P1.7 1-8 2-9 40-44 1-3 I/O 1 2 2 3 40 41 I/O I P2.0-P2.7 21-28 24-31 18-25 I/O P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O 6 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 3. Pin Description for 40/44 pin packages MNEMONIC Reset PIN NUMBER DIL 9 LCC 10 VQFP 1.4 4 TYPE I NAME AND FUNCTION Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Serial Input for UART_1. For 44-pin package only. Serial Ouput for UART_1. This pin is pulled up by a 100K resistor when not selected. For 44-pin package only. ALE/PROG 30 33 27 O (I) PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 XTAL2 RxD_1 TxD_1 19 18 - 21 20 12 34 15 14 6 28 I O I O Rev. C - Aug. 24, 1999 7 TS80C51U2 TS83C51U2 TS87C51U2 7. TS80C51U2 Enhanced Features In comparison to the original 80C52, the TS80C51U2 implements some new features, which are: • • • • • • • • • • The X2 option. The second full duplex enhanced UART. The Baud Rate generator. The Dual Data Pointer. The Watchdog. The 4 level interrupt priority system. The power-off flag. The ONCE mode. The ALE disabling. Some enhanced features are also located in the UARTs and the timer 2. 7.1 X2 Feature The TS80C51U2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: q q q q Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 7.1.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. XTAL1 FXTAL 2 XTAL1:2 0 1 FOSC state machine: 6 clock cycles. CPU control X2 CKCON reg Figure 1. Clock Generation Diagram 8 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode Figure 2. Mode Switching Waveforms The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UARTs, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. Rev. C - Aug. 24, 1999 9 TS80C51U2 TS83C51U2 TS87C51U2 Table 4. CKCON Register CKCON - Clock Control Register (8Fh) 7 Bit Number 7 6 Bit Mnemonic - 5 - 4 - 3 Description 2 - 1 - 0 X2 Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL). 6 - 5 - 4 - 3 - 2 - 1 - 0 X2 Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.temic-semi.com) 10 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3). External Data Memory 7 0 DPS DPTR1 DPTR0 AUXR1(A2H) DPH(83H) DPL(82H) Figure 3. Use of Dual Pointer Rev. C - Aug. 24, 1999 11 TS80C51U2 TS83C51U2 TS87C51U2 Table 5. AUXR1: Auxiliary Register 1 7 Bit Number 7 6 Bit Mnemonic - 5 - 4 - 3 Description 2 - 1 - 0 DPS Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Clear to select DPTR0. Set to select DPTR1. 6 - 5 - 4 - 3 - 2 - 1 - 0 DPS User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. 12 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE 0003 05A2 INC AUXR1 0005 90A000 MOV DPTR,#DEST 0008 LOOP: 0008 05A2 INC AUXR1 000A E0 MOVX A,@DPTR 000B A3 INC DPTR 000C 05A2 INC AUXR1 000E F0 MOVX @DPTR,A 000F A3 INC DPTR 0010 70F6 JNZ LOOP 0012 05A2 INC AUXR1 ; address of SOURCE ; switch data pointers ; address of DEST ; switch data pointers ; get a byte from SOURCE ; increment SOURCE address ; switch data pointers ; write the byte to DEST ; increment DEST address ; check for 0 terminator ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. Rev. C - Aug. 24, 1999 13 TS80C51U2 TS83C51U2 TS87C51U2 7.3 Timer 2 The timer 2 in the TS80C51U2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the TEMIC 8-bit Microcontroller Hardware description. Refer to the TEMIC 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In TS80C51U2 Timer 2 includes the following enhancements: q q Auto-reload mode with up or down counter Programmable clock-output 7.3.1 Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the TEMIC 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution. 14 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 (:6 in X2 mode) XTAL1 FXTAL :12 FOSC T2 0 1 C/T2 T2CONreg TR2 T2CONreg (DOWN COUNTING RELOAD VALUE) FFh (8-bit) FFh (8-bit) T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting TOGGLE T2CONreg EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CONreg TIMER 2 INTERRUPT RCAP2L (8-bit) RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1) 7.3.2 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: F osc Clock – OutFrequency = -------------------------------------------------------------------------------------4 × ( 65536 – RCAP 2 H ⁄ RCAP 2 L ) For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: q q q q Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. Rev. C - Aug. 24, 1999 15 TS80C51U2 TS83C51U2 TS87C51U2 q To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. XTAL1 :2 (:1 in X2 mode) TR2 T2CON reg TL2 (8-bit) TH2 (8-bit) OVERFLOW RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2 Q D T2OE T2MOD reg T2EX EXEN2 T2CON reg EXF2 T2CON reg TIMER 2 INTERRUPT Figure 5. Clock-Out Mode C/T2 = 0 16 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 6. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number 7 6 EXF2 Bit Mnemonic TF2 5 RCLK 4 TCLK 3 EXEN2 Description 2 TR2 1 C/T2# 0 CP/RL2# Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock bit for UART_0 Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit for UART_0 Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 6 EXF2 5 RCLK_0 4 TCLK_0 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Reset Value = 0000 0000b Bit addressable Rev. C - Aug. 24, 1999 17 TS80C51U2 TS83C51U2 TS87C51U2 Table 7. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 Bit Number 7 6 Bit Mnemonic - 5 - 4 - 3 Description 2 - 1 T2OE 0 DCEN Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. 6 - 5 - 4 - 3 - 2 - 1 T2OE 0 DCEN Reset Value = XXXX XX00b Not bit addressable 18 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.4 TS80C51U2 Serial I/O Ports enhancements The serial I/O ports in the TS80C51U2 are compatible with the serial I/O port in the 80C52. They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O ports include the following enhancements: q q Framing error detection Automatic address recognition As these improvements apply to both UART, most of the time in the following lines, there won’t be any reference to UART_0 or UART_1, but only to UART, generally speaking. Idem for the bits in registers. 7.4.1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 6). SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON_0 for UART_0 (98h) (SCON_1 for UART_1 (C0h)) Set FE bit if stop bit is 0 (framing error) (SMOD0_0 = 1 for UART_0) SM0 to UART mode control (SMOD0_0 = 0 for UART_0) SMOD1_0 SMOD0_0 POF GF1 GF0 PD IDL PCON for UART_0 (87h) (SMOD bits for UART_1 are located in BDRCON_1) To UART framing error control Figure 6. Framing Error Block Diagram When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set. Rev. C - Aug. 24, 1999 19 TS80C51U2 TS83C51U2 TS87C51U2 Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.). RXD D0 D1 D2 D3 D4 D5 D6 D7 Start bit RI SMOD0=X FE SMOD0=1 Data byte Stop bit Figure 7. UART Timings in Mode 1 RXD D0 D1 D2 D3 D4 D5 D6 D7 D8 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Data byte Ninth Stop bit bit Figure 8. UART Timings in Modes 2 and 3 7.4.2 Automatic Address Recognition The automatic address recognition feature is enabled for each UART when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). 7.4.3 Given Address Each UART has an individual address that is specified in SADDR_0 or SADDR_1 register; the SADEN_0 or SADEN_1 register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example 20 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR SADEN Given 0101 0110b 1111 1100b 0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A: SADDR SADEN Given SADDR SADEN Given SADDR SADEN Given 1111 0001b 1111 1010b 1111 0X0Xb 1111 0011b 1111 1001b 1111 0XX1b 1111 0010b 1111 1101b 1111 00X1b Slave B: Slave C: The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). 7.4.4 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR SADEN Broadcast =SADDR OR SADEN 0101 0110b 1111 1100b 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1X11b, SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B, SADDR= 1111 0010b SADEN 1111 1101b Broadcast 1111 1111b Slave B: Slave C: For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 7.4.5 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. Rev. C - Aug. 24, 1999 21 TS80C51U2 TS83C51U2 TS87C51U2 7.4.6 Baud Rate Selection for UART0_0 for mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. TIMER1_BRG TIMER2_BRG RCLK_0 INT_BRG_0 RBCK_0 TIMER1_BRG TIMER2_BRG TCLK_0 INT_BRG_0 TBCK_0 0 1 TIMER_BRG 0 1 / 16 Tx_0 Clock 0 1 TIMER_BRG 0 1 / 16 Rx_0 Clock Figure 9. Baud Rate selection 7.4.7 Baud Rate Selection for UART1_1 for mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the BDRCON_1 register. TIMER1_BRG TIMER2_BRG RCLK_1 INT_BRG_1 RBCK_1 TIMER1_BRG TIMER2_BRG TCLK_1 INT_BRG_1 TBCK_1 0 1 TIMER_BRG 0 1 / 16 Tx_1 Clock 0 1 TIMER_BRG 0 1 / 16 Rx_1 Clock Figure 10. Baud Rate selection 22 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.4.8 Baud Rate selection table for UART_0 TCLK_0 0 1 0 1 X X 0 1 X RCLK_0 0 0 1 1 0 1 X X X TBCK_0 0 0 0 0 1 1 0 0 1 RBCK_0 0 0 0 0 0 0 1 1 1 Clock Source for UART_0 Tx Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG_0 INT_BRG_0 Timer 1 Timer 2 INT_BRG_0 Clock Source UART_0 Rx Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 2 INT_BRG_0 INT_BRG_0 INT_BRG_0 7.4.9 Baud Rate selection table for UART_1 TCLK_1 0 1 0 1 X X 0 1 X RCLK_1 0 0 1 1 0 1 X X X TBCK_1 0 0 0 0 1 1 0 0 1 RBCK_1 0 0 0 0 0 0 1 1 1 Clock Source for UART_1 Tx Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG_1 INT_BRG_1 Timer 1 Timer 2 INT_BRG_1 Clock Source UART_1 Rx Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 2 INT_BRG_1 INT_BRG_1 INT_BRG_1 7.4.10 Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the X2 bit in CKON register, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1_0 bit in PCON register (for UART_0) or SMOD1_1 in BDRCON_1 register (for UART_1). The Internal Baud Rate Generator is common to both UARTs: SMOD1_0 /2 XTAL1 /2 FXTAL X2 SPD BRR SMOD1_1 0 1 /6 0 1 0 1 INT_BRG_0 auto reload counter BRG overflow BRL /2 0 1 INT_BRG_1 Figure 11. Internal Baud Rate Rev. C - Aug. 24, 1999 23 TS80C51U2 TS83C51U2 TS87C51U2 q for UART_1 Baud_Rate = 2SMOD1_1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] 2SMOD1_1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate 2SMOD1_0 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] 2SMOD1_0 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate (BRL) = 256 q for UART_0 Baud_Rate = (BRL) = 256 - Example of computed value when X2=1, SMOD1=1, SPD=1 Baud Rates FXTAL = 16.384 MHz BRL 115200 57600 38400 28800 19200 9600 4800 247 238 229 220 203 149 43 FXTAL = 24MHz BRL 243 230 217 204 178 100 - Error (%) 1.23 1.23 1.23 1.23 0.63 0.31 1.23 Error (%) 0.16 0.16 0.16 0.16 0.16 0.16 - Example of computed value when X2=0, SMOD1=0, SPD=0 Baud Rates FOSC = 16.384 MHz BRL 4800 2400 1200 600 247 238 220 185 FOSC = 24MHz BRL 243 230 202 152 Error (%) 1.23 1.23 1.23 0.16 Error (%) 0.16 0.16 3.55 0.16 The baud rate generator can be used for mode 1 or 3 (refer to figures 9 and 10), but also for mode 0 for both UARTs, thanks to the bit SRC located in BDRCON register (Table 12) 24 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.5 UARTs registers SADEN_0 - Slave Address Mask Register for UART_0 (B9h) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b SADEN_1 - Slave Address Mask Register for UART_1 (BAh) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b SADDR_0 - Slave Address Register for UART_0 (A9h) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b SADDR_1 - Slave Address Register for UART_1 (AAh) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b SBUF_0 - Serial Buffer Register for UART_0 (99h) 7 6 5 4 3 2 1 0 Reset Value = XXXX XXXXb SBUF_1 - Serial Buffer Register for UART_1 (C1h) 7 6 5 4 3 2 1 0 Reset Value = XXXX XXXXb BRL - Baud Rate Reload Register for the internal baud rate generator, UART_0 and UART_1 (9Ah) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b Rev. C - Aug. 24, 1999 25 TS80C51U2 TS83C51U2 TS87C51U2 Table 8. SCON Register SCON_0 - Serial Control Register for UART_0 (98h) 7 FE_0/ SM0_0 Bit Number 7 6 SM1_0 5 SM2_0 4 REN_0 3 TB8_0 2 RB8_0 1 TI_0 0 RI_0 Bit Mnemonic FE_0 Description Framing Error bit (SMOD0_0=1) for UART_0 Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0_0 must be set to enable access to the FE bit Serial port Mode bit 0 (SMOD0_0=0) for UART_0 Refer to SM1 for serial port mode selection. SMOD0_0 must be cleared to enable access to the SM0_0 bit Serial port Mode bit 1 for UART_0 SM1_0 SM0_0 Mode Description SM0_0 Baud Rate FXTAL/12 (FXTAL/6 X2 mode) Variable FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode) Variable 6 SM1_0 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART 5 SM2_0 Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_0 Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. Reception Enable bit for UART_0 Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_0. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_0 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 4 REN_0 3 TB8_0 2 RB8_0 1 TI_0 Transmit Interrupt flag for UART_0 Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag for UART_0 Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes. 0 RI_0 Reset Value = 0000 0000b Bit addressable 26 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 9. SCON Register SCON_1 - Serial Control Register for UART_1 (C0h) 7 FE_1/ SM0_1 Bit Number 7 6 SM1_1 5 SM2_1 4 REN_1 3 TB8_1 2 RB8_1 1 TI_1 0 RI_1 Bit Mnemonic FE_1 Description Framing Error bit (SMOD0_1=1) for UART_1 Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0_1 must be set to enable access to the FE bit Serial port Mode bit 0 (SMOD0_1=0) for UART_1 Refer to SM1 for serial port mode selection. SMOD0_1 must be cleared to enable access to the SM0_1 bit Serial port Mode bit 1 for UART_1 SM1_1 SM0_1 Mode Description SM0_1 Baud Rate FXTAL/12 (FXTAL/6 X2 mode) Variable FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode) Variable 6 SM1_1 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART 5 SM2_1 Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_1 Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. Reception Enable bit for UART_1 Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_1. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_1 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 4 REN_1 3 TB8_1 2 RB8_1 1 TI_1 Transmit Interrupt flag for UART_1 Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag for UART_1 Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes. 0 RI_1 Reset Value = 0000 0000b Bit addressable Rev. C - Aug. 24, 1999 27 TS80C51U2 TS83C51U2 TS87C51U2 Table 10. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number 7 6 EXF2 Bit Mnemonic TF2 5 RCLK 4 TCLK 3 EXEN2 Description 2 TR2 1 C/T2# 0 CP/RL2# Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock bit for UART_0 Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit for UART_0 Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 6 EXF2 5 RCLK_0 4 TCLK_0 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Reset Value = 0000 0000b Bit addressable 28 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 11. PCON Register PCON - Power Control Register (87h) 7 SMOD1_0 Bit Number 7 6 SMOD0_0 Bit Mnemonic SMOD1_0 5 - 4 POF 3 GF1 Description 2 GF0 1 PD 0 IDL Serial port Mode bit 1 for UART_0 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART_0 Clear to select SM0_0 bit in SCON_0 register. Set to to select FE_0 bit in SCON_0 register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 6 SMOD0_0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Rev. C - Aug. 24, 1999 29 TS80C51U2 TS83C51U2 TS87C51U2 Table 12. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 Bit Number 7 6 6 Bit Mnemonic - 5 - 4 BRR 3 TBCK_0 2 RBCK_0 1 SPD 0 SRC Description Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Clear to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART_0 Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART_0 Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART_0 Clear to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART_0 and UART_1 Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0.. 5 - 4 BRR 3 TBCK_0 2 RBCK_0 1 SPD 0 SRC Reset Value = XXX0 0000b 30 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 13. BDRCON_1 Register BDRCON_1 - Baud Rate Control Register for UART_1 (9Ch) 7 SMOD1_1 Bit Number 7 6 SMOD0_1 Bit Mnemonic SMOD1_1 5 RCLK_1 4 TCLK_1 3 TBCK_1 2 RBCK_1 1 - 0 - Description Serial port Mode bit 1 for UART_1 Set to select double baud rate, in mode 1, 2 and 3. SCON Select bit for UART_1 Clear to select SM0_1 bit in SCON_1 register.. Set to to select FE_1 bit in SCON_1 register. Receive Clock bit for UART_1 Clear to select Timer 1 as Receive Baud Rate Generator for the UART_1 Set to Select Timer 2 as the Receive Baud Rate Generator for the UART_1 Transmit Clock bit for UART_1 Clear to select Timer 1 as Transmit Baud Rate Generator for the UART_1 Set to Select Timer 2 as the Transmit Baud Rate Generator for the UART_1. Transmission Baud rate Generator Selection bit for UART_1 Clear to select Timer 1 or Timer 2 for the Baud Rate Generator, for Tx. Set to select internal Baud Rate Generator for Tx. Reception Baud Rate Generator Selection bit for UART_1 Clear to select Timer 1 or Timer 2 for the Baud Rate Generator for Rx. Set to select internal Baud Rate Generator for Rx. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. 6 SMOD0_1 5 RCLK_1 4 TCLK_1 3 TBCK_1 2 RBCK_1 1 0 - Reset Value = 0000 00XXb Rev. C - Aug. 24, 1999 31 TS80C51U2 TS83C51U2 TS87C51U2 7.6 Alternate function on Port 1 The M1UA_1 and M0UA_1 bits located into AUXR register at bit location 7 and 6 permit to validate alternate functions located on Port 1. Following the combination of these two bits, the TxD_1 output and RxD_1 input of UART_1 take place on Port 1 pins (two different locations are possible) and the other locations of TxD_1 and RxD_1 available only for 44-pin package are no more valid. Table 14. AUXR Register AUXR - Auxiliary Register (8Eh) 7 M1UA_1 Bit Number 7 6 M0UA_1 Bit Mnemonic M1UA_1 5 - 4 - 3 Description 2 - 1 - 0 AO Multiplex I/Os of UART_1 bit 1 This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins. Multiplex I/Os of UART_1 bit 0 This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins. M1UA_1M0UA_1Result 00 UART_1 pins are disabled. 01 UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only. 10 UART_1 pins are alternate functions of P1 located at P1.2 and P1.3. 11 UART_1 pins are alternate functions of P1 located at P1.6 and P1.7. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. 6 M0UA_1 5 - 4 - 3 - 2 - 1 - 0 AO Reset Value = 00XX XXX0b Not bit addressable 32 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.7 Interrupt System The TS80C51U2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the two serial port interrupts. These interrupts are shown in Figure 12. High priority interrupt 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 3 0 3 0 IPH, IP Interrupt polling sequence, decreasing from high to low priority RI_0 TI_0 TF2 EXF2 RI_1 TI_1 Individual Enable Global Disable Figure 12. Interrupt Control System Low priority interrupt Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 16.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 17.) and in the Interrupt Priority High register (See Table 18.). shows the bit values and priority levels associated with each combination. The second UART interrupt vector is located at address 0033H. All other vector addresses are the same as standard C52 devices. Rev. C - Aug. 24, 1999 33 TS80C51U2 TS83C51U2 TS87C51U2 Table 15. Priority Level Bit Values IPH.x 0 0 1 1 IP.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 16. IE Register IE - Interrupt Enable Register (A8h) 7 EA Bit Number 6 ES_1 Bit Mnemonic 5 ET2 4 ES_0 3 ET1 Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. Serial port Enable bit for UART_1 Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Serial port Enable bit for UART_0 Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. 2 EX1 1 ET0 0 EX0 7 EA 6 ES_1 5 ET2 4 ES_0 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value = 0000 0000b Bit addressable 34 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 17. IP Register IP - Interrupt Priority Register (B8h) 7 Bit Number 7 6 PS_1 Bit Mnemonic - 5 PT2 4 PS_0 3 PT1 Description 2 PX1 1 PT0 0 PX0 Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port Priority bit for UART_1 Refer to PSH for priority level. Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. Serial port Priority bit for UART_0 Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level. 6 PS_1 5 PT2 4 PS_0 3 PT1 2 PX1 1 PT0 0 PX0 Reset Value = X000 0000b Bit addressable Rev. C - Aug. 24, 1999 35 TS80C51U2 TS83C51U2 TS87C51U2 Table 18. IPH Register IPH - Interrupt Priority High Register (B7h) 7 Bit Number 7 6 PSH_1 Bit Mnemonic - 5 PT2H 4 PSH_0 3 PT1H Description 2 PX1H 1 PT0H 0 PX0H Reserved The value read from this bit is indeterminate. Do not set this bit. Serial port Priority High bit for UART_1 PSH_1 PS_1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial port Priority High bit for UART_0 PSH_0 PS_0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 6 PSH_1 5 PT2H 4 PSH_0 3 PT1H 2 PX1H 1 PT0H 0 PX0H Reset Value = X000 0000b Not bit addressable 36 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.8 Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 7.9 Power-Down Mode To save maximum power, a power-down mode can be invoked by software (Refer to 7.4.6, PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power-down. To properly terminate power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 13. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C51U2 into power-down mode. INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Figure 13. Power-Down Exit Waveform Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Rev. C - Aug. 24, 1999 37 TS80C51U2 TS83C51U2 TS87C51U2 Table 19. The state of ports during idle and power-down modes Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Port Data* Floating Port Data* Floating PORT1 Port Port Port Port Data Data Data Data PORT2 Port Data Address Port Data Port Data PORT3 Port Port Port Port Data Data Data Data * Port 0 can force a "zero" level. A "one" Level will leave port floating. 38 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.10 Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. 7.10.1 Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 21. (SFR0A7h). Table 20. WDTRST Register WDTRST Address (0A6h) 7 Reset value X 6 X 5 X 4 X 3 X 2 X 1 X Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. Rev. C - Aug. 24, 1999 39 TS80C51U2 TS83C51U2 TS87C51U2 Table 21. WDTPRG Register WDTPRG Address (0A7h) 7 T4 Bit Number 7 6 5 4 3 2 1 0 6 T3 Bit Mnemonic T4 T3 T2 T1 T0 S2 S1 S0 5 T2 4 T1 3 T0 Description 2 S2 1 S1 0 S0 Reserved Do not try to set or clear this bit. WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out (214 - 1) machine cycles, 16.3 ms @ 12 MHz (215 - 1) machine cycles, 32.7 ms @ 12 MHz (216 - 1) machine cycles, 65.5 ms @ 12 MHz (217 - 1) machine cycles, 131 ms @ 12 MHz (218 - 1) machine cycles, 262 ms @ 12 MHz (219 - 1) machine cycles, 542 ms @ 12 MHz (220 - 1) machine cycles, 1.05 s @ 12 MHz (221 - 1) machine cycles, 2.09 s @ 12 MHz Reset value XXXX X000 7.10.2 WDT during Power Down and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51U2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51U2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 40 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.11 ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C51U2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51U2; the following sequence must be exercised: q q Pull ALE low while the device is in reset (RST high) and PSEN is high. Hold ALE low as RST is deactivated. While the TS80C51U2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 22. External Pin Status during ONCE Mode ALE Weak pull-up PSEN Weak pull-up Port 0 Float Port 1 Weak pull-up Port 2 Weak pull-up Port 3 Weak pull-up XTAL1/2 Active Rev. C - Aug. 24, 1999 41 TS80C51U2 TS83C51U2 TS87C51U2 7.12 Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (See Table 23.). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 23. PCON Register PCON - Power Control Register (87h) 7 SMOD1_0 Bit Number 7 6 SMOD0_0 Bit Mnemonic SMOD1_0 5 - 4 POF 3 GF1 Description 2 GF0 1 PD 0 IDL Serial port Mode bit 1 for UART_0 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART_0 Clear to select SM0_0 bit in SCON_0 register. Set to to select FE_0 bit in SCON_0 register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 6 SMOD0_0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 00X1 0000b Not bit addressable 42 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 7.13 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 24. AUXR Register AUXR - Auxiliary Register (8Eh) 7 M1UA_1 Bit Number 7 6 M0UA_1 Bit Mnemonic M1UA_1 5 - 4 - 3 Description 2 - 1 - 0 AO Multiplex I/Os of UART_1 bit 1 This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins. Multiplex I/Os of UART_1 bit 0 This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins. M1UA_1M0UA_1Result 00 UART_1 pins are disabled. 01 UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only. 10 UART_1 pins are alternate functions of P1 located at P1.2 and P1.3. 11 UART_1 pins are alternate functions of P1 located at P1.6 and P1.7. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. 6 M0UA_1 5 - 4 - 3 - 2 - 1 - 0 AO Reset Value = 00XX XXX0b Not bit addressable Rev. C - Aug. 24, 1999 43 TS80C51U2 TS83C51U2 TS87C51U2 8. TS80C51U2 ROM 8.1 ROM Structure The TS83C51U2 ROM memory is divided in three different arrays: q q q the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes. the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 8.2 ROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 8.2.1 Encryption Array Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 8.2.2 Program Lock Bits The lock bits when programmed according to Table 25. will provide different level of protection for the on-chip code and data. Table 25. Program Lock bits Program Lock Bits Protection description LB3 U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset. Security level 1 LB1 U LB2 U 2 P U U U: unprogrammed P: programmed 8.2.3 Signature bytes The TS83C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 10. 8.2.4 Verify Algorithm Refer to 9.3.4 44 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 9. TS87C51U2 EPROM 9.1 EPROM Structure The TS87C51U2 EPROM is divided in two different arrays: q q the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes. the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. In addition a third non programmable array is implemented: q 9.2 EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 9.2.1 Encryption Array Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 9.2.2 Program Lock Bits The three lock bits, when programmed according to Table 26., will provide different level of protection for the on-chip code and data. Table 26. Program Lock bits Program Lock Bits Protection description LB3 U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, also external execution is disabled. Security level 1 LB1 U LB2 U 2 3 4 P U U U P U U U P U: unprogrammed, P: programmed WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. Rev. C - Aug. 24, 1999 45 TS80C51U2 TS83C51U2 TS87C51U2 9.2.3 Signature bytes The TS87C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 10. 9.3 EPROM Programming 9.3.1 Set-up modes In order to program and verify the EPROM or to read the signature bytes, the TS87C51U2 is placed in specific set-up modes (See Figure 14.). Control and program signals must be held at the levels indicated in Table 27. 9.3.2 Definition of terms Address Lines:P1.0-P1.7, P2.0-P2.5 respectively for A0-A13. Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals:ALE/PROG, EA/VPP. Table 27. EPROM Set-Up Modes Mode Program Code data RST 1 PSEN 0 ALE/ PROG EA/ VPP 12.75V P2.6 0 P2.7 1 P3.3 1 P3.6 1 P3.7 1 Verify Code data Program Encryption Array Address 0-3Fh Read Signature Bytes 1 0 1 1 0 0 1 1 1 0 12.75V 0 1 1 0 1 1 0 1 1 0 0 0 0 Program Lock bit 1 1 0 12.75V 1 1 1 1 1 Program Lock bit 2 1 0 12.75V 1 1 1 0 0 Program Lock bit 3 1 0 12.75V 1 0 1 1 0 46 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 +5V PROGRAM SIGNALS* EA/VPP ALE/PROG P0.0-P0.7 RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 XTAL1 D0-D7 VCC P1.0-P1.7 P2.0-P2.5 A0-A7 A8-A13 CONTROL SIGNALS* 4 to 6 MHz VSS GND * See Table 31. for proper value on these inputs Figure 14. Set-Up Modes Configuration 9.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the TS87C51U2 the following sequence must be exercised: q q q q q q Step 1: Activate the combination of control signals. Step 2: Input the valid address on the address lines. Step 3: Input the appropriate data on the data lines. Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V). Step 5: Pulse ALE/PROG once. Step 6: Lower EA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 15.). 9.3.4 Verify algorithm Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the TS87C51U2. P 2.7 is used to enable data output. To verify the TS87C51U2 code the following sequence must be exercised: q q q Step 1: Activate the combination of program and control signals. Step 2: Input the valid address on the address lines. Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 15.) The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Rev. C - Aug. 24, 1999 47 TS80C51U2 TS83C51U2 TS87C51U2 Programming Cycle A0-A12 D0-D7 Data In Data Out Read/Verify Cycle 100µs ALE/PROG 12.75V 5V 0V EA/VPP Control signals Figure 15. Programming and Verification Signal’s Waveform 9.4 EPROM Erasure (Windowed Packages Only) Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF). 9.4.1 Erasure Characteristics The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. 48 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 10. Signature Bytes The TS83/87C51U2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 27. for Read Signature Bytes. Table 28. shows the content of the signature byte for the TS83/87C51U2. Table 28. Signature Bytes Content Location 30h 31h 60h 60h 61h Contents 58h 57h 2Bh ABh FFh Family Code: C51 X2 Comment Manufacturer Code: TEMIC Product name: TS83C51U2 Product name: TS87C51U2 Product revision number Rev. C - Aug. 24, 1999 49 TS80C51U2 TS83C51U2 TS87C51U2 11. Electrical Characteristics 11.1 Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: C = commercial I = industrial Storage Temperature Voltage on VCC to VSS Voltage on VPP to VSS Voltage on Any Pin to VSS Power Dissipation 0°C to 70°C -40°C to 85°C -65°C to + 150°C -0.5 V to + 7 V -0.5 V to + 13 V -0.5 V to VCC + 0.5 V 1 W(2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 11.2 Power consumption measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In TEMIC new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, TEMIC presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. 50 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 11.3 DC Parameters for Standard Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Table 29. DC Parameters in Standard Voltage Symbol VIL VIH VIH1 VOL Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3 (6) Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 Unit V V V V V V Test Conditions IOL = 100 µA(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOL = 200 µA(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) IOL = 100 µA(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOH = -10 µA IOH = -30 µA IOH = -60 µA VCC = 5 V ± 10% VOL1 Output Low Voltage, port 0 (6) 0.3 0.45 1.0 V V V VOL2 Output Low Voltage, ALE, PSEN 0.3 0.45 1.0 V V V VOH Output High Voltage, ports 1, 2, 3 VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V VOH1 Output High Voltage, port 0 VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V ± 10% VOH2 Output High Voltage,ALE, PSEN VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V IOH = -100 µA IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V ± 10% RRST IIL ILI ITL CIO IPD ICC under RESET RST Pulldown Resistor Logical 0 Input Current ports 1, 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 Capacitance of I/O Buffer 50 90 (5) 200 -50 ±10 -650 10 kΩ µA µA µA pF µA Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V Fc = 1 MHz TA = 25°C 2.0 V < VCC < 5.5 V(3) VCC = 5.5 V(1) mA Power Down Current Power Supply Current Maximum values, X1 mode: (7) 20 (5) 50 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 Rev. C - Aug. 24, 1999 51 TS80C51U2 TS83C51U2 TS87C51U2 Symbol ICC operating Parameter Power Supply Current Maximum values, X1 mode: (7) Min Typ Max 3 + 0.6 Freq (MHz) @12MHz 10.2 @16MHz 12.6 Unit mA Test Conditions VCC = 5.5 V(8) ICC idle Power Supply Current Maximum values, X1 mode: (7) 0.25+0.3Freq (MHz) @12MHz 3.9 @16MHz 5.1 mA VCC = 5.5 V(2) 11.4 DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. Table 30. DC Parameters for Low Voltage Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ILI ITL RRST CIO Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3 (6) Output Low Voltage, port 0, ALE, PSEN (6) Output High Voltage, ports 1, 2, 3 Output High Voltage, port 0, ALE, PSEN Logical 0 Input Current ports 1, 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 RST Pulldown Resistor Capacitance of I/O Buffer Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V Test Conditions IOL = 0.8 mA(4) IOL = 1.6 mA(4) IOH = -10 µA IOH = -40 µA Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V 0.9 VCC 0.9 VCC -50 ±10 -650 50 90 (5) 200 10 µA µA µA kΩ pF µA Fc = 1 MHz TA = 25°C VCC = 2.0 V to 5.5 V(3) VCC = 2.0 V to 3.3 V(3) IPD Power Down Current 20 (5) 10 (5) 50 30 ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) 1 + 0.2 Freq (MHz) @12MHz 3.4 @16MHz 4.2 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 VCC = 3.3 V(1) mA Power Supply Current Maximum values, X1 mode: (7) VCC = 3.3 V(8) mA 52 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Symbol ICC idle Parameter Power Supply Current Maximum values, X1 mode: (7) Min Typ Max 0.15 Freq (MHz) + 0.2 @12MHz 2 @16MHz 2.6 Unit mA Test Conditions VCC = 3.3 V(2) NOTES 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 20.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used.. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 18.). 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 19.). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 20.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 16. ICC Test Condition, under reset Rev. C - Aug. 24, 1999 53 TS80C51U2 TS83C51U2 TS87C51U2 VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 17. Operating ICC Test Condition VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P0 EA VCC All other pins are disconnected. Figure 18. ICC Test Condition, Idle Mode VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 19. ICC Test Condition, Power-Down Mode VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 Figure 20. Clock Signal Waveform for ICC Tests in Active and Idle Modes 54 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 11.5 AC Parameters 11.5.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA TA TA TA = = = = 0 to +70°C (commercial temperature range); VSS = -40°C to +85°C (industrial temperature range); VSS 0 to +70°C (commercial temperature range); VSS = -40°C to +85°C (industrial temperature range); VSS 0 V; VCC = 5 V ± 10%; -M and -V ranges. = 0 V; VCC = 5 V ± 10%; -M and -V ranges. 0 V; 2.7 V < VCC < 5.5 V; -L range. = 0 V; 2.7 V < VCC < 5.5 V; -L range. Table 31. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 31. Load Capacitance versus speed range, in pF Port 0 Port 1, 2, 3 ALE / PSEN -M 100 80 100 -V 50 50 30 -L 100 80 100 Table 33., Table 36. and Table 39. give the description of each AC symbols. Table 34., Table 37. and Table 40. give for each range the AC parameter. Table 35., Table 38. and Table 41. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 32. Max frequency for derating formula regarding the speed grade Freq (MHz) T (ns) -M X1 mode 40 25 -M X2 mode 20 50 -V X1 mode 40 25 -V X2 mode 30 33.3 -L X1 mode 30 33.3 -L X2 mode 20 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 25 (Table 35.) T= 50ns TLLIV= 2T - x = 2 x 50 - 25 = 75ns Rev. C - Aug. 24, 1999 55 TS80C51U2 TS83C51U2 TS87C51U2 11.5.2 External Program Memory Characteristics Table 33. Symbol Description Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction FloatAfter PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float Parameter Table 34. AC Parameters for Fix Clock Speed -M 40 MHz -V X2 mode 30 MHz 60 MHz equiv. Min 33 25 4 4 70 15 55 35 0 18 85 10 0 12 53 10 9 35 25 0 20 95 10 45 17 60 50 0 10 80 10 -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. Min 50 35 5 5 -L standard mode 30 MHz Min 33 52 13 13 Units Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Min 25 40 10 10 Max Max Min 25 42 12 12 Max Max Max ns ns ns ns 98 ns ns ns 55 ns ns 18 122 10 ns ns ns 78 10 50 65 18 75 30 0 56 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 35. AC Parameters for a Variable Clock: derating formula Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x -M 10 15 15 30 10 20 40 0 7 40 10 -V 8 13 13 22 8 15 25 0 5 30 10 -L 15 20 20 35 15 25 45 0 15 45 10 Units ns ns ns ns ns ns ns ns ns ns ns 11.5.3 External Program Memory Read Cycle 12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ Figure 21. External Program Memory Read Cycle Rev. C - Aug. 24, 1999 57 TS80C51U2 TS83C51U2 TS87C51U2 11.5.4 External Data Memory Characteristics Table 36. Symbol Description Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high Parameter 58 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 37. AC Parameters for a Fix Clock Speed -M 40 MHz -V X2 mode 30 MHz 60 MHz equiv. Min 85 85 100 0 30 160 165 50 75 10 160 15 0 10 40 7 100 30 47 7 107 9 0 27 15 0 18 98 100 70 55 80 15 165 17 0 35 5 60 0 35 165 175 95 45 70 5 155 10 0 45 13 -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. Min 125 125 -L standard mode 30 MHz Units Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Min 130 130 Max Max Min 135 135 Max Max Min 175 175 Max ns ns 137 ns ns 42 222 235 ns ns ns ns ns ns ns ns 0 53 ns ns 102 0 95 0 25 155 160 105 70 103 13 213 18 130 Rev. C - Aug. 24, 1999 59 TS80C51U2 TS83C51U2 TS87C51U2 Table 38. AC Parameters for a Variable Clock: derating formula Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x -M 20 20 25 0 20 40 60 25 25 25 15 15 10 0 15 15 -V 15 15 23 0 15 35 50 20 20 20 10 10 8 0 10 10 -L 25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11.5.5 External Data Memory Write Cycle ALE TWHLH PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX Figure 22. External Data Memory Write Cycle 60 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 11.5.6 External Data Memory Read Cycle ALE TLLDV TWHLH PSEN TLLWL TRLDV TRLRH TRHDZ TRHDX DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 RD TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TAVDV Figure 23. External Data Memory Read Cycle 11.5.7 Serial Port Timing - Shift Register Mode Table 39. Symbol Description Symbol TXLXL TQVHX TXHQX Serial port clock cycle time Output data set-up to clock rising edge Parameter Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid TXHDX TXHDV Table 40. AC Parameters for a Fix Clock Speed -M 40 MHz -V X2 mode 30 MHz 60 MHz equiv. Min 200 117 13 0 117 34 -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. Min 300 200 30 0 -L standard mode 30 MHz Units Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Min 300 200 30 0 Max Max Min 300 200 30 0 Max Max Min 400 283 47 0 Max ns ns ns ns 200 ns 117 117 Rev. C - Aug. 24, 1999 61 TS80C51U2 TS83C51U2 TS87C51U2 Table 41. AC Parameters for a Variable Clock: derating formula Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x -M -V -L Units ns 50 20 0 133 50 20 0 133 50 20 0 133 ns ns ns ns 11.5.8 Shift Register Timing Waveforms INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV VALID VALID TXHQX 1 2 TXHDX VALID VALID VALID VALID VALID 3 4 5 6 7 SET TI VALID SET RI Figure 24. Shift Register Timing Waveforms 62 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 11.5.9 EPROM Programming and Verification Characteristics TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating range while verifying Table 42. EPROM Programming Parameters Symbol VPP IPP 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ Parameter Programming Supply Voltage Programming Supply Current Oscillator Frquency Address Setup to PROG Low Adress Hold after PROG Min 12.5 Max 13 75 Units V mA MHz 4 48 TCLCL 6 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL Data Setup to PROG Low Data Hold after PROG (Enable) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Valid Data ENABLE Low to Data Valid Data Float after ENABLE 10 10 90 110 48 TCLCL 48 TCLCL 0 48 TCLCL µs µs µs 11.5.10 EPROM Programming and Verification Waveforms PROGRAMMING P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* P0 TDVGL TAVGL ALE/PROG TSHGL TGLGH EA/VPP CONTROL SIGNALS (ENABLE) VCC TEHSH VPP TGHSL VCC TELQV ADDRESS VERIFICATION ADDRESS TAVQV DATA IN TGHDX TGHAX DATA OUT TEHQZ * 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5 Figure 25. EPROM Programming and Verification Waveforms Rev. C - Aug. 24, 1999 63 TS80C51U2 TS83C51U2 TS87C51U2 11.5.11 External Clock Drive Characteristics (XTAL1) Table 43. AC Parameters Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Parameter Min 25 5 5 Max Units ns ns ns 5 5 60 ns ns % 11.5.12 External Clock Drive Waveforms VCC-0.5 V 0.45 V 0.7VCC 0.2VCC-0.1 V TCHCL TCLCX TCLCL TCHCX TCLCH Figure 26. External Clock Drive Waveforms 11.5.13 AC Testing Input/Output Waveforms VCC-0.5 V INPUT/OUTPUT 0.45 V 0.2VCC+0.9 0.2VCC-0.1 Figure 27. AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 11.5.14 Float Waveforms FLOAT VOH-0.1 V VLOAD VOL+0.1 V VLOAD+0.1 V VLOAD-0.1 V Figure 28. Float Waveforms 64 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 11.5.15 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED STATE4 P1 P2 STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2 THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION PCL OUT DATA SAMPLED PCL OUT DATA SAMPLED PCL OUT FLOAT P2 (EXT) READ CYCLE RD FLOAT INDICATES ADDRESS TRANSITIONS FLOAT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT FLOAT P2 WRITE CYCLE WR P0 DPL OR Rt OUT DATA OUT P2 PORT OPERATION OLD DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED NEW DATA P0 PINS SAMPLED INDICATES DPH OR P2 SFR TO PCH TRANSITION INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) RXD SAMPLED RXD SAMPLED Figure 29. Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. Rev. C - Aug. 24, 1999 65 TS80C51U2 TS83C51U2 TS87C51U2 12. Ordering Information TS 87C51U2 -V I B R -V: -L: -E : VCC: 5V +/- 10% 40 MHz, X1 mode 30 MHz, X2 mode VCC: 2.7 to 5.5 V 30 MHz, X1 mode 20 MHz, X2 mode Samples Packages: A: PDIL 40 B: PLCC 44 E: VQFP 44 (1.4mm) J: Window CDIL 40* K: Window CQPJ 44* Part Number TS80C51U2: ROMless TS83C51U2zzz: 16k ROM, zzz is the customer code TS87C51U2: 16k OTP EPROM Temperature Range I: Commercial and Industrial -40 to 85oC TEMIC Semiconductors (*) Check with TEMIC Sales Office for availability - Ceramic parts only for OTP (TS87C51U2) Ceramic packages (J, K) are available for prototyping, not for volume production. Conditioning R: Tape & Reel D: Dry Pack B: Tape & Reel and Dry Pack Table 44. Maximum Clock Frequency Code Standard Mode, oscillator frequency Standard Mode, internal frequency X2 Mode, oscillator frequency X2 Mode, internal equivalent frequency -M 40 40 20 40 -V 40 40 30 60 -L 30 30 20 40 Unit MHz MHz 66 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 Table 45. Possible Ordering Entries TS80C51U2 ROMless -VIA -VIB -VIE -LIA -LIB -LIE -EA -EB -EE -EJ -EK X X X X X X X X X TS83C51U2zzz 16K ROM X X X X X X TS87C51U2 16K OTP X X X X X X X X X X X q q q -Ex for samples Tape and Reel available for B and E packages Dry pack mandatory for E packages Rev. C - Aug. 24, 1999 67