73S8009R

73S8009R Low Cost Versatile Smart Card Interface Simplifying System Integration™ DS_8009R_056 APPLICATIONS • DESCRIPTION The 73S8009R is a very low-cost level shifter, single smart card (ICC) interface IC. The device includes a level shifter interface between a 3.3 V (typical) logic circuitry (host microcontroller) and an ISO-7816 / EMV smart card. The 73S8009R is designed to provide full electrical compliance with ISO-7816-3 EMV4.1 (EMV2000) and GSM11-11 specifications. In normal operating mode, for maximum designer flexibility, the host microcontroller is responsible for card activation and deactivation. The 73S8009R incorporates an ISO-7816-3 deactivation sequencer that controls the card signals in case of fault detection and card removal. Card presence and faults are reported to the host through an interrupt output. When the 73S8009R is ready to support a card with the selected voltage, a RDY signal informs the host it can initiate the card activation sequence. The 73S8009R supports 5V, 3V and 1.8V cards. Selection is done through 2 dedicated digital inputs. Level-shifters drive the card signals with the selected card voltage coming from an internal Low Drop-Out (LDO) voltage regulator. The LDO regulator is powered by a dedicated power supply input, VPC. Digital circuitry is separately powered by a digital power supply, VDD. Emergency card deactivation is initiated upon card extraction or any fault generated by the protection circuitry. The fault can be a card over-current, a VDD (digital power), a VPC (regulator power), a VCC (card power output) or an over-heating fault. A chip select digital input drives internal latches that allow the host controller to control multiple 73S8009R ICs in parallel. A power down digital input also allows the host microcontroller to place the IC in a very low-power mode making the 73S8009R particularly suitable for low-power and battery-powered applications. Auxiliary I/O lines are also available (SO28 package only) and make the 73S8009R suitable for all kind of cards, including synchronous (memory) cards. Rev. 1.3 • • • S et-Top-Box Conditional Access and Pay-per-View SIM card readers in DECT and GSM phones, GPRS, WIFI and VOIP devices DATA SHEET October 2009 Point of Sales & Transaction Terminals General purpose smart card readers ADVANTAGES • Lowest cost smart card interface IC on the market  Ideal to replace discrete designs in POS terminals and Set-Top-Boxes Traditional step-up converter is replaced by an LDO regulator  Greatly reduced power dissipation  Fewer external components are required  Better noise performance  Very low power dissipation Small format (4x4x0.8 mm) QFN20 package option • • FEATURES • Card Interface: • Complies with ISO-7816-3, EMV 4.0 and GSM 11-11 specifications • An LDO voltage regulator provides 1.8V / 3V / 5V to the card from an external power supply input • Provides at least 90 mA to the card • ISO-7816-3 card emergency deactivation sequencer • Protection includes 3 voltage supervisors that detect voltage drops on VCC (card), VDD (digital) and VPC (regulator) power supplies • Over-current detection, 150 mA max. • 2 card detection inputs, 1 for each user polarity • Auxiliary I/O lines for C4 / C8 contact signals • Card CLK clock frequency up to 20 MHz © 2009 Teridian Semiconductor Corporation 1 73S8009R Data Sheet • System Controller Interface • Five signal images of the card signals (RSTIN, CLKIN, IOUC, AUX1UC, AUX2UC) • Two inputs select card voltage (CMDVCC%, CMDVCC#) • Two Interrupt outputs (OFF, RDY) inform the system controller of card presence / faults and the interface status • Chip select input (CS) • Power down input (PWRDN) • DS_8009R_056 Regulator Power Supply (VPC): • Class A-B-C readers: 5V, 3V and 1.8V cards: 4.75 V to 6.0 V Digital Interface (VDD): 2.7 V to 3.6 V 6 kV ESD protection on the card interface SO28 or QFN20 package • • • FUNCTIONAL DIAGRAM VDD [17] 28 VPC [9] 15 VCC FAULT VOLTAGE REFERENCE bias currents VPC FAULT vref LDO REGULATOR 20 [12] 22 [14] VCC GND CMDVCC5 CMDVCC3 8 [2] 9 [3] 4 [20] OFF RDY PWRDN CS 10 [4] RSTIN 11 [5] CLKIN 12 [6] 13 [7] 1 [18] CONTROL LOGIC RESET BUFFER 21 [13] RST CLOCK BUFFER 19 [11] CLK 26 [16] 16 [10] PRES PRES 1.5MHz TEMP FAULT R-C OSC. 5 [1] IOUC AUX1UC AUX2UC 6 7 OVER TEMP 25 [15] I/O AUX1 AUX2 SMART CARD I/O BUFFERS 24 23 27 GND Pin numbers reference the SO28 package [Pin numbers] reference the QFN20 Package Figure 1: 73S8009R Block Diagram Rev. 1.3 2 DS_8009R_056 73S8009R Data Sheet Table of Contents 1 2 Pinout ............................................................................................................................................. 5 Electrical Specifications................................................................................................................ 8 2.1 Absolute Maximum Ratings ..................................................................................................... 8 2.2 Recommended Operating Conditions ...................................................................................... 8 2.3 Smart Card Interface Requirements ........................................................................................ 9 2.4 Digital Signals Characteristics ............................................................................................... 11 2.5 DC Characteristics ................................................................................................................ 11 2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 12 Applications Information ............................................................................................................. 13 3.1 Example 73S8009R Schematics ........................................................................................... 13 3.2 System Controller Interface ................................................................................................... 14 3.3 Power Supply and Voltage Supervision ................................................................................. 14 3.4 Card Power Supply ............................................................................................................... 14 3.5 Over-temperature Monitor ..................................................................................................... 15 3.6 Activation and Deactivation Sequence................................................................................... 15 3.7 OFF and Fault Detection ....................................................................................................... 16 3.8 Power-down Operation.......................................................................................................... 17 3.9 Chip Select ........................................................................................................................... 18 3.10 I/O Circuitry and Timing......................................................................................................... 18 Mechanical Drawings .................................................................................................................. 20 4.1 20-pin QFN ........................................................................................................................... 20 4.2 28-Pin SO ............................................................................................................................. 21 Ordering Information ................................................................................................................... 22 Related Documentation ............................................................................................................... 22 Contact Information..................................................................................................................... 22 3 4 5 6 7 Revision History .................................................................................................................................. 23 Rev. 1.3 3 73S8009R Data Sheet DS_8009R_056 Figures Figure 1: 73S8009R Block Diagram ......................................................................................................... 2 Figure 2: 73S8009R 20-Pin QFN Pinout .................................................................................................. 5 Figure 3: 73S8009R 28-Pin SO Pinout..................................................................................................... 5 Figure 4: Typical 73S8009R Application Schematic ............................................................................... 13 Figure 5: Activation Sequence ............................................................................................................... 15 Figure 6: Deactivation Sequence ........................................................................................................... 16 Figure 7: OFF Activity Outside and Inside a Card Session ..................................................................... 17 Figure 8: Power-down Operation ........................................................................................................... 17 Figure 9: CS Timing Definitions.............................................................................................................. 18 Figure 10: I/O and I/OUC State Diagram ................................................................................................ 19 Figure 11: I/O to I/OUC Delay Timing Diagram....................................................................................... 19 Figure 12: 20-pin QFN Package Dimensions ......................................................................................... 20 Figure 13: 28-Pin SO Package Dimensions ........................................................................................... 21 Tables Table 1: 73S8009R Pin Definitions .......................................................................................................... 6 Table 2: Absolute Maximum Device Ratings ............................................................................................ 8 Table 3: Recommended Operating Conditions ......................................................................................... 8 Table 4: DC Smart Card Interface Requirements ..................................................................................... 9 Table 5: Digital Signals Characteristics .................................................................................................. 11 Table 6: DC Characteristics ................................................................................................................... 11 Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 12 Table 8: Choice of VCC Pin Capacitor ................................................................................................... 15 Table 9: Order Numbers and Packaging Marks ...................................................................................... 22 4 Rev. 1.3 DS_8009R_056 73S8009R Data Sheet 1 Pinout The 73S8009R is supplied as a 20-pin QFN package and as a 28-pin SO package. TEST1 PRES 16 15 14 OFF 20 19 18 CS I/OUC CMDVCC% CMDVCC# RSTIN CLKIN 1 2 3 4 5 17 VDD I/O VCC RST GND CLK TERIDIAN 73S8009R 13 12 11 PWRDN TEST2 RDY VPC Figure 2: 73S8009R 20-Pin QFN Pinout (Top View) CS TEST1 N/C OFF I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# RSTIN CLKIN RDY PWRDN TEST2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PRES VDD GND PRES I/O AUX1 AUX2 VCC RST GND CLK N/C N/C PRES VPC Figure 3: 73S8009R 28-Pin SO Pinout Rev. 1.3 10 6 7 8 9 5 73S8009R Data Sheet Table 1 describes the pin functions for the device. Table 1: 73S8009R Pin Definitions Pin Name I/O AUX1 AUX2 RST CLK Pin (SO28) 25 24 23 21 19 Pin (QFN20) 15 NA NA 13 11 Type Description DS_8009R_056 Card Interface IO IO IO O O Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. Card reset: provides reset signal to card. Card clock: provides clock signal to card. The rate of this clock is determined by the external clock frequency provided on pin CLKIN. Card Presence switch: active high indicates card is present. Should be tied to GND when not used, but includes a highimpedance pull-down current source. Card Presence switch: active low indicates card is present. Should be tied to VDD when not used, but includes a highimpedance pull-up current source. Card power supply – logically controlled by the sequencer, output of LDO regulator. Requires an external filter capacitor to GND. Card ground. Clock source for the card clock. This pin must be tied to GND in typical applications. This pin must be tied to GND in typical applications. Non-connected pin. System interface supply voltage and supply voltage for internal circuitry. LDO regulator power supply source. GND I Ground. When CS = 1, the control and signal pins are configured normally. When CS is set low, CMDVCC%, RSTIN, and CMDVCC# are latched, IOUC, AUX1UC, and AUX2UC are set to high-impedance pull-up mode and do not pass data to or from the smart card. Signals RDY and OFF are disabled to prevent a low output and the internal pull-up resistors are disconnected. Interrupt signal to the processor. Active low, multi-function indicating fault conditions and card presence. Open drain output configuration. It includes an internal 20 kΩ pull-up to VDD. The pull-up is disabled in PWRDN and CS=0 modes. Rev. 1.3 PRES 26 16 I PRES 16 10 I VCC 22 14 PSO GND CLKIN TEST1 TEST2 NC VDD VPC GND CS 20 11 2 14 3,17,18 28 15 27 1 NA 5 19 8 NA 17 9 12 18 GND I – – – Miscellaneous Inputs and Outputs Power Supply and Ground Microcontroller Interface OFF 4 20 O 6 DS_8009R_056 Pin Name I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# Pin (SO28) 5 6 7 8 9 Pin (QFN20) 1 NA NA 2 3 73S8009R Data Sheet Type I/O I/O I/O I I Description System controller data I/O to/from the card. Includes a pullup resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. Logic low on one or both of these pins will cause the LDO to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table: CMDVCC% CMDVCC# VCC Output Voltage 0 0 1.8 V 0 1 5.0 V 1 0 3.0 V 1 1 LDO off Refer to for additional information on the CMDVCC% and CMDVCC# operation. RSTIN RDY 10 12 4 6 I O Reset Input. This signal is the reset command to the card. Signal to controller indicating the 73S8009R is ready because VCC is above the required value after CMDVCC% and/or CMDVCC# is asserted low. A 20 KΩ pull-up resistor to VDD is provided internally. The pull-up is disabled in PWRDN and CS=0 modes. PWRDN=1 puts the circuit into low-power mode with all analog functions disabled. The circuit will recover from the PWRDN state in the same manner as recovery from a POR event, taking approximately 1 ms. PWRDN assertion when either CMDVCC% or CMDVCC# is low has no effect and is ignored. There is no pull-up or pull-down provided on this pin. PWRDN 13 7 I Rev. 1.3 7 73S8009R Data Sheet DS_8009R_056 2 Electrical Specifications This section provides the following:       Absolute Maximum Ratings Recommended Operating Conditions Smart Card Interface Requirements Digital Signals Characteristics DC Characteristics Voltage / Temperature Fault Detection Circuits 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009R. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings Parameter Supply voltage VDD Supply voltage VPC Input voltage for digital inputs Storage temperature Pin voltage (except card interface) Pin voltage (card interface) ESD tolerance – Card interface pins ESD tolerance – Other pins Rating -0.5 to 4.0 VDC -0.5 to 6.5 VDC -0.3 to (VDD +0.5) VDC -60 °C to +150 °C -0.3 to (VDD + 0.5) VDC -0.3 to (VCC + 0.5) VDC +/- 6 kV +/- 2 kV Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. Smart card pins are protected against shorts between any combination of smart card pins. 2.2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Supply voltage VDD Supply voltage VPC for Class A-B-C Reader Ambient operating temperature 2.7 to 3.6 VDC 4.75 to 6.0 VDC -40 °C to +85 °C Rating 8 Rev. 1.3 DS_8009R_056 73S8009R Data Sheet 2.3 Smart Card Interface Requirements Table 4: DC Smart Card Interface Requirements Table 4 lists the 73S8009R Smart Card interface requirements. Symbol Parameter Condition Min Nom Max Unit Card Power Supply (VCC) Regulator General Conditions: -40 °C < T < 85 °C, 4.75 V < VPC < 6.0 V, 2.7 V < VDD < 6.0 V VCC Card supply voltage including ripple and noise Inactive mode Inactive mode ICC = 1 mA Active mode; ICC < 65 mA; 5 V Active mode; ICC < 65mA; 5 V, NDS condition Active mode; ICC < 65 mA; 3 V Active mode; ICC < 40 mA; 1.8 V Active mode; single pulse of 100 mA for 2 µs; 5 V, fixed load = 25 mA Active mode; single pulse of 100 mA for 2 µs; 3 V, fixed load = 25 mA Active mode; current pulses of 40 nAs with peak |ICC | < 200 mA, t < 400 ns; 5 V Active mode; current pulses of 40 nAs with peak |ICC | < 200 mA, t 4.6 V or 2.7 V as selected Class A, B (5 V and 3 V) Class C (1.8 V) CF = 1.0 µF CF = 1.0 µF on VCC 5 V operation 3 V operation 1.8 V operation -0.1 -0.1 4.65 4.75 2.85 1.68 4.6 – – – – – – – 0.1 0.4 5.25 5.25 3.15 1.92 5.25 V 2.7 – 3.15 4.6 – 5.25 2.7 – 3.15 1.62 – 1.92 ICCrip ICCmax VCC Ripple Card supply output current – – – 100 60 0.06 0.075 4.6 2.75 1.65 – – – – – 0.15 0.15 – – – 1.0 3.3 350 40 90 180 130 0.25 0.6 – – – mV mA ICCF VSR VSF VRDY ICC fault current Vcc slew rate, rise rate on activate Vcc slew rate, fall rate on de-activate VCC ready voltage, VCC rising (RDY = 1) mA V/μs V/μs V CF ISO 7816-13 application External filter capacitor (VCC to GND) EMV 4.1 application CF should be ceramic with low ESR (< 100 mΩ) µF Rev. 1.3 9 73S8009R Data Sheet Symbol Parameter Condition Min Nom DS_8009R_056 Max Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC. VOH VOH VOL VOL VIH VIH VIL VIL VINACT ILEAK IIL IIL ISHORTL ISHORTH t R, t F Output level, high (I/O, AUX1, AUX2) Output level, high (I/OUC, AUX1UC, AUX2UC) Output level, low (I/O, AUX1, AUX2) IOH = 0 µA IOH = -40 µA IOH = 0 µA IOH = -40 µA IOL = 1 mA 0.9 * VCC 0.75 * VCC 0.9 * VDD 0.75 * VDD – – – – – – IOL = 0 IOL = 1 mA VIH = VCC VIL = 0 0.6 * VCC 1.8 -0.15 -0.3 – – – – – – – – – – – – – – – – – – – – – – – – – – VCC+0.1 VCC+0.1 VDD+0.1 VDD+0.1 0.15 * VCC 0.3 VCC+0.30 VDD+0.30 0.2 * VCC 0.8 0.1 0.3 10 0.65 0.7 15 15 100 µA mA mA mA mA ns V V V V V V V V V Output level, low (I/OUC, IOL = 1 mA AUX1UC, AUX2UC) Input level, high (I/O, AUX1, AUX2) Input level, high (I/OUC, AUX1UC, AUX2UC) Input level, low (I/O, AUX1, AUX2) Input level, low (I/OUC, AUX1UC, AUX2UC) Output voltage when outside of session Input leakage Input current, low (I/O, AUX1, AUX2) Input current, low (I/OUC, VIL = 0 AUX1UC, AUX2UC) Short circuit output current Short circuit output current For output low, shorted to VCC through 33 Ω For output high, shorted to ground through 33 Ω Output rise time, fall time For I/O, AUX1, AUX2, CL = 80 pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50 pF, 10% to 90%. Input rise, fall times Internal pull-up resistor Maximum data rate Delay, I/O to I/OUC, AUX1 Edge from master to slave to AUX1UC, AUX2 to measured at 50% point AUX2UC, I/OUC to I/O, AUX1UC to AUX1, AUX2UC to AUX2 (respectively falling edge to falling edge and rising edge to rising edge) Input capacitance Output stable for >200 ns tIR, tIF RPU FDMAX TFDIO TRDIO – 8 – 60 – – 11 – 100 25 1 14 1 200 90 µs kΩ MHz ns CIN 10 – – 10 pF Rev. 1.3 DS_8009R_056 Symbol VOH VOL VINACT IRST_LIM ICLK_LIM Parameter Output level, high Output level, low Output voltage when outside of session Output current limit, RST Output current limit, CLK VCC = 3 V VCC = 5 V CL = 35 pF for CLK, 10% to 90% CL = 200 pF for RST, 10% to 90% Condition IOH = -200 µA IOL = 200 µA IOL = 0 IOL = 1 mA – – Min 0.9 * VCC 0 – – – – 0.3 0.5 – – 45 73S8009R Data Sheet Nom – – – – – – – – – – – Max VCC 0.15*VCC 0.1 0.3 30 70 – – 8 100 55 % Unit V V V V mA mA V/ns V/ns ns Reset and Clock for card interface, RST, CLK CLKSR3V CLK slew rate CLKSR5V CLK slew rate t R, t F Output rise time, fall time δ Duty cycle for CLK CL =35 pF, FCLK ≤ 20 MHz 2.4 Digital Signals Characteristics Table 5: Digital Signals Characteristics Table 5 lists the 73S8009R digital signals characteristics. Symbol VIL VIH VOL VOH ROUT |I IL1 | Parameter Input low voltage Input high voltage Output low voltage Output high voltage Pull-up resistor; OFF, RDY Input leakage current Condition – – IOL = 2 mA IOH = -1 mA – GND < VIN < VDD Min -0.3 1.8 – VDD-0.45 – Nom – – – – 20 – Max 0.8 VDD+0.3 0.45 – – 5 Unit V V V V kΩ μA Digital I/O except for OSC I/O 2.5 DC Characteristics Table 6 lists the DC characteristics. Table 6: DC Characteristics Symbol IDD IPC Parameter Supply current Supply current Condition Normal operation Power down VCC on, ICC = 0 , I/O, AUX1, AUX2 = high, CLK not toggling Power down IPCOFF VPC supply current when VCC = 0 CMDVCC is high Min – – – – – Nom 700 – 450 – 345 Max 1500 5 650 5 550 µA µA Unit µA Rev. 1.3 11 73S8009R Data Sheet DS_8009R_056 2.6 Voltage / Temperature Fault Detection Circuits Table 7 lists the voltage / temperature fault detection circuits. Table 7: Voltage / Temperature Fault Detection Circuits Symbol VPCF VCCF Parameter VPC fault (VPC Voltage Supervisor threshold) RDY = 0 (VCC fault, VCC Voltage Supervisor threshold) Die over temperature fault Card over current fault Condition VPC < VCC, a transient event VCC = 5 V VCC = 3 V VCC = 1.8 V TF ICCF – – Min – – – – 115 110 Typical VCC > VPC + 0.3 – – – – – Max – 4.6 2.7 1.65 145 150 °C mA Unit V V 12 Rev. 1.3 DS_8009R_056 73S8009R Data Sheet 3 Applications Information This section provides general usage information for the design and implementation of the 73S8009R. 3.1 Example 73S8009R Schematics Figure 4 shows a typical application schematic for the implementation of the 73S8009R. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. CS_from_uC OFF_interrupt_to_uC I/OUC_to/from_uC AUX1UC_to/from_uC AUX2UC_to/from_uC CMDVCC5_from_uC CMDVCC3_from_uC RSTIN_from_uC CLKIN_from_uC RDY_status_to_uC PWRDN_from_uC See NOTE 3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CS TEST1 N/C OFF I/OUC AUX1UC AUX2UC CMDVCC5 CMDVCC3 RSTIN CLKIN RDY PWRDN TEST2 VDD GND PRES I/O AUX1 AUX2 VCC RST GND CLK N/C N/C PRES VPC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 See NOTE 1 C6 100nF See NOTE 4 VDD VPC See NOTE 2 C5 10uF C4 100nF 73S80009R SO28 VDD R 2 20K Card detection switch is normally closed ISO7816=1µF, EMV=3.3µF C1 8 7 6 5 4 3 2 1 NOTES: 1) VDD = 2.7V to 3.6V DC. 2) VPC = 4.75V to 6.0V DC (Class A-B-C Reader: 1.8V, 3V and 5V cards) 3) Must be tied to GND if not used 4) Internal pull-up allows it to be left open if unused. 10 9 Low ESR (