73S8010C

73S8010C Smart Card Interface Simplifying System Integration™ DATA SHEET April 2009 DESCRIPTION The Teridian 73S8010C is a single smart card interface IC. It provides full electrical compliance with ISO-7816-3 and EMV 4.0 specifications. Interfacing with the host is done through the two-wire I2C bus. Data exchange with the card is managed from the system controller using the I/O line (and eventually the auxiliary I/O lines). An on-chip oscillator using an external crystal, or connection to a clock signal coming from the system controller can generate the card clock signal. The 73S8010C IC incorporates an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Level shifters drive the card signals with the selected card voltage (3 V or 5 V), coming from an internal DC-DC converter. With its high-efficiency DC-DC converter, the Teridian 73S8010C is a cost-effective solution for any smart card reader application to be powered from a single 2.7 V to 3.6 V power supply. Hardware support for auxiliary I/O lines, C4 / C8 contacts, is provided. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a VDD (digital power supply), a VCC (card power supply), a card over-current, or an over-heating fault. ADVANTAGES • • Single smart card interface The inductor-based DC-DC converter provides higher current and efficiency than the usual charge-pump capacitor-based converters  Ideal for battery-powered applications  Suitable for high current cards and SAMs: (100 mA max) Power down mode: 2 µA typical Small Format (5x5mm) 32-QFN package option FEATURES • Card Interface:  Complies with ISO-7816-3 and EMV 4.0  A DC-DC Converter provides 3V / 5V to the card from an external power supply input  High-efficiency converter: > 80% @ VDD= 3.3 V, VCC = 5 V and ICC = 65 mA  Up to 100 mA supplied to the card  ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry  Protection include 2 voltage supervisors that detect voltage drops on card VCC and VDD power supplies  The VDD voltage supervisor threshold value can be externally adjusted  True over-current detection (150 mA max.)  1 card detection input  Auxiliary I/O lines, for C4 / C8 contact signals Host Interface:  Fast mode, 400 kbps I2C slave bus  8 possible devices in parallel  One control register and one status register  Interrupt output to the host for fault detection  Crystal oscillator or host clock, up to 27 MHz Power Supply:  VDD: 2.7 V to 3.6 V 6 kV ESD Protection on the card interface Package: SO28 or 32QFN • • • • APPLICATIONS • • • Set-Top-Boxes, DVD / HDD Recorders: Conditional Access and Pay-per-View slots Point of Sales and Transaction Terminals EMV slots in cell phones and PDAs • • Rev. 1.5 © 2009 Teridian Semiconductor Corporation 1 73S8010C Data Sheet FUNCTIONAL DIAGRAM VDD [20] 21 DS_8010C_024 VDDF_ADJ [17] 18 VDD [3] 6 [4, 6, 8, 16, 25, 32] 7, 9 NC [2] 5 [21] 22 GND [5] 8 VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE VDD FAULT VCC FAULT LIN PWRDN [18] 19 DC-DC CONVERTER & VOLTAGE SUPERVISOR [1] 4 GND [12] 14 GND [15] 17 SCL SDA [19] 20 Int_Clk R-C OSC. VCC SAD0 SAD1 [29] 1 [30] 2 [31] 3 SAD2 [22] 23 I2C DIGITAL & FAULT LOGIC ICC RESET BUFFER [14] 16 RST INT ISO-7816 SEQUENCER [23] 24 ICC CLOCK BUFFER [13] 15 CLK [7] 10 PRES XTAL OSC XTALIN [24] 25 XTALOUT CLOCK GENERATION OVER TEMP TEMP FAULT [26] 26 [9] 11 IOUC [27] 27 I/O AUX1UC [28] 28 ICC I/O BUFFERS [11] 13 AUX1 [10] 12 AUX2UC AUX2 Figure 1: 73S8010C Block Diagram Pin number reference to SO28 Package [Pin number] reference to 32QFN Package 2 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet Table of Contents 1 Pin Description .................................................................................................................................... 5 1.1 Card Interface ............................................................................................................................... 5 1.2 Miscellaneous Inputs and Outputs................................................................................................ 5 1.3 Power Supply and Ground............................................................................................................ 5 1.4 Microcontroller Interface ............................................................................................................... 6 Host Interface (I2C Bus) ...................................................................................................................... 7 2.1 Host Interface Control ................................................................................................................... 7 2.2 Host Interface Status .................................................................................................................... 8 2.3 I2C-bus Timing .............................................................................................................................. 9 Oscillator............................................................................................................................................ 10 DC-DC Converter – Card Power Supply ......................................................................................... 10 Voltage Supervision ......................................................................................................................... 11 Power Down....................................................................................................................................... 11 Over-temperature Monitor................................................................................................................ 12 Activation Sequence ......................................................................................................................... 12 Deactivation Sequence..................................................................................................................... 13 Interrupt ............................................................................................................................................. 13 Warm Reset ....................................................................................................................................... 14 I/O Timing........................................................................................................................................... 14 Typical Application Schematic ........................................................................................................ 15 Electrical Specification..................................................................................................................... 16 14.1 Absolute Maximum Ratings ........................................................................................................ 16 14.2 Recommended Operating Conditions......................................................................................... 16 14.3 DC Characteristics: Card Interface ............................................................................................. 17 14.4 DC Characteristics: Digital Signals ............................................................................................. 20 14.5 DC Characteristics: Supply ......................................................................................................... 20 14.6 DC Characteristics: I2C Interface ................................................................................................ 21 14.7 Voltage / Temperature Fault Detection Circuits.......................................................................... 21 Mechanical Drawings ....................................................................................................................... 22 15.1 32-pin QFN ................................................................................................................................. 22 15.2 28-pin SO .................................................................................................................................... 23 Package Pin Designation ................................................................................................................. 24 16.1 32-pin QFN ................................................................................................................................. 24 16.2 28-pin SO .................................................................................................................................... 25 Ordering Information ........................................................................................................................ 26 Related Documentation .................................................................................................................... 26 Contact Information .......................................................................................................................... 26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Revision History ........................................................................................................................................ 27 Rev. 1.5 3 73S8010C Data Sheet DS_8010C_024 Figures Figure 1: 73S8010C Block Diagram ............................................................................................................. 2 Figure 2: I2C Bus Write Protocol ................................................................................................................... 8 Figure 3: I2C Bus Read Protocol ................................................................................................................... 9 Figure 4: I2C Bus Timing Diagram ................................................................................................................ 9 Figure 5: Power Down Mode Operation...................................................................................................... 12 Figure 6: Activation Sequence .................................................................................................................... 12 Figure 7: Deactivation Sequence ................................................................................................................ 13 Figure 8: FAULT Functions, INT operation ................................................................................................. 13 Figure 9: Warm Reset operation ................................................................................................................. 14 Figure 10: I/O Timing .................................................................................................................................. 14 Figure 11: 73S8010C – Typical Application Schematic .............................................................................. 15 Figure 12: DC – DC Converter Efficiency (VCC = 5 V) ................................................................................ 18 Figure 13: DC – DC Converter Efficiency (VCC = 3 V) ................................................................................ 18 Figure 14: 32-pin QFN Package Drawing ................................................................................................... 22 Figure 15: 28-pin SO Package Drawing ..................................................................................................... 23 Tables Table 1: Device Address Selections ............................................................................................................. 7 Table 2: Host Control Register ...................................................................................................................... 7 Table 3: Host Status Register ....................................................................................................................... 8 Table 4: Choice of Vcc Capacitor ............................................................................................................... 10 4 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 1 Pin Description 1.1 Card Interface Pin (SO) 11 13 12 16 15 PIN (QFN) 9 11 10 14 13 Description Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. Card reset: provides reset (RST) signal to card. Card clock: provides clock (CLK) signal to card. The rate of this clock is determined by the crystal oscillator frequency and CLKSEL bits in the control register. Card Presence switch: active high indicates card is present. Includes a pull-down resistor. Card power supply: logically controlled by sequencer, output of DC-DC converter. Requires an external filter capacitor to the card GND. Card ground. Name I/O AUX1 AUX2 RST CLK PRES VCC GND 10 17 14 7 15 12 1.2 Miscellaneous Inputs and Outputs PIN (SO) 24 25 18 PIN (QFN) 23 24 17 Description Crystal oscillator input: can either be connected to a crystal or driven as a source for the card clock. Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as an external clock input. VDD threshold adjustment input: this pin can be used to overwrite a higher VDDF value (that controls deactivation of the card). Must be left open if unused. Non-connected pin. Name XTALIN XTALOUT VDDF_ADJ NC 7, 9 4, 6, 8, 16, 25, 32 1.3 Power Supply and Ground PIN (SO) 6, 21 4 14 22 5 Pin (QFN) 3, 20 1 12 21 2 Description System controller interface supply voltage: supply voltage for internal circuitry and DC-DC converter power supply source. DC-DC converter ground. Smart Card I/O ground. Digital ground. External inductor: Connect external inductor from pin 5 to VDD. Keep the inductor close to pin 5. Name VDD GND GND GND LIN Rev. 1.5 5 73S8010C Data Sheet DS_8010C_024 1.4 Microcontroller Interface PIN (SO) 23 8 PIN Description (QFN) 22 5 Interrupt output (negative assertion): Interrupt output signal to the processor. A 20 kΩ pull up to VDD is provided internally. Power Down control input: Active High. When Power Down (PD) mode is activated, all internal analog functions are disabled to place the 73S8010C in its lowest power consumption mode. Must be tied to ground when the power down function is not used. Serial device address bits: Digital inputs for address selection that allow the connection of up to 8 devices in parallel. Address selections as follows: SAD2 0 0 0 0 1 1 1 1 SAD1 0 0 1 1 0 0 1 1 SAD0 0 1 0 1 0 1 0 1 I2C Address (7 bits) 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E Name INT PWRDN SAD0 SAD1 SAD2 1 2 3 29 30 31 Pins SAD0 and SAD1 are internally pulled-down and SAD2 is internally pulled-up. The default address when left unconnected is 48h. SCL SDA I/OUC AUX1UC AUX2UC 19 20 26 27 28 18 19 26 27 28 I2C clock signal input. I2C bi-directional serial data signal. System controller data I/O to/from the card. Includes internal pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes internal pullup resistor to VDD. System controller auxiliary data I/O to/from the card. Includes internal pullup resistor to VDD. 6 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 2 Host Interface (I2C Bus) A fast-mode 400 kHz I2C bus slave interface is used for controlling the device and reading the status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This allows up to 8 devices to be connected in parallel. Table 1: Device Address Selections SAD2 0 0 0 0 1 1 1 1 SAD1 0 0 1 1 0 0 1 1 SAD0 0 1 0 1 0 1 0 1 I2C Address (7 bits) 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E Bit 0 of the I2C address is the R/W bit. Refer to Figure 2 and Figure 3 for usage. 2.1 Host Interface Control Table 2: Host Control Register Table 2 describes the Host Interface Control Register bits (power-on Reset = 0x00). Name Start/Stop Warm reset 5 V and 3 V Clock Stop Clock Stop Level Clksel1 Bit 0 1 2 3 4 5 Description When set, initiates an activation and a cold reset procedure; when reset, initiates a deactivation sequence. When set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute. When set, VCC = 3 V; when reset, VCC = 5 V. When set, card clock is stopped. Bit 4 determines the card clock stop level. When set, card clock stops high; when reset card clock stops low. Bits 5 and 6 determine the clock rate to the card according to the following table. CLKDIV1 0 0 1 1 CLKDIV2 0 1 1 0 Clock Rate XTALIN/8 XTALIN/4 XTALIN/2 XTALIN Clksel2 6 I/O enable 7 When set, data is transferred between I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC) are high impedance. I2C-bus Write to the Control Register The I2C-bus Write command to the control register follows the format shown in Figure 2. After the START condition, the master sends a slave address. This address is seven bits long followed by an eighth bit, which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts sending the 8 bits of data to the control register during the DATA bits time. After the DATA bits, the ‘zero’ Rev. 1.5 7 73S8010C Data Sheet DS_8010C_024 ACK bit is sent to the master by the device. The master should send the STOP condition after receiving the ACK bit. SDA MSB SCL 1-7 LSB 8 9 MSB 1-8 LSB 9 START condition ADDRESS bits R/W bit ACK bit DATA bits ACK bit STOP condition Figure 2: I2C Bus Write Protocol 2.2 Host Interface Status Table 3: Host Status Register Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04). Name PRES PRESL I/O SUPL PROT MUTE EARLY ACTIVE Bit 0 1 2 3 4 5 6 7 Description Set when the card is present; reset when the card is not present. Set when the PRES pin changes state (rising/falling edge); reset when the status register is read. Generates an interrupt when set Set when I/O is high; reset when I/O is low. Set when a voltage fault is detected; reset when the status register is read. Generates an interrupt when set. Set when an over-current or over-heating fault has occurred during a card session; reset when the status register is read. Generates an interrupt when set. Set during ATR when the card has not answered during the ISO 7816-3 time window (40000 card clock cycles); reset when the next session begins or this register is read. Set during ATR when the card has answered before 400 card clock cycles; reset when the next session begins or this register is read. Set when the card is active (VCC is on); reset when the card is inactive. I2C-bus Read from t he Status Register: The I2C-bus Read Command from the Status Register follows the format shown in Figure 3. After the START condition, the master sends a slave address. This address is seven bits long followed by an eighth bit, which is the opcode bit (R/W). A ‘one’ indicates the master will read data from the status register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The device now starts sending the 8-bit status register data to the control register during the DATA bits time. After the DATA bits, the ‘one’ ACK bit is sent to the device by the master. The master should send the STOP condition after receiving the ACK bit. 8 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet SDA MSB SCL 1-7 LSB 8 9 MSB 1-8 LSB 9 START condition ADDRESS bits R/W bit ACK bit DATA bits ACK bit STOP condition Figure 3: I2C Bus Read Protocol 2.3 Fsclk Tlow Thi I2C-bus Timing Parameter Clock frequency Clock low Clock high Hold time START condition Data set up time Data hold time Set up time STOP condition Bus free time between a STOP and START condition 1.3 0.6 0.6 100 5 0.6 1.3 900 Conditions Min. Typ. Max. 400 UNIT kHz µs µs µs ns ns µs µs Symbol Thdsta Tsudat Thddat Tsusto Tbuf SDA Tbuf SCL Thi Tlow Thdsta Tsudat Thddat Tsusto Figure 4: I2C Bus Timing Diagram Rev. 1.5 9 73S8010C Data Sheet DS_8010C_024 3 Oscillator The Teridian 73S8010C device has an on-chip oscillator that can generate the smart card clock using an external crystal, connected between the XTALIN and XTALOUT pins, to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. 4 DC-DC Converter – Card Power Supply An internal DC-DC converter provides the card power supply. This converter is able to provide either a 3 V or 5 V card voltage from the power supply applied on the VDD pin. The digital ISO-7816-3 sequencer controls the converter. Bit 2 of the Control register selects the card voltage. The circuit is an inductive step-up converter/regulator. The external components required are 2 filter capacitors on the power-supply input VDD (100 nF + 10 µF, next to the LIN pin), an inductor, and an output filter capacitor on the card power supply VCC. The circuit performs regulation by activating the step-up operation when VCC is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the input supply VDD is less than the set point for VCC. When VDD is greater than the set point for VCC (VDD = 3.6 V, VCC = 3 V) the circuit operates as a linear regulator. Depending on the inductor values, the voltage converter can provide current on VCC as high as 100 mA. The circuit provides over-current protection and limits ICC to 150 mA. When an over-current condition is sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output INT. Choice of the Inductor The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between pin LIN (pin 5 in the SO package, pin 2 in the QFN package) and the VDD voltage. The value of the inductor can be optimized to meet a particular configuration (ICC_MAX). The inductor should be located on the PCB as close as possible to the LIN pin of the IC. Choice of the VCC Capacitor Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that the interface must be able to provide to the card vary. Table 4 shows the recommended capacitors for each VCC power supply configuration and applicable specification. Table 4: Choice of Vcc Capacitor Specification Requirement Specification EMV 4.0 ISO-7816-3 Min VCC Voltage Allowed During Transient Current 4.6V 4.5V Max Transient Current Charge 30nA.s 20nA.s Application Capacitor Type X5R/X7R w/ ESR < 100 mΩ Capacitor Value 3.3 µF 1 µF 10 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 5 Voltage Supervision Two voltage supervisors constantly check the level of the VDD and VCC voltages. A card deactivation sequence is forced when a fault occurs for any of these voltage supervisors. The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller. The VDD voltage supervisor is also used to initialize the ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or when a fault occurs. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3 V nominal. However, it may be desirable in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the QFN package) is used to connect an external resistor REXT1 to ground to raise the VDD fault voltage to another value, VDDF (refer to Figure 11). The resistor value is defined as follows: REXT = 180 kΩ / (VDDF - 2.33) An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of R3 from the pin to supply and R4 from the pin to ground (see Figure 11). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R4/(R4+R5). Kx is calculated as: Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage. To determine the values of R4 and R5, use the following formulas. R5 = 72000 / Kx R4 = R5*(Kx / (1 – Kx)) Taking the example above, where a VDD fault threshold voltage of 2.7 V is desired, solving for Kx gives:  Kx = (2.649 / 2.7) - 0.6042 = 0.377. Solving for R5 gives: Solving for R4 gives:  R5 = 72000 / 0.377 = 191 kΩ.  R4 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ. Using standard 1% resistor values gives R5 = 191 kΩ and R4 = 115 kΩ. These values give an equivalent resistance of Kx = 0.376, a 0.3% error. If the 2.3 V default threshold is used, the VDDF_ADJ pin must be left unconnected. 6 Power Down A power down function is provided via the PWRDN pin (active high). When activated, the Power Down (PD) mode disables all the internal analog functions, including the card analog interface, the oscillators and the DC-DC converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only allowed in the deactivated condition (out of a card session, when the Start/Stop bit is set to 0 from the I2C host controller). The host controller invokes the power down state when it is desirable to save power. The signal PRES remains functional in PD mode such that a card insertion sets INT high. The micro-controller must then set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to setting the Start/Stop bit to 1). Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators + reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms time period. If a card is present, INT can be used as an indication that the circuit has completed its recovery from power down state. INT will go high at the end of the stabilization period. Should the Start/Stop be set to 1 during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be taken into account and the card interface will remain inactive. Since Start/Stop is taken into account on its edges, it should be toggled low and high again after the 10 ms to activate a card. Figure 5 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if the power down function is not used. Rev. 1.5 11 73S8010C Data Sheet DS_8010C_024 PRES INT PWRDN Internal RC OSC ~10ms OFF follows PRES regardless of PWRDN PWRDN during a card session has no effect PWRDN has effect when the cardi s deactivated Start/Stop bit After setting PWRDN = 0, the controller must wait at least 10ms before setting Start/Stop = 1 EMV / ISO deactivation time ~= 100 uS Figure 5: Power Down Mode Operation 7 Over-temperature Monitor A built-in detector monitors die temperature. When an over-temperature condition occurs (most likely resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and generates an interrupt). 8 Activation Sequence After Power on Reset, the INT signal is low until VDD is stable. When VDD has been stable for approximately 10 ms and the INT signal is high, the system controller may read the status register to see if the card is present. If all the status bits are satisfactory, the system controller can initiate the activation sequence by writing a ‘1’ to the Start/Stop bit (bit 0 of the Control register). The following steps and Figure 6 show the activation sequence and the timing of the card control signals when the system controller initiates the Start/Stop bit (bit 0) of the control register: 1. Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the session is aborted. 2. Turn I/O to reception mode at the end of t1. 3. CLK is applied to the card at the end of t2. 4. RST (to the card) is set high at the end of t3. Start/Stop Start/Stop VCC IO CLK RST t1 t2 t3 t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator), I/O in reception mode reception t2 ≥ 0.5 μs, CLK starts t3 ≥ 42000 card clock cycles, RST set high Figure 6: Activation Sequence 12 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 9 Deactivation Sequence Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VCC fault, and card extraction during the session. The following steps and Figure 7 show the deactivation sequence and the timing of the card control signals when the system controller clears the Start/Stop bit: 1. 2. 3. 4. RST goes low at the end of t1. CLK goes low at the end of t2. I/O goes low at the end of t3. Out of reception mode. Shut down VCC at the end of time t4. Start/Stop RST CLK IO VCC t1 t2 t3 t4 t1 ≥ 0.5 μs t2 ≥ 7.5 μs t3 ≥ 0.5 μs t4 ≥ 0.5 μs Figure 7: Deactivation Sequence 10 Interrupt The interrupt is an active low interrupt. It is set low if either a VCC fault or a VDD fault is detected. It is also set low if one of the following status bit conditions is detected: • • • • Early ATR Mute ATR Card insert or card extract Protection status from Over-current or Over-heating If the interrupt is set low by the detection of these status bits, then the interrupt is set high when these status bits are read. (READ STATUS DONE) INT ANY FAULT STATUS BITS READ STATUS DONE Figure 8: FAULT Functions, INT operation Rev. 1.5 13 73S8010C Data Sheet DS_8010C_024 A power-on-reset (POR) event will reset all of the control and status registers to their default states. A VDD fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that creates interval “t1,” will not clear the interrupt until VDD is valid for at least the t1 time. The VDD fault can be considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of the VDD fault, POR will be asserted. 11 Warm Reset The 73S8010C automatically asserts a warm reset to the card when instructed through bit 1 of the I2C Control register (Warm Reset bit). The warm reset length is automatically defined as 42,000 card clock cycles. The bit Warm Reset is automatically reset when the card starts answering or when the card is declared mute. IO Warm Reset (bit 1) RST t1 t2 t3 t1 > 1.5 µs, Warm Reset Starts t2 = 42000 card clock cycles, End of Warm Reset t3 = Resets Warm Reset bit 1 when detected ATR or Mute Figure 9: Warm Reset operation 12 I/O Timing The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are high when the activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable bit (bit 7 of the Control register) is set, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then both I/O lines return to their neutral state. The delay between the I/O signals is shown in Figure 10. IO IOUC tIO_HL tIO_LH tIOUC_HL tIOUC_LH Delay from I/O to I/OUC: Delay from I/OUC to I/O: tIO_HL = 100 ns tI/OUC_HL = 100 ns tIO_LH = 25 ns tI/OUC_LH = 25 ns Figure 10: I/O Timing 14 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 13 Typical Application Schematic See NOTE 5 AUX2UC_to/f rom_uC AUX1UC_to.f rom_uC IOUC_to/f rom_uC VDD SAD0 SAD1 SAD2 Note 2 R5 Rext2 - OR C4 100nF C5 10uF L1 See note 7 10uH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAD0 SAD1 SAD2 GND GND VPC NC NC NC PRES I/O AUX2 AUX1 GND AUX2UC AUX1UC I/OUC XTALOUT XTALIN INT_ GND VDD SDA SCL VDD_ADJ VCC RST CLK 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C2 22pF C3 22pF See NOTE 3 External_clock_f rom uC Y1 See NOTE 1 C6 100nF R4 Rext1 R3 2K CRY STAL PWRDN_f rom_uC See NOTE 5 See NOTE 4 73S8010C SO28 See note 6 R2 2K VDD INT_interrupt_to_uC R1 SDA_f rom_uC SCL_f rom_uC ISO7816=1uF, EMV=3.3uF Low ESR ( 4.6 or 2.7 V as ICCmax the card selected, L=10 µH ICCF ICC fault current Short circuit, VCC to ground VCC slew rate - Rise rate on VSR CF on VCC = 1 µF activate VCC slew rate - Fall rate on VSF CF on VCC = 1 µF deactivate External filter capacitor CF (VCC to GND) L Inductor (LIN to VDD) VCC = 5 V, ICC = 65 mA, Limax Imax in inductor VDD = 2.7 V VCC = 5 V, ICC = 65 mA, Efficiency η VDD = 3.3 V -0.1 -0.1 4.75 2.8 0.1 0.4 5.25 3.2 V V V V 4.6 5.25 V 2.76 3.2 V 4.6 5.25 V 2.76 3.2 V 100 100 0.05 0.1 0.47 125 0.15 0.3 1 10 400 87 180 0.25 0.5 3.3 mA mA V/µs V/µs µF µH mA % Rev. 1.5 17 73S8010C Data Sheet DS_8010C_024 1011B01 Converter efficiency (VCC 5V) Converter Efficiency (VCC 5 V) 100 95 90 85 Efficiency [%] 80 75 70 65 60 55 50 0 20 40 Icc [mA] 60 80 100 2.7V 3.0V 3.3V 3.6V Figure 12: DC – DC Converter Efficiency (VCC = 5 V) Output current on Vcc at 5 V. Input voltage on VDD at 2.7, 3.0, 3.3 and 3.6 volts. 1011B01 Converter efficiency (VCC 3V) 100 95 90 85 Efficiency [%] 80 75 70 65 60 55 50 0 20 40 Icc [mA] 60 80 100 2.7V 3.0V 3.3V (Linear) 3.6V (Linear) Figure 13: DC – DC Converter Efficiency (VCC = 3 V) Output current on VCC at 3 V. Input voltage on VDD at 2.7, 3.0, 3.3 and 3.6 volts. 18 Rev. 1.5 DS_8010C_024 Symbol Parameter Condition Min. 73S8010C Data Sheet Typ. Max. Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. IIL requirements only pertain to I//OUC, AUX1UC, and AUX2UC. VOH VOH VOL VIH VIH VIL VINACT ILEAK IIL ISHORTL ISHORTH Output level, high (I/O, AUX1, AUX2) Output level, high (I/OUC, AUX1UC, AUX2UC) Output level, low Input level, high (I/O, AUX1, AUX2) Input level, high (I/OUC, AUX1UC, AUX2UC) Input level, low Output voltage when outside of session Input leakage Input current, low Short circuit output current Short circuit output current IOL = 0 IOL = 1 mA VIH = VCC VIL = 0, CS = 1 VIL = 0, CS = 0 For output low, shorted to VCC through 33 Ω For output high, shorted to ground through 33 Ω For I/O, AUX1, AUX2, CL = 80 pF, 10% to 90% For I/OUC, AUX1UC, AUX2UC, CL=50 pF, 10% to 90% Output stable for >200 ns 8 11 IOH = 0 IOH = -40 µA IOH = 0 IOH = -40 µA IOL=1 mA 1.8 1.8 -0.3 0.9 VCC 0.75 VCC 0.9 VDD 0.75 VDD VCC+ 0.1 VCC + 0.1 VDD+ 0.1 VDD + 0.1 0.3 VCC + 0.30 VDD + 0.30 0.8 0.1 0.3 10 0.65 5 15 15 V V V V V V V V V V µA mA μA mA mA tR, tF Output rise time, fall times 100 ns tIR, tIF RPU FDMAX TFDIO CIN Input rise, fall times Internal pull-up resistor Maximum data rate Delay, I/O to I/OUC, I/OUC to I/O Input capacitance 20 1 14 1 µs kΩ MHz ns 10 pF Rev. 1.5 19 73S8010C Data Sheet DS_8010C_024 Symbol VOH VOL VINACT IRST_LIM ICLK_LIM tR, tF Parameter Output level, high Output level, low Output voltage when outside of a session Output current limit, RST Output current limit, CLK Output rise time, fall time Duty cycle for CLK, except for f=fXTAL Condition IOH = -200 µA IOL = 200 µA IOL = 0 IOL = 1 mA Min. 0.9 VCC 0 Typ. Max. VCC 0.3 0.1 0.3 30 70 8 100 Unit V V V V mA mA ns ns % Reset and Clock for card interface, RST, CLK δ CL = 35 pF for CLK, 10% to 90% CL = 200 pF for RST, 10% to 90% CL =35 pF, FCLK ≤ 20 MHz 45 55 14.4 DC Characteristics: Digital Signals Symbol VIL VIH VOL VOH ROUT |IIL1| VILXTAL VIHXTAL IILXTAL fMAX Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Pull-up resistor, INT Input Leakage Current Input Low Voltage - XTALIN Input High Voltage - XTALIN Input Current - XTALIN Max freq. Osc or external clock External input duty cycle limit tR/F < 10% fIN, 45% < δCLK < 55% 48 GND < VIN < VDD GND < VIN < VDD -5 -0.3 0.7 VDD -30 IOL = 2 mA IOH = -1 mA VDD - 0.45 20 5 0.3 VDD VDD+0.3 30 27 52 Condition Min. -0.3 1.8 Typ. Max. 0.8 VDD + 0.3 0.45 Unit V V V V kΩ μA V V μA MHz % Digital I/O except for OSC I/O Oscillator (XTALIN) I/O Parameters δin 14.5 DC Characteristics: Supply Symbol Parameter Condition Linear mode, ICC=0 I/O, AUX1, AUX2=high Step up mode, ICC=0 I/O, AUX1, AUX2=high PWRDN=1, Start/stop bit = 0 All digital inputs driven with a true logical 0 or 1 Min. Typ. 4.9 4.7 0.11 2.5 Max. Unit mA mA µA IDD Supply Current on VDD IDD_PD Supply Current on VDD in Power Down mode 20 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 14.6 DC Characteristics: I2C Interface Symbol SDA, SCL VIL VIH VOL CIN IIN TF TSP Input Low Voltage Input High Voltage Output Low Voltage Pin capacitance Output High Voltage Output fall time Pulse width of spikes that are suppressed IOH = -1 mA CL = 0 to 400 pF Transition from valid logic level to opposite level VDD - 0.45 20 + 0.1*CL Parameter Condition Min. -0.3 0.7*VDD Typ. Max. 0.3* VDD VDD + 0.3 0.40 10 250 50 Unit V V V pF V ns ns IOL = 3 mA 14.7 Voltage / Temperature Fault Detection Circuits Symbol VDDF VCCF TF Parameter VDD fault – VDD Voltage supervisor threshold VCC fault – VCC Voltage supervisor threshold Die over temperature fault Condition No external resistor on VDDF_ADJ pin VCC = 5 V VCC= 3 V Min. 2.15 4.20 2.5 115 Typ. Max. 2.4 4.6 2.7 145 Unit V V V °C Rev. 1.5 21 73S8010C Data Sheet DS_8010C_024 15 Mechanical Drawings 15.1 32-pin QFN 0.85 NOM./ 0.9MAX. 5 2.5 0.00 / 0.005 0.20 REF. 1 2 3 2.5 5 SEATING PLANE TOP VIEW SIDE VIEW 0.35 / 0.45 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 CHAMFERED 0.30 1 2 3 3.0 / 3.75 0.2 MIN. 0.35 / 0.45 Figure 14: 32-pin QFN Package Drawing 0.25 1.5 / 1.875 0.5 0.5 0.25 BOTTOM VIEW 22 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 15.2 28-pin SO .050 TYP. (1.270) .305 (7.747) .285 (7.239) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .110 (2.790) .092 (2.336) .016 nom (0.40) .420 (10.668) .390 (9.906) .335 (8.509) .320 (8.128) Figure 15: 28-pin SO Package Drawing Rev. 1.5 23 73S8010C Data Sheet DS_8010C_024 16 Package Pin Designation Use handling procedures necessary for a static sensitive component. 16.1 32-pin QFN AUX2UC AUX1UC NC SAD2 SAD1 SAD0 I/OUC 26 32 31 30 29 28 27 GND LIN VDD NC PRDWN NC PRES NC 1 2 3 4 5 6 7 8 10 11 12 13 14 15 AUX2 AUX1 CLK RST GND VCC NC I/O 16 9 25 NC 24 23 22 XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ TERIDIAN 73S8010C 21 20 19 18 17 Figure 13: 73S8010C 32-pin QFN Pin Out (Top View) 24 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet 16.2 28-pin SO SAD0 SAD1 SAD2 GND LIN VDD NC PWRDN NC PRES I/O AUX2 AUX1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AUX2UC AUX1UC I/OUC XTALOUT XTALIN INT GND VDD SDA SCL VDDF_ADJ VCC RST CLK 73S8010C Figure 15: 73S8010C 28-pin SO Pin Out (Top View) Rev. 1.5 25 73S8010C Data Sheet DS_8010C_024 17 Ordering Information Part Description 73S8010C-SO 28-pin Lead-Free SO 73S8010C-SO 28-pin Lead-Free SO Tape / Reel 73S8010C-QFN 32-pin Lead-Free QFN 73S8010C-QFN 32-pin Lead-Free QFN Tape / Reel Order Number 73S8010C-IL/F 73S8010C-ILR/F 73S8010C-IM/F 73S8010C-IMR/F Packaging Mark 73S8010C-IL 73S8010C-IL 73S8010C 73S8010C 18 Related Documentation The following 73S8010C documents are available from Teridian Semiconductor Corporation: 73S8010C Data Sheet (this document) 73S8010C 28SO Demo Board User’s Guide 73S8010C QFN Demo Board User’s Guide 19 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8010C, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com. 26 Rev. 1.5 DS_8010C_024 73S8010C Data Sheet Revision History Revision 1.0 1.2 1.3 1.4 1.5 Date 6/13/2005 9/21/2005 12/5/2007 1/17/2008 4/3/2009 Description First publication. Changed SDATA hold time. Added ISO and ENV logo, remove leaded package options, replace 32QFN punched with SAWN, update 28SO dimension. Changed dimension of bottom exposed pad on 32QFN mechanical package figure. Removed all references to VPC as VPC must be tied to VDD. © 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com Rev. 1.5 27