78P2351R-IM

78P2351R Serial 155M NRZ to CMI Converter DATA SHEET AUGUST 2006 DESCRIPTION The 78P2351R is Teridian’s second generation Line Interface Unit (LIU) for 155 Mbit/s electrical SDH interfaces (STM1e). The device is a single chip solution that includes an integrated Clock & Data Recovery in both the transmit and receive paths for easy, cost efficient NRZ to CMI conversion. The device interfaces to 75Ω coaxial cable through wideband transformers and can handle over 12.7dB of cable loss. By eliminating the needs for synchronous clocks, the small 78P2351R (7x7mm MLF package) is ideal for new STM1e (ES1) Small Form-factor Pluggable (SFP) transceiver modules. FEATURES • • • • • • • • • • • ITU-T G.703 compliant, adjustable cable driver for 155.52 Mbps CMI-coded coax transmission Integrated adaptive CMI equalizer and CDR in receive path handles over 12.7dB of cable loss LVPECL-compatible system interface with integrated CDR in transmit path for flexible NRZ to CMI conversion Configurable via HW control pins or 4-wire serial port interface Compliant with ANSI T1.105.03-1994; ITU-T G.813, G.825, G.958; and Telcordia GR-253CORE for jitter performance Receive Loss of Signal (Rx LOS) detection Receive Monitor Mode handles up to 20dB of flat loss (at max 6dB cable loss) Optional fixed backplane equalizer compensates for up to 1.5m of trace Operates from a single 3.3V supply Available in a small 7x7mm 56-pin QFN package Industrial Temperature: -40˚C to +85˚C APPLICATIONS • • • • • • STM1e SFP modules SDH/ATM Line Cards Add Drop Multiplexers (ADMs) PDH/SDH Test Equipment Digital Microwave Radios Multi-Service Switches BLOCK DIAGRAM 78P2351R Tx Disable Fixed Eq. 75ohm Coax (CMI Encoded) CDR TD + TD - Adaptive Eq. CMI ENDEC CDR RD + RD Rx LOS LVPECL Data (NRZ Encoded) Page: 1 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter TABLE OF CONTENTS ................................................................................................ 2 FUNCTIONAL DESCRIPTION........................................................................................ 4 REFERENCE CLOCK ............................................................................................................................4 RECEIVER OPERATION .......................................................................................................................4 Receiver Monitor Mode ..................................................................................................................4 Receive Loss of Signal .................................................................................................................4 TRANSMITTER OPERATION ................................................................................................................5 Plesiochronous Mode ....................................................................................................................5 Synchronous Mode ........................................................................................................................5 Clock Synthesizer...........................................................................................................................5 Pulse Amplitude Adjustment.........................................................................................................6 Transmit Backplane Equalizer ......................................................................................................6 POWER-DOWN FUNCTION .................................................................................................................6 LOOPBACK MODES .............................................................................................................................6 POWER-ON RESET ..............................................................................................................................7 SERIAL CONTROL INTERFACE .........................................................................................................7 REGISTER DESCRIPTION............................................................................................. 8 REGISTER ADDRESSING.....................................................................................................................8 REGISTER TABLE.................................................................................................................................8 LEGEND .................................................................................................................................................9 GLOBAL REGISTERS ...........................................................................................................................9 ADDRESS 0-0: MASTER CONTROL REGISTER .........................................................................9 PORT-SPECIFIC REGISTERS ............................................................................................................10 ADDRESS 1-0: MODE CONTROL REGISTER ...........................................................................10 ADDRESS 1-1: SIGNAL CONTROL REGISTER.........................................................................11 ADDRESS 1-2: ADVANCED TX CONTROL REGISTER 1 .........................................................11 ADDRESS 1-3: ADVANCED TX CONTROL REGISTER 0 .........................................................12 ADDRESS 1-4: RESERVED.........................................................................................................12 ADDRESS 1-5: STATUS MONITOR REGISTER.........................................................................12 ADDRESS 1-6, 1-7: RESERVED...................................................................................................13 PIN DESCRIPTION ....................................................................................................... 14 LEGEND ...............................................................................................................................................14 TRANSMITTER PINS ...........................................................................................................................14 RECEIVER PINS ..................................................................................................................................14 REFERENCE AND STATUS PINS ......................................................................................................14 CONTROL PINS ..................................................................................................................................15 SERIAL-PORT PINS ............................................................................................................................16 POWER AND GROUND PINS .............................................................................................................16 Page: 2 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter TABLE OF CONTENTS (continued) ELECTRICAL SPECIFICATIONS ................................................................................. 17 ABSOLUTE MAXIMUM RATINGS..........................................................................................................17 RECOMMENDED OPERATING CONDITIONS ......................................................................................17 DC CHARACTERISTICS.........................................................................................................................17 ANALOG PINS CHARACTERISTICS.....................................................................................................18 DIGITAL I/O CHARACTERISTICS..........................................................................................................18 Pins of type CI, CID ........................................................................................................................18 Pins of type CIT ..............................................................................................................................18 Pins of type CIS ..............................................................................................................................18 Pins of type COZ ............................................................................................................................18 Pins of type PO ...............................................................................................................................19 Pins of type PI.................................................................................................................................19 Pins of type OD...............................................................................................................................19 REFERENCE CLOCK CHARACTERISTICS..........................................................................................19 SERIAL-PORT TIMING CHARACTERISTICS........................................................................................20 TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE .................................................................21 TRANSMITTER OUTPUT JITTER ..........................................................................................................24 RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled)..................................25 RECEIVER JITTER TOLERANCE ..........................................................................................................26 RECEIVER JITTER TRANSFER FUNCTION .........................................................................................27 LOSS OF SIGNAL CONDITIONS ...........................................................................................................28 APPLICATION INFORMATION .................................................................................... 28 EXTERNAL COMPONENTS ...................................................................................................................28 TRANSFORMER SPECIFICATIONS ......................................................................................................28 THERMAL INFORMATION .....................................................................................................................28 MECHANICAL SPECIFICATIONS ............................................................................... 29 PACKAGE INFORMATION .......................................................................................... 30 ORDERING INFORMATION ............................................................................................................ 30 Revision History ........................................................................................................................................31 Page: 3 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter FUNCTIONAL DESCRIPTION The 78P2351R contains all the necessary transmit and receive circuitry for connection between 155.52Mbit/s NRZ data sources (STS-3/STM-1) and CMI encoded electrical interfaces (ES1/STM-1e). The 78P2351R system interface mimics a 3.3V optical transceiver module and only requires a reference clock and wideband transformer to complete the electrical interface. The chip can be controlled via control pins or serial port register settings. In hardware mode (pin control) the SPSL pin must be low. Additionally, the following unused pins must be set accordingly: SDO pin must be tied low SDI pin must be tied low SEN pin must be tied high In software mode (SPSL pin high), control pins set register defaults upon power-up or reset. The 78P2351R can then be configured via the 4-wire serial control interface. See Pin Descriptions section for more information. REFERENCE CLOCK The 78P2351R requires a reference clock supplied to the CKREFP/N pins. For reference frequencies of 19.44MHz or 77.76MHz, the device accepts a single ended CMOS level input at CKREFP (with CKREFN pin tied to ground). For reference frequency of 155.52MHz, the device accepts a differential LVPECL clock input at CKREFP/N. The frequency of this reference input is selected by either the CKSL control pin or register bit as follows: CKSL pin Low Float High CKSL[1:0] bits 00 10 11 Reference Frequency 19.44MHz 77.76MHz 155.52MHz The recovered CMI signal first enters an AGC and an adaptive equalizer designed to overcome intersymbol interference caused by long cable lengths. The variable gain differential amplifier automatically controls the gain to maintain a constant voltage level output regardless of the input voltage level. The outputs of the data comparators are connected to the clock recovery circuits. The clock recovery system employs a Delay Locked Loop (DLL), which utilizes a line-rate reference frequency derived from the clock applied to the CKREFP/N pins. After the clock and data have been recovered, the data is decoded to binary by the CMI decoder. The SODP/N pins output the recovered NRZ data at LVPECL levels. Receiver Monitor Mode The SCK_MON pin or MON register bit puts the receiver in monitor mode and adds approximately 20dB of flat gain to the receive signal before equalization. Rx Monitor Mode can handle 20dB of flat loss typical of monitoring points with up to 6dB (typical 225ft) of cable loss. Note that Loss of Signal detection is disabled during Rx Monitor Mode. Receive Loss of Signal Detect The 78P2351R includes a Loss of Signal (LOS) detector. When the peak value of the received signal is less than approximately 19dB below nominal for approximately 110 UI, Receive Loss of Signal is asserted. The Rx LOS signal is cleared when the received signal is greater than approximately 18dB below nominal for 110 UI. During Rx LOS conditions, the receive clock will remain on the last phase tap of the Rx DLL outputting a stable clock while the receive data outputs are squelched and held at logic ‘0’. Note: Rx Loss of Signal detection is disabled during Local Loopback and Receive Monitor Modes. RECEIVER OPERATION The receiver accepts an ITU-T G.703 compliant CMI encoded signal at 155.52Mbit/s from the RXP/N inputs. When properly terminated and transformercoupled to the line, the receiver can handle over 12.7dB of cable loss. The receiver’s jitter tolerance exceeds all relevant standards even with 12.7dB worth of cable attenuation and inter-symbol interference (ISI). See Receiver Jitter Tolerance section for more info. Page: 4 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter TRANSMITTER OPERATION The transmitter section generates an adjustable ITU-T G.703 compliant analog signal for transmission through a wideband transformer onto 75Ω coaxial cable. Differential NRZ data is input to the 78P2351R on the SIDP/N pins at LVPECL levels and passed to a low jitter clock and data recovery circuit. An optional clock decoupling FIFO is provided to decouple the on chip and off chip clocks. The NRZ data is encoded using CMI line coding to ensure an adequate number of transitions. Each of the transmit timing modes can be configured in HW mode or SW mode as shown in the table below. Tx Mode Reserved Synchronous (FIFO enabled) Plesiochronous Loop-timing Synchronous Mode When the NRZ transmit data is source synchronous with the reference clock applied at CKREFP/N as shown in Figure 2, the 78P2351R can be optionally used in synchronous mode or re-timing mode. In this mode, the 78P2351R will recover the clock from the NRZ data input and re-time the data in an integrated +/- 4-bit FIFO. System Reference Clock CKREFP/N NRZ SIDP/N CMIP/N CMI XFMR Coax Framer/ Mapper NRZ TDK 78P2351R SODP/N RXP/N CMI XFMR Coax HW Control CKMODE Low Floating High n/a SW Control SMOD[1:0] 00 10 01 11 Figure 2: Synchronous Since the reference clock and transmit clock/data go through different delay paths, it is inevitable that the phase relationship between the two clocks can vary in a bounded manner due to the fact that the absolute delays in the two paths can vary over time. The transmit FIFO allows long-term clock phase drift between the Tx clock and system reference clock, not exceeding +/- 25.6ns, to be handled without transmit error. If the clock wander exceeds the specified limits, the FIFO will over or under flow, and the FERR register signal will be asserted. This signal can be used to trigger an interrupt. This interrupt event is automatically cleared when a FIFO Reset (FRST) pulse is applied, and the FIFO is recentered. Notes: 1) External remote loopbacks (i.e. loopback within framer) are not possible in synchronous operation (FIFO enabled) unless the data is re-justified to be synchronous to the system reference clock or the 78P2351R is configured for looptiming operation. 2) During IC power-up or transmit power-up, the clocks going to the FIFO may not be stable and cause the FIFO to overflow or underflow. As such, the FIFO should be manually reset using FRST anytime the transmitter is powered-up. Clock Synthesizer The transmit clock synthesizer is a low-jitter PLL that generates a 311.04 MHz clock for the CMI encoder. A synthesized 155.52 MHz reference clock is also used in both the receive and transmit sides for clock and data recovery. Plesiochronous Mode Plesiochronous mode represents a common condition where a synchronous reference clock is not available. In this mode, the 78P2351R will recover the transmit clock from the plesiochronous data and bypass the internal FIFO and re-timing block. This mode is commonly used for mezzanine cards, modules, and any application where the reference clock can’t always be synchronous to the transmit source clock/data System Clock XO CKREFP NRZ SIDP/N CMIP/N CMI XFMR Coax Framer/ Mapper NRZ TDK 78P2351R SODP/N RXP/N CMI XFMR Coax Figure 1: Plesiochronous Mode Page: 5 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter Pulse Amplitude Adjustment Contact TDK applications for information on user programmable registers with up to 200mV of programmable transmit gain. Transmit Backplane Equalizer An optional fixed LVPECL equalizer is integrated in the transmit path for architectures that use LIUs on active interface cards. The fixed equalizer can compensate for up to 1.5m of trace and can be enabled by the TXOUT1 pin or TXEQ bit as follows: TXOUT1 pin Low Float TXEQ bit 1 0 Tx Equalizer Enabled Disabled Adaptive Eq. CDR Fixed Eq. TD + TD - Line-side Adaptive Eq. CDR CMI ENDEC RD + RD - Figure 3: Remote (analog) Loopback TD + TD - CDR Fixed Eq. CMI ENDEC CDR RD + RD - POWER-DOWN FUNCTION Power-down control is provided to allow the 78P2351R to be shut off. Transmit and receive power-down can be set independently through SW control. Global power-down is achieved by powering down both the transmitter and receiver. Note: the 4-wire serial port interface and configuration registers are not affected by powerdown. The transmitter can also be powered down using the TXPD control pin. The CMI outputs are tri-stated during transmit power-down for redundancy applications. The TXPD pin is active in both hardware and software modes. LOOPBACK MODES In SW mode, LLBK and RLBK bits in the Signal Control register are provided to activate the local and remote analog loopback modes respectively. In HW mode, the LPBK pin can be used to activate local and remote analog loopback paths as shown in the table below. LPBK pin Low Loopback Mode Normal operation Remote (analog) Loopback: Recovered receive clock and data looped back directly to the transmit driver. The CMI decoder and most of transmit path is bypassed (including the redundant Tx monitor output) Local (analog) Loopback: Transmit clock and data looped back to receiver at the analog media interface. Figure 4: Local (analog) Loopback In SW mode only, a Full Remote (digital) Loopback bit FLBK is also available in the Advanced Tx Control register. This loopback exercises the entire Rx and Tx paths of the 78P2351 including the Tx clock recovery unit. As such, the user must enable either Plesiochronous or Loop-timing transmit modes to utilize the Full Remote (digital) Loopback. TD + TD - CDR Fixed Eq. Line-side Adaptive Eq. CDR CMI ENDEC RD + RD - Figure 5: Remote (Digital) Loopback Float High Page: 6 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter INTERNAL POWER-ON RESET Power-On Reset (POR) function is provided on chip. Roughly 50 µs after Vcc reaches 2.4V at power up, a reset pulse is internally generated. This resets all registers to their default values as well as all state machines within the transceiver to known initial values. The reset signal is also brought out to the PORB pin. The PORB pin is a special function analog pin that allows for the following: • Override the internal POR signal by driving in an external active low reset signal; • Use the internally generated POR signal to trigger other resets; • Add external capacitor to slow down the release of power-on reset (approximately 8µs per nF added). NOTE: Do not pull-up the PORB pin to Vcc or drive this pin high during power-up. This will prevent the internal reset generator from resetting the entire chip and may result in errors. SERIAL CONTROL INTERFACE The serial port controlled register allows a generic controller to interface with the 78P2351R. It is used for mode settings, diagnostics and test, retrieval of status and performance information, and for on-chip fuse trimming during production test. The SPSL pin must be high in order to use the serial port. The serial interface consists of 4 pins: Serial Port Enable (SEN), Serial Clock (SCK_MON), Serial Data In (SDI), Serial Data Out (SDO). The SEN pin initiates the read and write operations. It can also be used to select a particular device allowing SCK_MON, SDI and SDO to be bussed together. SCK_MON is the clock input that times the data on SDI and SDO. Data on SDI is latched in on the rising-edge of SCK_MON, and data on SDO is clocked out using the falling edge of SCK_MON. SDI is used to insert mode, address, and register data into the chip. Address and Data information are input least significant bit (LSB) first. The mode and address bit assignment and register table are shown in the following section. SDO is a tristate capable output. It is used to output register data during a read operation. SDO output is normally high impedance, and is enabled only during the duration when register data is being clocked out. Read data is clocked out least significant bit (LSB) first. If SDI coming out of the micro-controller chip is also tristate capable, SDI and SDO can be connected together to simplify connections. The maximum clock frequency for register access is 20MHz. Page: 7 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter REGISTER DESCRIPTION REGISTER ADDRESSING Address Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Sub-Address PA[0] SA[2] SA[1] SA[0] Bit 1 Bit 0 Read/ Write R/W* Port Address Assignment PA[3] PA[2] PA[1] REGISTER TABLE a) PA[3:0] = 0 : Global Registers Sub Addr 0 1 2 Reg. Name MSCR (R/W) -(R/W) -(R/W) Description Master Control Reserved Reserved Bit 7 - - - Bit 6 - - - Bit 5 - - - Bit 4 CKSL[1] - - Bit 3 CKSL[0] - - Bit 2 - - - Bit 1 - - - Bit 0 SRST - - b) PA[3:0] = 1 : Port-Specific Registers Sub Addr 0 1 2 3 4 5 6-7 Reg. Name MDCR (R/W) SGCR (R/W) ACR1 (R/W) ACR0 (R/W) -(R/W) STAT (R/C) -Description Mode Control Signal Control Advanced Tx Control 1 Advanced Tx Control 0 Reserved Status Monitor Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MON - - BST[1] - - -Bit 1 - - TPK BST[0] - TXLOS -Bit 0 - FRST TXEQ FLBK - FERR -- PDTX PDRX - TCMIINV RCMIINV LOSOR --- --- --- --- ---- SMOD[1] SMOD[0] RLBK LLBK -- -- -- RXLOS - --- Page: 8 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter REGISTER DESCRIPTION (continued) LEGEND TYPE R/O R/C DESCRIPTION Read only Read and Clear TYPE R/W DESCRIPTION Read or Write GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER BIT 7:5 NAME -TYPE R/W DFLT VALUE 0X0 DESCRIPTION Reserved. Reference Clock Frequency Select: Selects the reference clock frequency input at CKREFP/N pins. 11: 155.52 MHz (differential LVPECL input) 10: 77.76 MHz (single-ended CMOS input) – Tie CKREFN to ground. 00: 19.44 MHz (single-ended CMOS input) – Tie CKREFN to ground. Note: Default values depend on the CKSL pin setting upon reset or power up. Reserved. Register Soft-Reset: When this bit is set, all registers are reset to their default values. This register bit is self-clearing. 4:3 CKSL [1:0] R/W X 2:1 0 -SRST R/W R/W X0 0 ADDRESS 0-1: RESERVED BIT 7:0 NAME -TYPE R/W DFLT VALUE 00100X11 DESCRIPTION Reserved. ADDRESS 0-2: RESERVED BIT 7:0 NAME -TYPE R/W DFLT VALUE XXXXXXX0 DESCRIPTION Reserved. Page: 9 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter REGISTER DESCRIPTION (continued) PORT-SPECIFIC REGISTERS For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and the read/write operation will be ignored. ADDRESS 1-0: MODE CONTROL REGISTER BIT 7 NAME PDTX TYPE R/W DFLT VALUE 0 DESCRIPTION Transmitter Power-Down: 0 : Normal Operation 1 : Power-Down. CMI Transmit output is tri-stated. Receiver Power-Down: 0 : Normal Operation 1 : Power-Down Reserved. Serial Mode Interface Selection: SMOD[1] SMOD[0] 0 0 Reserved 4 SMOD[1] R/W X Synchronous data is passed through the CDR and then through the FIFO. 0 1 Plesiochronous data is passed through the CDR to recover a clock, but the FIFO is bypassed because the data is not synchronous with the reference clock. 1 1 Loop Timing Mode Enable: The recovered receive clock is used as the reference for the transmit DLL and FIFO. Note: Default values depend on the CKMODE pin setting upon reset or power up. Receive Monitor Mode Enable: 0: Normal Operation 1: Adds 20dB of flat gain to the receive signal before equalization. Reserved. 1 0 6 5 PDRX -- R/W R/W 0 0 3 SMOD[0] R/W X 2 1:0 MON -- R/W R/W 0 01 Page: 10 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter REGISTER DESCRIPTION (continued) ADDRESS 1-1: SIGNAL CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION Transmit CMI Inversion: This bit will flip the polarity of the transmit CMI data outputs at CMIP/N. For debug use only. 0: Normal 1: Invert Receive CMI Inversion: This bit will flip the polarity of the receive CMI data inputs at RXP/N. For debug use only. 0: Normal 1: Invert Receive Loss of Signal Override/Disable: When set, the LOS signal will always remain low. 0: Normal 1: Forces LOS output to be low and resets counter Analog Loopback Selection: RLBK LLBK 0 0 Normal operation 1 0 Remote Loopback Enable: Recovered receive data is looped back to the transmit driver for retransmission. 0 1 Local Loopback Enable: The transmit data is looped back and used as the input to the receiver. Reserved. FIFO Reset: 0: Normal operation 1: Reset FIFO pointers to default locations. This reset should be initiated anytime the transmitter or IC powers up to ensure the FIFO is centered after internal VCO clocks and external transmit clocks are stable. NOTE: FIFO reset not required for Plesiochronous Mode 7 TCMIINV R/W 0 6 RCMIINV R/W 0 5 LOSOR R/W 0 4 RLBK R/W 0 3 2:1 LLBK -- R/W R/W 0 00 0 FRST R/W 0 ADDRESS 1-2: ADVANCED TRANSMIT CONTROL REGISTER 1 BIT 7:1 NAME -TYPE R/W DFLT VALUE 000000 0 DESCRIPTION Reserved. Transmit Fixed Equalizer Enable: When enabled, compensates for between 0.75m and 1.5m of FR4 trace to the LVPECL data inputs SIDP/N 0: Normal Operation 1: Enable equalizer 0 TXEQ R/W 0 Page: 11 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter REGISTER DESCRIPTION (continued) ADDRESS 1-3: ADVANCED TRANSMIT CONTROL REGISTER 0 BIT 7:3 NAME -TYPE R/W DFLT VALUE 10101 DESCRIPTION Reserved. Transmit Driver Amplitude Boost: Adds 5% or 10% of boost to the CMI output. 00 : Normal amplitude 01 : 5% boost 10 : Reserved 11 : 10% boost Full Remote (digital) Loopback Enable: When enabled the recovered receive data is decoded and looped back to the transmit clock recovery unit exercising the entire receive and transmit paths. NOTE: Must be used in conjunction with Plesiochronous Mode or LoopTiming Mode. 2:1 BST[1:0] R/W 00 0 FLBK R/W 0 ADDRESS 1-4: RESERVED BIT 7:0 NAME -TYPE R/W DFLT VALUE 1XX00000 DESCRIPTION Reserved. ADDRESS 1-5: STATUS MONITOR REGISTER BIT 7:5 4 3:2 1 NAME -RXLOS -TXLOS TYPE R/C R/C R/C R/C DFLT VALUE XXX X X X DESCRIPTION Reserved. Receive Loss of Signal Indication: 0: Normal operation 1: Loss of signal condition detected at CMI inputs Reserved. Transmit Loss of Signal Indication: 0: Valid transmit input signal detected at SIDP/N 1: No valid signal detected at SIDP/N Transmit FIFO Error Indication: This bit is set whenever the internal FERR signal is asserted, indicating that the FIFO is operating at its depth limit. It is reset to 0 when the FRST bit is asserted. 0: Normal operation 1: Transmit FIFO phase error 0 FERR R/C X Page: 12 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ADDRESS 1-6: TRANSMIT GAIN REGISTER BIT 7:0 NAME RSVD TYPE R/O DFLT VALUE 0 DESCRIPTION Reserved for pulse amplitude programmability. Contact Teridian applications support for more information. ADDRESS 1-7: RESERVED BIT 7:0 NAME RSVD TYPE R/O DFLT VALUE 0 DESCRIPTION Reserved for test. Page: 13 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter PIN DESCRIPTION LEGEND TYPE A CIT CI CID CIS COZ DESCRIPTION Analog Pin 3-State CMOS Digital Input CMOS Digital Input CMOS Digital Input w/ Pull-down CMOS Schmitt Trigger Input CMOS Tristate Digital Output TYPE PO OD PI S G DESCRIPTION LVPECL-Compatible Differential Output Open-drain Output LVPECL-Compatible Differential Input Supply Ground TRANSMITTER PINS NAME SIDP SIDN PIN 4 5 TYPE PI DESCRIPTION Transmit Serial Data Input: Differential NRZ data input. See Transmitter Operation section for more info on different timing modes. Transmit Serial CMI Data Output: A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse templates when properly terminated and transformer coupled to 75ohm cable. Notes: 1) Pins are tri-stated during transmit power-down. 2) Pins are active, but undefined during reset. CMIP CMIN 53 54 A RECEIVER PINS NAME SODP SODN RXP RXN PIN 13 14 50 51 TYPE DESCRIPTION Receive Serial NRZ Data Output: Recovered serial data decoded into NRZ format and output at LVPECL levels. Notes: 1) Outputs are squelched during LOS and held low. 2) Pins are active, but undefined during reset. Receive Serial CMI Input: Receive inputs that should be differentially terminated and transformer coupled to the coaxial cable. PO A REFERENCE AND STATUS PINS NAME PIN TYPE DESCRIPTION Reference Clock Input: (Required) A reference clock input used for clock/data recovery and generation. Can be a differential 155.52MHz differential LVPECL Input (Type PI) at CKREFP/N or a single-ended 19.44MHz or 77.78MHz CMOS Input (Type CI) at CKREFP (tie CKREFN to ground when unused). Loss of Signal (active-high): Standards compatible loss of signal indicator. Power-On Reset (active low): See Power-On Reset description on use of this pin. Do not pull-up to Vcc. CKREFP CKREFN 45 44 PI/ CI LOS PORB 33 36 OD A Page: 14 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter PIN DESCRIPTION (continued) CONTROL PINS NAME PIN TYPE DESCRIPTION Loopback Selection: Low: Normal operation Float: Remote Loopback Enable: Recovered receive data and clock are looped back to the transmitter for retransmission. High: Local Loopback Enable: The transmit data is looped back and used as the input to the receiver. Clock Mode Selection: Low: Reserved Float: Reference clock is synchronous to transmit data. Clock is recovered with a CDR and data is passed through a FIFO High: Reference clock is plesiochronous to transmit data. Clock is recovered with a CDR and the FIFO is bypassed Advanced Tx Control 1: Low: Enables fixed LVPECL equalizer at the transmit inputs SIDP/N (for FR4 trace lengths up to 1.5m). Float: Normal operation High: Normal operation Advanced Tx Control 0: Low: Nominal amplitude Float: 5% amplitude boost High: 10% amplitude boost Transmitter Power Down: When high, powers down and tri-states the transmit driver. Serial Port Selection: When high, chip is software controlled through the 4-wire serial port. Reference Clock Frequency Selection: Selects the reference frequency that is supplied at the CKREFP/N pins. Its level is read in at power-up or on the rising edge of a reset signal at the PORB pin. Low: 19.44MHz Float: 77.76MHz High: 155.52MHz LPBK 10 CIT CKMODE 9 CIT TXOUT1 56 CIT TXOUT0 1 CIT TXPD SPSL 8 32 CID CID CKSL 34 CIT Page: 15 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter PIN DESCRIPTION (continued) SERIAL-PORT PINS NAME PIN TYPE DESCRIPTION [SPSL=1] Serial-Port Enable: High during read and write operations. Low disables the serial port. While SEN is low, SDO remains in high impedance state, and SDI and SCK activities are ignored. [SPSL=0] Reserved. Must be tied high [SPSL=1] Serial Clock: Controls the timing of SDI and SDO. [SPSL=0] Receive Monitor Mode Enable: When high, adds 20dB of flat gain to the incoming signal before equalization. [SPSL=1] Serial Data Input: Inputs mode and address information. Also inputs register data during a Write operation. Both address and data are input least significant bit first. [SPSL=0] Reserved. Must be tied low [SPSL=1] Serial Data Output: Outputs register information during a Read operation. Data is output least significant bit first [SPSL=0] Must be tied low SEN 41 CIU SCK_MON 42 CIS SDI 40 CI SDO 39 COZ POWER AND GROUND PINS It is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. NAME VCC GND PIN 2, 6, 11, 31, 38, 43, 48, 52 3, 7, 12, 30, 35, 37, 46, 47, 49, 55 TYPE S G DESCRIPTION Power Supply (Vdd) Ground Page: 16 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER Supply Voltage (Vdd) Storage Temperature Junction Temperature Pin Voltage (CMIP,CMIN) Pin Voltage (all other pins) Pin Current RATING -0.5 to 4.0 VDC -65 to 150 °C -40 to 150 °C Vdd + 1.5 VDC -0.3 to (Vdd+0.6) VDC ±100 mA RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. PARAMETER DC Voltage Supply (Vdd) Ambient Operating Temperature Junction Temperature RATING 3.15 to 3.45 VDC -40 to 85°C -40 to 125°C DC CHARACTERISTICS: PARAMETER Supply Current (including transmitter current through transformer) Receive-only Supply Current Power down Current SYMBOL Idd CONDITIONS Max cable length Transmitter disabled (PDTX=1) PDTX=1, PDRX=1 MIN NOM 160 MAX 180 UNIT mA Iddr Iddq 92 7 106 10 mA mA Page: 17 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) ANALOG PINS CHARACTERISTICS: The following table is provided for informative purpose only. Not tested in production. PARAMETER RXP and RXN Common-Mode Bias Voltage RXP and RXN Differential Input Impedance Analog Input/Output Capacitance PORB Input Impedance DIGITAL I/O CHARACTERISTICS: Pins of type CI, CID: PARAMETER Input Voltage Low Input Voltage High Input Current Pull-down Resistance Input Capacitance Pins of type CIT: PARAMETER Input Voltage Low Input Voltage High Minimum impedance to be considered as “float” state Pins of type CIS: PARAMETER Low-to-High Threshold High-to-Low Threshold Input Current Input Capacitance Pins of type COZ: PARAMETER Output Voltage Low Output Voltage High Output Transition Time Effective Source Impedance Tri-state Output Leakage Current SYMBOL Vol Voh Tt Rscr Iz -1 CONDITIONS Iol = 8mA Ioh = -8mA CL = 20pF, 10-90% 30 1 2.4 2 MIN NOM MAX 0.4 UNIT V V ns Ω µA SYMBOL Vt+ VtIil, Iih Cin CONDITIONS MIN 1.3 0.8 -1 8 NOM MAX 1.7 1.2 1 UNIT V V µA pF SYMBOL Vtil Vtih Rtiz Vcc-0.6 30 CONDITIONS MIN NOM MAX 0.4 UNIT V V kΩ SYMBOL Vil Vih Iil, Iih Rpd Cin Type CID only 2.0 -1 40 0 58 8 1 120 CONDITIONS MIN NOM MAX 0.8 UNIT V V µA kΩ pF SYMBOL Vblin Rilin Cin -CONDITIONS Ground Reference MIN 1.9 20 8 5 NOM MAX 2.6 UNIT V kΩ pF kΩ Page: 18 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) DIGITAL I/O CHARACTERISTICS: (continued) Pins of type PO: PARAMETER Signal Swing Common Mode Level Effective Source Impedance Rise Time Fall Time Pins of type PI: PARAMETER Signal Swing Common Mode Level Pins of type OD PARAMETER Output Voltage Low Pull-down Leakage Current Pull-up Resistor SYMBOL Vol Ipd Rpu CONDITIONS Iol = 8mA Logic high output 4.7 MIN NOM MAX 0.4 1 10 UNIT V nA kΩ SYMBOL Vpki Vcm CONDITIONS Vdd referenced MIN 0.3 -1.6 NOM -1.2 MAX -0.8 UNIT V V SYMBOL Vpk Vcm Reff Tr Tf 10-90% 10-90% Vdd referenced CONDITIONS MIN 0.5 -1.55 NOM 0.8 -1.2 20 0.8 0.8 1.2 1.2 MAX 1.1 -1.1 UNIT V V Ω ns ns REFERENCE CLOCK CHARACTERISTICS: PARAMETER CKREF Duty Cycle CKREF Frequency Stability SYMBOL -Synchronous mode CONDITIONS MIN 40 -20 -75 NOM MAX 60 +20 UNIT % ppm -- Plesiochronous or Loop-timing mode. (see Note 1) +75 Note 1: In Plesiochronous mode, the transmit data source (i.e. framer) must still be of +/-20ppm quality in order to meet SONET/SDH bit rate requirements. Page: 19 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) SERIAL-PORT TIMING CHARACTERISTICS: PARAMETER SDI to SCK setup time SDI to SCK hold time SCK to SDO propagation delay SCK Frequency SYMBOL tsu th tprop SCK CONDITIONS MIN 4 4 10 20 TYP MAX UNIT ns ns ns MHz CS SCK tsu th tsu th SDI SDO X 1 SA0 SA1 SA2 PA0 PA1 PA2 PA3 tprop X or Z Z D0 D1 D2 D3 D4 D5 D6 D7 Z Figure 6: Read Operation CS SCK tsu th tsu th SDI SDO X 0 SA0 SA1 SA2 PA0 PA1 PA2 PA3 D0 D1 D2 D3 D4 D5 D6 D7 X Z Figure 7: Write Operation Page: 20 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE Bit Rate: 155.52Mbits/s ± 20ppm Code: Coded Mark Inversion (CMI) Relevant Specification: ITU-T G.703, Telcordia GR-253, ANSI T1.102 With the coaxial output port driving a 75Ω load, the output pulses conform to the templates in Figures 8 and 9. These specifications are tested during production test. Consult application note for reference schematic, layout guidelines, and recommended transformers. PARAMETER Peak-to-peak Output Voltage (Fuse-trimmed to nominal target at final test) Rise/ Fall Time CONDITION Template, steady state MIN 0.9 NOM 1.04 MAX 1.1 UNIT V 10-90% Negative Transitions -0.1 -0.5 -0.35 2 0.1 0.5 0.35 ns Transition Timing Tolerance Positive Transitions at Interval Boundaries Positive Transitions at midinterval ns The following specifications are not tested during production test. They are included for information only. Note that the return loss depends on the board layout and the particular transformer used. PARAMETER Output Impedance Return Loss CONDITION Driver is open drain 7MHz to 240MHz 15 MIN NOM 1 8 MAX UNIT MΩ pF dB Page: 21 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 0.50 0.45 0.40 1ns 0.1ns 0.1ns 0.35ns T = 6.43ns (Note 1) (Note 1) Nominal Pulse 1.608ns 1ns 0.1ns 0.35ns 0.1ns 1.608ns 1ns 0.05 -0.05 Nominal Zero Level (Note 2) -0.40 -0.45 -0.50 -0.55 -0.60 1ns 1.608ns (Note 1) 1ns 1.608ns 1ns (Note 1) Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Figure 8 – Mask of a Pulse corresponding to a binary Zero. Page: 22 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 0.50 0.45 0.40 1ns 0.1ns 0.1ns 0.5ns 6.43ns (Note 1) (Note 1) 1ns 0.5ns Nominal Pulse 0.05 -0.05 Nominal Zero Level (Note 2) 3.215ns 1.2ns 1.2ns 3.215ns -0.40 -0.45 -0.50 -0.55 -0.60 1ns 1.608ns (Note 1) 1ns 1.608ns Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 – For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 µF, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed ±0.05V. This may be checked by removing the input signal again and verifying that the trace lies with ±0.05V of the nominal zero level of the masks. Note 3 – Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 – For the purpose of these masks, the rise time and decay time should be measured between –0.4V and 0.4V, and should not exceed 2ns. Note 5 –The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are ± 0.1ns and ±0.5ns respectively. Figure 9 – Mask of a Pulse corresponding to a binary One Page: 23 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.813, G.823, G.825 and G.958; ANSI T1.1021993 and T1.105.03-1994; and GR-253-CORE for all supported rates. Transmit output jitter is not tested during production test. Jitter Detector Transmitter Output 20dB/decade Measured Jitter Amplitude f1 f2 PARAMETER Transmitter Output Jitter CONDITION 200 Hz to 3.5 MHz, measured with respect to CKREF for 60s MIN NOM MAX 0.075 UNIT UIpp Page: 24 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled) Consult application notes for reference schematic, layout guidelines, and recommended transformers. PARAMETER Peak Differential Input Amplitude, RXP and RXN Peak Differential Input Amplitude, RXP and RXN Flat-loss Tolerance Latency PLL Lock Time Return Loss 7MHz to 240MHz 15 CONDITION MON=0. 12.7dB of cable loss MON=1. 20dB flat loss with 6dB cable loss (max) MON=0. All valid cable lengths. MIN 70 25 -2 5 1 TYP MAX 550 80 4 10 10 UNIT mVpk mVpk dB UI µs dB The input signal is assumed compliant with ITU-T G.703 and can be attenuated by the dispersive loss of a cable. The minimum cable loss is 0dB and the maximum is –12.7dB at 78MHz. The “Worst Case” line corresponds to the ITU-T G.703 recommendation. The “Typical” line corresponds to a typical installation referred to in ANSI T1.102-1993. The receiver is tested using the cable model. It is a lumped element approximation of the “Worst Case” line. 30 25 Attenuation (dB) 20 15 10 5 0 1.00E+05 1.00E+06 1.00E+07 Frequency (Hz) Worst Case Typical 1.00E+08 1.00E+09 Figure 10: Typical and worst-case Cable attenuation Page: 25 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TOLERANCE The 78P2351R exceeds all relevant jitter tolerance specifications shown in Figure 11. STM-1e (electrical) jitter tolerance specifications are in ITU-T G.825. Receive jitter tolerance is not tested during production test. 100 155Mbps Electrical (CMI) Interfaces G.825 - STM-1e Tolerance (for 2048 kbps networks) G.825 - STM-1e Tolerance (for 1544 kbps networks) 10 Jitter Tolerance ( UIpp ) 1 0.1 0.01 1.E+00 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Jitter Frequency Figure 11: Jitter Tolerance - electrical (CMI) interfaces PARAMETER CONDITION 10Hz to 19.3Hz 19.3Hz to 500Hz MIN 38.9 NOM 750 f-1 MAX UNIT UIpp µs UIpp STM-1e Jitter Tolerance 500Hz to 6.5kHz 6.5kHz to 65kHz 65kHz to 1.3MHz 1.5 9800 f-1 0.15 µs UIpp Page: 26 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. The corner frequency of the Rx DLL is approximately 120 kHz. Receiver jitter transfer function is not tested during production test. 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 Figure 12: Jitter Transfer PARAMETER Receiver Jitter transfer function Jitter transfer function roll-off CONDITION below 120 kHz MIN NOM MAX 0.1 UNIT dB dB per decade 20 Page: 27 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter ELECTRICAL SPECIFICATIONS (continued) LOSS OF SIGNAL CONDITION PARAMETER LOS threshold LOS timing CONDITION MIN -35 10 TYP -19 110 MAX -15 255 UNIT dB UI Nominal value Maximum cable loss 3 dB 15dB Loss of Signal must be cleared Tolerance range LOS can be detected or cleared 35dB Loss of Signal must be declared APPLICATION INFORMATION EXTERNAL COMPONENTS: COMPONENT Receiver Termination Resistor Transmitter Termination Resistor TRANSFORMER SPECIFICATIONS: COMPONENT Turns Ratio for the Receiver Turns Ratio for the Transmitter (center-tapped) Suggested Manufacturers: Halo, MiniCircuits, Tamura, Belfuse THERMAL INFORMATION: PACKAGE CONDITIONS No forced air; 4-layer JEDEC test board No forced air; 4-layer JEDEC test board Die attach pad soldered to PCB ΘJA ( ˚C/W) 46.8 23.5 ΘJC ( ˚C/W) 16.6 15.6 VALUE UNITS 1:1 1:1CT TOLERANCE PIN(S) RXP RXN CMIP CMIN VALUE 75 75 UNITS Ω Ω TOLERANCE 1% 1% Standard 56-pin JEDEC QFN SCHEMATICS For reference schematics, layout guidelines, suggested transformer part numbers, etc. please check Teridian Semiconductor's website or contact your local sales representative for the latest application note(s) and/or evaluation boards. Page: 28 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter MECHANICAL SPECIFICATIONS 0.90 MAX 7.000 3.500 6.750 0.05 MAX 3.375 SEATING PLANE 1 0.40 6.750 6.750 3.375 3.500 0.23 ± 0.05 0 =12 SIDE VIEW 5.200 TOP VIEW 5.10 ± 0.15 0.25 MIN. 2.55 ± 0.075 1 2.55 ± 0.075 5.10 ± 0.15 5.200 0.400 ± 0.100 BOTTOM VIEW 56-pin Quad Flat No-lead package (QFN) (All dimensions in mm) Page: 29 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter PACKAGE INFORMATION (Top View) TXOU1 GND CMIN CMIP VCC RXN RXP GND VCC GND GND CKREFP CKREFN VCC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 TXOUT0 VCC GND SIDP SIDN VCC GND TXPD CKMODE LPBK VCC GND SODP SODN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 28 78P2351R-IM 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SCK_MON SEN SDI SDO VCC GND PORB GND CKSL LOS SPSL VCC GND N/C ORDERING INFORMATION PART DESCRIPTION 56-pin QFN; Revision A06 Tape & Reel option Lead-free option ORDER NUMBER 78P2351R-IM append ‘R’ append ‘/F’ PACKAGE MARK 78P2351R-IM xxxxxxxxxxP6 n/a xxxxxxx-xxx xxxxxxxxxxP6F Page: 30 of 31 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 2006 Teridian Semiconductor Corporation Rev. 2.1 78P2351R Serial 155M NRZ to CMI Converter -- v2-0 Revision History Contact Teridian for revision history of earlier releases August 15, 2005: Final Datasheet Release Updated Ordering Numbers to reflect production silicon revision A06 Improved/modified Functional Descriptions Improved/modified Register Descriptions Added FLBK bit Removed Rx LOL bit Improved/modified Pin Descriptions Updated Electrical Specification min/max limits for: DC Characteristics, CID, CIU, CIT, and PO pin types CMI Loss of Signal Conditions Changed name and logo from TDK to Teridian August 15, 2006: Updated Ordering Numbers to remove silicon revision A06 Updated Package Mark from C6 to P6 v2-1 If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Page: 31 of 31 2006 Teridian Semiconductor Corporation Rev. 2.1