DG3157DL-T1-GE3

DG3157 Vishay Siliconix High-Speed, Low RON, SPDT Analog Switch (2:1 Multiplexer/Demultiplexer Bus Switch) DESCRIPTION FEATURES The DG3157 is a high-speed single-pole double-throw, low power, TTL-Compatible bus switch. Using sub-micro CMOS technology, the DG3157 achieves low on-resistance and negligible propagation delay. • Halogen-free According to IEC 61249-2-21 The DG3157 can handle both analog and digital signals and permits signals with amplitudes of up to VCC to be transmitted in either direction. • 1.65 V to 5.5 V VCC operation • Direct cross to industry standard SN74LVC1G3157, NC7SB3157, NLASB3175, Pl5A3157, and STG3157 • SC-70 6-lead package • 5 Ω connection between ports • Minimal propagation delay • Break-before-make switching When the Select pin is low, B0 is connected to the output A pin. When the Select pin is high, B1 is connected to the output A pin. The path that is open will have a highimpedance state with respect to the output. Make-beforebreak is guaranteed. An eptiaxial layer prevents latch-up. • Zero bounce in flow-through mode FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION SC-70 6-Pin B1 1 6 S GND 2 5 V+ B0 3 4 A Top View Device Marking: G1 TRUTH TABLE ORDERING INFORMATION Logic Input (S) Function 0 B0 Connected to A 1 Document Number: 72648 S09-0294-Rev. D, 23-Feb-09 B1 Connected to A Temp. Range Package Part Number - 40 °C to 85 °C SC-70-6 DG3157DL-T1-E3 DG3157DL-T1-GE3 (Halogen-free) www.vishay.com 1 DG3157 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Limit Reference V+ to GND Unit - 0.3 to + 6 S, A, Ba V - 0.3 to (V+ + 0.3) Continuous Current (Any terminal) ± 50 Peak Current (Pulsed at 1 ms, 10 % duty cycle) ± 200 Storage Temperature D Suffix Power Dissipation (Packages)b 6-Pin SC-70c mA - 65 to 150 °C 250 mW Notes: a. Signals on A, or B or S exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 3.1 mW/°C above 70 °C. SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter DC Characteristics High Level Input Voltage Low Level Input Voltage Symbol VSH VSL V+ = 3.0 V, VS = 0.25 V to 0.7 V+e Temp.a Min.b V+ = 1.65 to 1.95 V Full 0.75 V+ V+ = 2.3 to 5.5 V Full 0.7 V+ V+ = 1.65 to 1.95 V Full V+ = 2.3 to 5.5 V VBN = 0 V, IA = 30 mA V+ = 4.5 V On Resistance RON V+ = 3.0 V V+ = 2.3 V V+ = 1.65 V On Resistance Flatness RFLAT 0 < VBN < V+ VBN = 2.3 V, IA = - 30 mA ΔRON 0.25 V+ Full Unit V 0.3 V+ Full 6 7 Full 6 12 15 Full 9 Full 8 9 VBN = 3.0 V, IA = - 24 mA Full 12 20 VBN = 0 V, IA = 8 mA Full 9 12 VBN = 2.3 V, IA = - 8 mA Full 13 30 VBN = 0 V, IA = 4 mA Full 12 20 VBN = 1.8 V, IA = - 4 mA Full 18 50 Ω V+ = 4.5 V, IA = - 30 mA Room 6 0.1 - 1.0 0.1 - 1.0 0.1 - 1.0 µA V+ = 3.0 V, IA = - 24 mA Room 12 V+ = 2.3 V, IA = - 8 mA Room 22 Room 90 V+ = 4.5 V, VBN = 3.15 V, IA = - 30 mA Room 0.32 V+ = 3.0 V, VBN = 2.1 V, IA = - 24 mA Room 0.31 V+ = 2.3 V, VBN = 1.6 V, IA = - 8 mA Room 0.30 V+ = 1.65 V, VBN = 1.15 V, IA = - 4 mA Room Room Full Room Full Room Full V+ = 5.5 V, VA = 5.5 V Off Stage Switch Leakage IBN(off) V+ = 5.5 V, VA/VB = 0 V/5.5 V On State Switch Leakage IBN(on) V+ = 5.5 V, VA/VB = 0 V/5.5 V www.vishay.com 2 Max.b VBN = 0 V, IA = 24 mA IS Input Leakage Current Typ.c VBN = 4.5 V, IA = - 30 mA V+ = 1.65 V, IA = - 4 mA On Resistance Matching Between Channels Limits - 40 °C to 85 °C 0.29 - 0.1 - 1.0 - 0.1 - 1.0 - 0.1 - 1.0 Document Number: 72648 S09-0294-Rev. D, 23-Feb-09 DG3157 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter Power Supply Power Supply Range Symbol V+ = 3.0 V, VS = 0.25 V to 0.7 V+e V+ Quiescent Supply Current I+ V+ = 5.5 V, VA = VB = V+ or GND Limits - 40 °C to 85 °C Temp.a Min.b Full Room Full 1.65 Typ.c Max.b Unit 5.5 1 10 V µA AC Electrical Characteristice Prop Delay Timef tPHL/tPLH V+ = 1.65 to 1.95 V Full V+ = 2.3 to 2.7 V Full 1.2 V+ = 3.0 to 3.6 V Full 0.8 V+ = 4.5 to 5.5 V 0.3 10.2 10.4 5.9 6.2 4.1 4.5 2.6 2.9 10.2 10.4 5.9 6.2 4.1 4.5 2.6 2.9 V+ = 1.65 to 1.95 V Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Full 0.5 V+ = 2.3 to 2.7 V Full 0.5 V+ = 3.0 to 3.65 Full 0.5 Full 0.5 VA = 0 V V+ = 1.65 to 1.95 V Output Enable Timef tPZL/tPZH VLOAD = 2 x V+ for tPZL VLOAD = 0 V for tPZH V+ = 2.3 to 2.7 V V+ = 3.0 to 3.6 V V+ = 4.5 to 5.5 V V+ = 1.65 to 1.95 V Output Disable Timef tPLZ/tPHZ VLOAD = 2 x V+ for tPLZ VLOAD = 0 V for tPHZ V+ = 2.3 to 2.7 V V+ = 3.0 to 3.6 V V+ = 4.5 to 5.5 V Break-Before-Make Timed Charge Injectiond tBBM V+ = 4.5 to 5.5 V CL = 0.1 nF, VGEN = 0 V V+ = 5 V RGEN = 0 Ω V+ = 3.3 V Room 7 Room 3 RL = 50 Ω, f = 10 MHz Room - 57.6 Room - 58.7 BW RL = 50 Ω Room > 250 CIN V+ = 0 V Room 4.9 Room < 6.5 Room < 18.5 Q ns pC Analog Switch Characteristics Off Isolationd Crosstalk OIRR d XTALK - 3 db Bandwidthd Capacitance Control Pin Capacitanced d B Port Off Capacitance A Port Capacitance When CIO-B CIO-A(on) V+ = 5 V dB MHz pF Switch Enabled Notes: a. Room = 25 °C, Full = as determined by the operating suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for design aid only, not guaranteed nor subject to production testing. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 72648 S09-0294-Rev. D, 23-Feb-09 www.vishay.com 3 DG3157 Vishay Siliconix LOGIC DIAGRAM Positive Logic B1 S A B0 Figure 1. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 40 RON – On Resistance (Ω) 35 30 V+ = 1.65 V, IS = 4 mA 25 20 V+ = 2.3 V, IS = 8 mA V+ = 3.0 V, IS = 24 mA 15 10 V+ = 4.5 V, IS = 30 mA 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VA (V) RON vs. VA vs. V+ www.vishay.com 4 Document Number: 72648 S09-0294-Rev. D, 23-Feb-09 DG3157 Vishay Siliconix AC LOADING AND WAVEFORMS VLD RL 500 Ω SW Open From Output Under Test TEST SW tPLH/tPHL Open GND RL 500 Ω CL 50 pF tPLZ/tPZL VLD tPHZ/tPZH GND Load Circuit Figure 2. AC Test Circuit tf = 2.5 ns tr = 2.5 ns 3.0 V 90 % Switch Input tr = 2.5 ns tf = 2.5 ns 90 % 1.5 V 90 % Logic Input 1.5 V 1.5 V 1.5 V 10 % 10 % 10 % GND tPLZ VLD 2 tPHL tPLH VOH Output 10 % tPZL GND tw 3.0 V 90 % 1.5 V 1.5 V Output VOL + 0.3 V Waveform 1 SW at V LD 1.5 V VOL tPZH tPHZ VOH VOL VOH 0.3 V Output Waveform 2 SW at GND Propagation Delay T imes 1.5 V 0V Enable and Disable T ime-Low- and High-Level Enabling Figure 3. AC Waveforms Notes: • CL includes probe and jig capacitance. • Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. • Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. • All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. • The outputs are measured one at a time with one transition per measurement. • tPLZ and tPHZ are the same as tdis. • tPZL and tPZH are the same as tdis. • tPLH and tPHL are the same as tdis. • VLD = 2 V+. Document Number: 72648 S09-0294-Rev. D, 23-Feb-09 www.vishay.com 5 DG3157 Vishay Siliconix TEST CIRCUITS V+ Logic Input V+ B1 B0 A B1 VSH tr < 5 ns tf < 5 ns VSL VO B0 RL 50 Ω S CL 35 pF VB = VB 0 1 VO GND 90 % Switch 0V Output tD tD CL (includes fixture and stray capacitance) Figure 4. Break-Before-Make Interval V+ V+ Rgen OUT BX VA A VOUT + S Vgen VS CL = 1 nF VIN = 0 – V+ On On Off GND Q= OUT x CL IN depends on switch configuration: input polarity determined by sense of switch. Figure 5. Charge Injection V+ V+ 10 nF 10 nF V+ V+ BX S COM 0 V, 2.4 V A Meter A S 0 V, 2.4 V RL GND BX HP4192A Impedance Analyzer or Equivalent GND Analyzer f = 1 MHz VA Off Isolation = 20 log V Bx Figure 6. Off-Isolation Figure 7. Channel Off/On Capacitance Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72648. www.vishay.com 6 Document Number: 72648 S09-0294-Rev. D, 23-Feb-09 Package Information Vishay Siliconix SCĆ70: 6ĆLEADS MILLIMETERS 6 5 Dim A A1 A2 b c D E E1 e e1 L 4 E1 E 1 2 3 -B- e b e1 D -Ac A2 A L A1 Document Number: 71154 06-Jul-01 INCHES Min Nom Max Min Nom Max 0.90 – 1.10 0.035 – 0.043 – – 0.10 – – 0.004 0.80 – 1.00 0.031 – 0.039 0.15 – 0.30 0.006 – 0.012 0.10 – 0.25 0.004 – 0.010 1.80 2.00 2.20 0.071 0.079 0.087 1.80 2.10 2.40 0.071 0.083 0.094 1.15 1.25 1.35 0.045 0.049 0.053 0.65BSC 0.026BSC 1.20 1.30 1.40 0.047 0.051 0.055 0.10 0.20 0.30 0.004 0.008 0.012 7_Nom 7_Nom ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5550 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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