DG528, DG529
Vishay Siliconix
Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers
DESCRIPTION
FEATURES
The DG528 is an 8-channel single-ended analog multiplexer
• Low RDS(on): 270
designed to connect one of eight inputs to a common output
• 44 V Power Supply Rating
as determined by a 3-bit binary address (A0, A1, A2). DG529,
• On-Board Address Latches
a 4-channel dual analog multiplexer, is designed to connect
• Break-Before-Make
one of four differential inputs to a common differential output
• Low Leakage - ID(on): 30 pA
as determined by its 2-bit binary address (A0, A1) logic.
BENEFITS
These analog multiplexers have on-chip address and control
• Improved System Accuracy
latches to simplify design in microprocessor based applica-
• Microporcessor Bus Compatible
tions. Break-before-make switching action protects against
• Easily Interfaced
momentary shorting of the input signals. The DG528/529 are
• Reduced Crosstalk
built on the improved PLUS-40 CMOS process. A buried
APPLICATIONS
layer prevents latchup.
• Data Acquisition Systems
The on chip TTL-compatible address latches simplify digital
• Automatic Test Equipment
interface design and reduce board space in data acquisition
• Avionics and Military Systems
systems, process controls, avionics, and ATE.
• Medical Instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
S2
S3
S4
D
3
Latches
16
4
Decoders/Drivers
15
14
5
6
13
7
12
8
11
9
1
0
A2
GND
V+
S5
RS
3
2
1
20 19
A1
NC
A1
WR
17
A0
2
RS
4
Latches
S8
A0
V±
5
Decoders/Drivers
18 A2
17 GND
S1
6
16 V+
S2
7
15 S5
S3
8
14 S6
VS1a
S2a
S3a
S6
S7
WR
EN
EN
9
10 11 12 13
S7
S1
18
S8
V-
1
NC
EN
DG529
Dual-In-Line
D
A0
DG528
PLCC
S4
WR
DG528
Dual-In-Line
S4a
Da
1
18
2
17
3
Latches
16
4
Decoders/Drivers
15
5
14
6
13
7
12
8
11
9
10
RS
A1
GND
V+
S1b
S2b
S3b
S4b
Db
Top View
Top View
Document Number: 70068
S11-1029–Rev. D, 23-May-11
Top View
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DG528, DG529
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE - DG528
TRUTH TABLE - DG529
8-Channel Single-Ended Multiplexer
A2
A1
A0
EN
WR
Differential 4-Channel Multiplexer
RS
On Switch
Latching
X
EN
WR
RS
On Switch
1
Maintains previous
switch condition
0
None (latches cleared)
Latching
X
X
X
X
X
X
1
Maintains previous
switch condition
0
None (latches cleared)
Reset
X
A0
X
X
Reset
X
Transparent Operation
X
X
X
Transparent Operation
X
X
X
0
0
1
None
X
0
0
1
None
0
0
0
1
0
1
1
0
1
0
1
1
0
0
1
1
0
1
2
1
1
0
1
2
0
1
0
1
0
1
3
0
1
0
1
3
0
1
1
1
0
1
4
1
1
0
1
4
1
0
0
1
0
1
5
1
0
1
1
0
1
6
1
1
0
1
0
1
7
1
1
1
1
0
1
8
ORDERING INFORMATION - DG528
Temp Range
0 °C to 70 °C
Package
18-pin Plastic DIP
20-pin PLCC
- 25 °C to 85 °C
- 55 °C to 125 °C
18-pin Cer DIP
Part Number
DG528CJ
Logic "0" = VAL 0.8 V
Logic "1" = VAH 2.4 V
X = Don’t Care
ORDERING INFORMATION - DG529
Temp Range
Package
0 °C to 70 °C
18-pin Plastic DIP
DG528DN
- 25 °C to 85 °C
DG528BK
- 55 °C to 125 °C
Part Number
18-pin Cer DIP
DG529CJ
DG529BK
DG529AK/883
DG528AK
DG528AK/883
5962-8768901VA
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
V+
Voltages Referenced to V-
Limit
GND
25
(V-) - 2 to (V+) + 2
or 30 mA, whichever occurs first
30
Digital Inputsa, VS, VD
Current (Any Terminal Except S or D)
Continuous Current, S or D
20
Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max)
40
Storage Temperature
- 65 to 150
(CJ, DN Suffix)
- 65 to 125
Power Dissipation (Package)
d
V
mA
(AK, BK Suffix)
18-pin Plastic DIPc
b
Unit
44
°C
470
18-pin CerDIP
900
e
800
mW
20-pin PLCC
Notes:
a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/°C above 75 °C.
d. Derate 12 mW/°C above 75 °C.
e. Derate 10 mW/°C above 75 °C.
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Document Number: 70068
S11-1029–Rev. D, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG528, DG529
Vishay Siliconix
SPECIFICATIONSa
A Suffix
B, C, D Suffix
- 55 °C to 125 °C - 40 °C to 85 °C
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V, WR = 0,
RS = 2.4 V, VIN = 2.4 V, 0.8 µFf
Temp.b
Typ.c
RDS(on)
VD = ± 10 V, IS = - 200 µA
Full
Room
Full
270
Min.d
Max.d
Min.d
Max.d
Unit
- 15
15
400
500
- 15
15
450
550
V
Parameter
Analog Switch
Symbol
Analog Signal Rangee
Drain-Source
On-Resistance
Greatest Change in RDS(on)
Between Channelsf
VANALOG
RDS(on)
- 10 V < VS < 10 V
Room
6
Source Off Leakage Current
IS(off)
VEN = 0 V, VD = ± 10 V
VS = ± 10 V
Room
Full
± 005
-1
- 50
1
50
-5
- 50
5
50
ID(off)
Room
Full
Room
Full
Room
Full
Room
Full
± 0.015
Drain Off Leakage Current
- 10
- 200
- 10
- 100
- 10
- 200
- 10
- 100
10
200
10
100
10
200
10
100
- 20
- 200
- 20
- 100
- 20
- 200
- 20
- 100
20
200
20
100
20
200
20
100
- 0.002
VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V
Room
Hot
Room
Hot
Room
Hot
See Figure 5
See Figure 4
See Figure 6 and 7
See Figure 6 and 8
VS = 0 V, Ry = 0 CL = 10 F
Room
Room
Room
Room
Room
0.6
0.2
1
0.4
4
VEN = 0 V, RL = 1 kCL = 15 pF
VS = 7 VRMS, f = 500 kHz
Room
68
Room
Room
Room
2.5
5
25
Room
12
Drain On Leakage Current
ID(on)
VEN = 0 V, VD = ± 10 V
VS = ± 10 V
VS = VD = ± 10 V
VEN = 2.4 V
DG528
DG529
DG528
DG529
± 0.008
± 0.03
± 0.015
%
nA
Digital Control
VA = 2.4 V
Logic Input Current
IAH
VA = 15 V
Input Voltage High
Logic Input Current
Input Voltage Low
IAL
- 10
- 30
0.006
- 0.002
- 10
- 30
10
30
- 10
- 30
10
30
µA
- 10
- 30
Dynamic Characteristics
Transition Time
Break-Before-Make Interval
EN and WR Turn-On Time
EN and WR Turn-Off Time
Charge Injection
tTRANS
tOPEN
tON(EN,WR)
tOFF(EN,RS)
Q
Off Isolation
OIRR
Logic Imput Capacitance
Source Off Capacitance
Cin
CS(off)
Drain Off Capacitance
CD(off)
Minimum Input Timing Requirements
tW
Write Pulse Width
tS
AX, EN Data Set Up time
tH
AX, EN Data Hold Time
Reset Pulse Width
tRS
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
f = 1 MHz
VEN = 0 V, VD = 0 V, f = 140 kHz
DG528
VEN = 0 V, VD = 0 V
f = 140 kHz
DG529
VS = 5 V, See Figure 3
VEN = VA = 0 V
1
µs
1.5
1
pC
dB
pF
Full
Full
Full
Full
300
180
30
500
Room
Room
- 1.5
300
180
30
500
2.5
ns
2.5
- 1.5
mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 70068
S11-1029–Rev. D, 23-May-11
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DG528, DG529
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless noted)
TA = 25 °C
ID(on)
0
400
IS(off)
± 7.5 V
I S, I D (pA)
RDS(on) – Drain-Source On-Resistance (Ω)
500
300
± 10 V
ID(off)
- 40
± 15 V
200
- 20
± 15 V Supplies
TA = 25
± 20 V
100
- 20
- 15
- 10
-5
0
5
10
15
- 60
20
- 15
VD – Drain Voltage (V)
- 10
-5
0
5
10
15
VANALOG – Analog Voltage (V)
RDS(on) vs. VD and Power Supply
Leakage Currents vs. Analog Voltage
2.5
TA = 25 °C
4
2.0
I+, I- (mA)
V T (V)
3
1.5
1.0
I+
2
1
0.5
I-
0
0
0
±5
± 10
± 15
V+, V- Positive and Negative Supplies (V)
Input Switching Threshold vs.
V+ and V- Supply Voltages
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± 20
1k
10 k
100 k
1M
Toggle Frequency (Hz)
Supply Currents vs. Toggle Frequency
Document Number: 70068
S11-1029–Rev. D, 23-May-11
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DG528, DG529
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
GND
S1
VREF
V+
DO QO
EN
Sn
V-
V+
V+
V-
V-
Dn Qn
AX
V-
V+
Latches
V+
VWR
Level
Shift
Decode
V+
VV+
D
V+
V-
CLK
RESET
RS
V-
Figure 1.
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V
logic interface with input protection circuitry followed by a
latch, level shifter, decoder and finally the switch constructed
with parallel n- and p-channel MOSFETs (see Figure 1).
The logic interface circuit compares the TTL input signal
against a TTL threshold reference voltage. The output of the
comparator feeds the data input of a D type latch. The level
sensitive D latch continuously places the DX input signal on
the QX output when the WR input is low, resulting in transparent latch operation. As soon as WR returns high, the latches
hold the data last present on the DX input, subject to the minimum input timing requirements.
Following the latches the QX signals are level shifted and
decoded to provide proper drive levels for the CMOS
switches. This level shifting insures full on/off switch operation
for any analog signal present between the V+ and V- supply
rails.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard-wired to the logic supply or to V+ if
one of the channels will always be used (except during a reset)
or it can be tied to address decoding circuitry for memory
mapped operation. The RS pin is used as a master reset. All
latches are cleared regardless of the state of any other latch
or control line. The WR pin is used to transfer the state of the
address control lines to their latches, except during a reset or
when EN is low (see Truth Tables).
3V
3V
WR
RS
50 %
50 %
0
0
tRS
tW
tS
3V
A0, A1, (A2)
EN
tOFF (RS)
tH
Switch
Output
80 %
VO
80 %
80 %
0
0
Figure 2.
Document Number: 70068
S11-1029–Rev. D, 23-May-11
Figure 3.
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DG528, DG529
Vishay Siliconix
TEST CIRCUITS
+ 15 V
+ 2.4 V
V+
RS
EN
Logic
Input
All S and Da
+5V
tr < 20 ns
tf < 20 ns
3V
50 %
0V
DG528
DG529
A0, A1, (A2)
GND
Db, D
WR
50 Ω
VO
VS
V300 Ω
- 15 V
35 pF
80 %
Switch
Output
VO
tOPEN
0V
Figure 4. Break-Before-Make
+ 15 V
RS
+ 2.4 V
V+
S1
± 10 V
EN
S2 - S 7
A0
A1
A2
GND
DG528
WR
S8
± 10 V
VO
D
V-
50 Ω
300 Ω
Logic
Input
tr < 20 ns
tf < 20 ns
3V
50 %
0V
35 pF
- 15 V
VS1
90 %
Switch
Output
+ 15 V
RS
+ 2.4 V
EN
A0
A1
GND
VO
0V
V+
S1b
10 %
± 10 V
VS8
S1a - S 4a, Da
S2b and S3b
S4b
DG529
WR
V-
Db
50 Ω
300 Ω
tTRANS
S1 ON
tTRANS
S8 ON
± 10 V
VO
35 pF
- 15 V
Figure 5. Transition Time
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Document Number: 70068
S11-1029–Rev. D, 23-May-11
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DG528, DG529
Vishay Siliconix
TEST CIRCUITS
+ 15 V
V+
+ 2.4 V
RS
EN
S1
-5V
DG528
S2 - S 8
A0
A1
A2
WR
GND
VO
D
V-
50 Ω
300 Ω
35 pF
Logic
Input
tr < 20 ns
tf < 20 ns
3V
50 %
0V
- 15 V
tON(EN)
tOFF(EN)
0V
+ 15 V
Switch
Output
V+
+ 2.4 V
RS
S1b
EN
-5V
VO
DG529
90 %
VO
S1a - S 4a, Da
S2b - S 4b
A0
A1
GND
Db
WR
VO
V-
50 Ω
300 Ω
35 pF
- 15 V
Figure 6. Enable tON/tOFF Time
+ 15 V
+ 2.4 V
EN
A0, A1, (A2)
V+
S1 or S1b
+5V
3 V
WR
Remaining
Switches
RS
VO
DG528
DG529
WR
GND
50 %
0 V
Db, D
VO
V300 W
tON(WR)
Switch
Output
35 pF
20 %
0V
- 15 V
Figure 7. Write Turn-On Time tON(WR)
Document Number: 70068
S11-1029–Rev. D, 23-May-11
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DG528, DG529
Vishay Siliconix
TEST CIRCUITS
+ 15 V
+ 2.4 V
EN
A0, A1, (A2)
V+
S1 or S1b
3 V
+5V
RS
50 %
Remaining
Switches
RS
GND
DG528
DG529
WR
0 V
tOFF(RS)
VO
Db, D
80 %
VO
Switch
Output
V300 W
35 pF
0V
- 15 V
Figure 8. Reset Turn-Off Time tOFF(RS)
+ 15 V
± 15 V
Analog
Inputs
V+
S1
A0, A1, A2 ,
EN
Data Bus
Processor
System
Bus
DG528
RS
RESET
+5V
WRITE
WR
S8
Address
Bus
Address
Decoder
D
Analog
Output
V- 15 V
Figure 9. Bus Interface
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Document Number: 70068
S11-1029–Rev. D, 23-May-11
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DG528, DG529
Vishay General Semiconductor
APPLICATION HINTSa
V+
Positive Supply Voltage
(V)
VNegative Supply Voltage
(V)
20
- 20
- 15
- 8 (min)
15b
8c
VIN
Logic Input Voltage VINH(min)/VINL(max)
(V)
2.4/0.8
2.4/0.8
2.4/0.8
VS or VD
Analog Voltage Range
(V)
± 20
± 15
±8
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
b. Electrical Parameter Chart based on V+ = 15 V, V- = - 15 V, VR = GND.
c. Operation below ± 8 V is not recommended.
The DG528/DG529 minimize the amount of interface hardware between a microprocessor system bus and the analog
system being controlled or measured. The internal TTL compatible latches give these multiplexers write-only memory, that
is, they can be programmed to stay in a particular switch state
(e.g., switch 1 on) until the microprocessor determines it is
necessary to turn different switches on or turn all switches off
(see Figure 9).
The input latches become transparent when WR is held low;
therefore, these multiplexers operate by direct command of
the coded switch state on A2, A1, A0. In this mode the DG528
is identical to the popular DG508A. The same is true of the
DG529 versus the popular DG509A.
During system power-up, RS would be low, maintaining all
eight switches in the off state. After RS returned high the
DG528 maintains all switches in the off state. When the system program performs a write operation to the address assigned to the DG528, the address decoder provides a CS
active low signal which is gated with the WRITE (WR) control
signal. At this time the data on the DATA BUS (that will determine which switch to close) is stabilizing. When the WR signal
returns to the high state, (positive edge) the input latches of
the DG528 save the data from the DATA BUS. The coded information in the A0, A1, A2 and EN latches is decoded and the
appropriate switch is turned on.
The EN latch allows all switches to be turned off under program control. This becomes useful when two or more DG528s
are cascaded to build 16-line and larger multiplexers.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70068.
Document Number: 70068
S11-1029–Rev. D, 23-May-11
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Package Information
Vishay Siliconix
PLCC: 2OĆLEAD
D–SQUARE
A2
MILLIMETERS
D1–SQUARE
B1
B
e1
D2
Document Number: 71263
02-Jul-01
INCHES
Min
Max
Min
Max
4.20
4.57
0.165
0.180
2.29
3.04
0.090
0.120
0.51
–
0.020
–
0.331
0.553
0.013
0.021
0.661
0.812
0.026
0.032
9.78
10.03
0.385
0.395
8.890
9.042
0.350
0.356
7.37
8.38
0.290
0.330
1.27 BSC
0.050 BSC
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5306
A1
A
Dim
A
A1
A2
B
B1
D
D1
D2
e1
0.101 mm
0.004″
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
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or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
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Revision: 08-Feb-17
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