DG534ADJ

DG534A/538A Vishay Siliconix 4-/8-Channel Wideband Video Multiplexers FEATURES BENEFITS APPLICATIONS D Wide Bandwidth: 500 MHz D Very Low Crosstalk: –97 dB @ 5 MHz D On-Board TTL-Compatible Latches with Readback D Optional Negative Supply D Low rDS(on): 45
D Single-Ended or Differential Operation D Latch-up Proof D D D D D D D D Wideband Signal Routing and Multiplexing D Video Switchers D ATE Systems D Infrared Imaging D Ultrasound Imaging Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing High-Speed Readback Allows Bipolar Signal Swings Reduced Insertion Loss Allows Differential Signal Switching DESCRIPTION The DG534A is a digitally selectable 4-channel or dual 2-channel multiplexer. The DG538A is an 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing. The DG534A/DG538A are built on a D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a “T” configuration to achieve extremely high levels of off isolation. Crosstalk is reduced to –97 dB at 5 MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up. For more information refer to Vishay Siliconix applications note AN502. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG534ADJ DG534ADN Dual-In-Line 20 NC DA GND DB DA 2 19 DB 3 2 1 20 19 V+ 3 18 V– SA1 4 17 SB1 GND 5 16 GND SA2 6 15 SB2 4/2 7 14 VL RS 8 13 I/O WR 9 12 EN A1 10 11 A0 V– 1 V+ PLCC GND SA1 4 18 SB1 GND 5 17 GND SA2 6 16 SB2 4/2 7 15 VL RS 8 14 NC Latch/Drivers Latches/Drivers Top View Document Number: 70069 S-05734—Rev. G, 29-Jan-02 I/O A0 EN 10 11 12 13 A1 WR 9 Top View www.vishay.com 1 DG534A/538A Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG538ADJ Dual-In-Line DG538ADN V+ DA GND V+ 3 26 SB1 4 3 2 SA1 4 25 GND GND 5 24 SB2 GND 5 25 GND SA2 6 23 GND SA2 6 24 SB2 GND 7 22 SB3 GND 7 23 GND SA3 8 22 SB3 GND 9 21 GND SA4 10 20 SB4 8/4 11 19 VL SA3 8 21 GND GND 9 20 SB4 S B1 27 V– V– 28 DB 2 DB 1 DA S A1 PLCC GND 1 28 27 26 17 EN 12 13 14 15 16 17 18 Latch/Drivers 16 A0 A2 14 RS RS 12 WR 13 15 A1 I/O Latch/Drivers EN 18 I/O A1 A0 19 VL 8/4 11 WR A2 SA4 10 Top View Top View TRUTH TABLE Ċ DG534A A1 A0 EN X X X X 1 1 Maintains previous state X X X X X 0 X None (latches cleared) X X X 0 0 1 X None 0 0 0 1 0 1 0 SA1 0 0 1 1 0 1 0 SA2 0 1 0 1 0 1 0 SB1 0 1 1 1 0 1 0 SB2 0 X 0 1 0 1 1 SA1 and SB1 0 X 1 1 0 1 1 SA2 and SB2 1 1 Note c 1 Note b WR RS 4/2a I/O On Switch DA and DB may be connected externally Latches Transparent Logic “0” = VAL v 0.8 V Logic “1” = VAH w 2.4 V X = Don’t Care www.vishay.com 2 Document Number: 70069 S-05734—Rev. G, 29-Jan-02 DG534A/538A Vishay Siliconix TRUTH TABLE Ċ DG538A A2 A1 A0 EN X X X X X 1 1 Maintains previous state X X X X X X 0 X None (latches cleared) X X X X 0 0 1 X None 0 0 0 0 1 0 1 0 SA1 0 0 0 1 1 0 1 0 SA2 0 0 1 0 1 0 1 0 SA3 0 0 1 1 1 0 1 0 SA4 0 1 0 0 1 0 1 0 SB1 0 1 0 1 1 0 1 0 SB2 0 1 1 0 1 0 1 0 SB3 0 1 1 1 1 0 1 0 SB4 0 X 0 0 1 0 1 1 SA1 and SB1 0 X 0 1 1 0 1 1 SA2 and SB2 0 X 1 0 1 0 1 1 SA3 and SB3 0 X 1 1 1 0 1 1 SA4 and SB4 1 1 Note c 1 WR Note b RS 8/4a I/O On Switch DA and DB should be connected externally Latches Transparent Logic “0” = VAL v 0.8 V Logic “1” = VAH w 2 V X = Don’t Care Notes: a. Connect DA and DB together externally for single-ended operation. b. With I/O high, An and EN pins become outputs and reflect latch contents. See timing diagrams for more detail. c. 8/4 can be either “1” or “0” but should not change during these operations. ORDERING INFORMATION Temperature Range Package Part Number DG534A –40 to 85_C _ –55 to 125_C 20-Pin Plastic DIP DG534ADJ 20-Pin PLCC DG534ADN 20-Pin Sidebraze DG534AAP/883, 5962-906021MRC 28-Pin Plastic DIP DG538ADJ 28-Pin PLCC DG538ADN DG538A –40 to 85_C _ –55 to 125_C Document Number: 70069 S-05734—Rev. G, 29-Jan-02 28-Pin Sidebraze DG538AAP/883, 5962-8976001MXA www.vishay.com 3 DG534A/538A Vishay Siliconix ABSOLUTE MAXIMUM RATINGS V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +21 V Storage Temperature V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +21 V V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to +0.3 V (A Suffix) . . . . . . . . . . . . . . . . . . . –65 to 150_C (D Suffix) . . . . . . . . . . . . . . . . . . . –65 to 125_C Power Dissipation (Package)a Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW PLCCc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Sidebrazed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to (V+) + 0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (VL) + 0.3 V or 20 mA, whichever occurs first Notes: a. All leads soldered or welded to PC board. b. Derate 8.3 mW/_C above 75_C. c. Derate 6 mW/_C above 75_C. d. Derate 16 mW/_C above 75_C. VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V–) + 14 V or 20 mA, whichever occurs first Current (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Current(S or D) Pulsed l ms 10% Duty . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Symbol V+ = 15 V, V– = –3 V, VL = 5 V WR = 0.8 V, RS, EN= 2 V VANALOG V– = –5 V Tempb Typc A Suffix D Suffix –55 to 125_C –40 to 85_C Mind Maxd Mind 8 –5 Maxd Unit 8 V Analog Switch Analog Signal Rangeg Drain-Source On-Resistance rDS(on) Full Room Full –5 45 90 120 90 120 9 9 rDS(on) IS = –10 mA, VS = 0 V VAIL = 0.8 V, VAIH = 2 V Sequence Each Switch On Source Off Leakage Current IS(off) VS = 8 V, VD = 0 V, EN = 0.8 V Room Full 0.05 –5 –50 5 50 –5 –50 5 50 Drain Off Leakage Current ID(off) VS = 0 V, VD = 8 V, EN = 0.8 V Room Full 0.1 –20 –500 20 500 –20 –100 20 100 Drain On Leakage Current ID(on) VS = VD = 8 V Room Full 0.1 –20 –1000 20 1000 –20 –200 20 200 Resistance Match Between Channels Room
nA Digital Control Input Voltage High VAIH Full Input Voltage Low VAIL Full Address Input Current IAI Address Output Current IAO 2 2 0.8 –1 –10 1 10 0.8 VAI = 0 V, or 2 V or 5 V Room Full –0.1 –1 –10 VAO = 2.7 V Room –21 VAO = 0.4 V Room 3.5 PLCC Room 28 40 40 DIP Room 31 45 45 PLCC Room 3 5 4 DIP Room 4 PLCC Room 6 DIP Room 8 Room Full 160 Room Full 80 –2.5 2.5 1 10 V A –2.5 mA 2.5 Dynamic Characteristics On State Input Capacitanceg Off State Input Capacitanceg CS(on) See Figure 11 CS(off) See Figure 12 Off State Output Capacitanceg CD(off) Transition Time tTRANS Break-Before-Make Interval tOPEN See Figure 4 5 10 8 300 500 300 500 10 50 25 50 25 EN, WR Turn On Time tON See Figure 2 and 3 Room Full 150 300 500 300 500 EN, Turn Off Time tOFF See Figure 2 Room Full 105 175 300 175 300 Qi See Figure 5 Room –70 Charge Injection www.vishay.com 4 pF ns pC Document Number: 70069 S-05734—Rev. G, 29-Jan-02 DG534A/538A Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Symbol V+ = 15 V, V– = –3 V, VL = 5 V WR = 0.8 V, RS, EN= 2 V Tempb Typc PLCC Room –75 DIP Room –65 PLCC Room –97 DIP Room –87 PLCC Room –80 DIP Room –70 PLCC Room –77 DIP Room –72 PLCC Room –77 DIP Room –72 RIN = 10
, RL = 10 k
f = 5 MHz, See Figure 10 Room –84 RIN = RL = 75
f = 5 MHz, See Figure 10 Room –84 RL = 50
, See Figure 6 Room 500 Room Full 0.6 Room Full 0.6 A Suffix D Suffix –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit Dynamic Characteristics (Cont’d) Chip Disabled Crosstalkf Adjacent Input Crosstalkf XTALK(CD) XTALK(AI) RL = 75
 f = 5 MHz EN = 0.8 V See Figure 8 RIN = 10
RL = 10 k
f = 5 MHz SeeFigure 9 RIN = 75
, RL = 75
f = 5 MHz See Figure 7 All Hostile Crosstalk XTALK(AH) RIN = 10
RL = 10 k
f = 5 MHz See Figure 7 RIN = 75
, RL = 75
f = 5 MHz See Figure 7 Differential Crosstalk Bandwidth XTALK(DIFF) BW dB MHz Power Supplies Positive Supply Current Negative Supply Current Functional Check of Maximum Operating Supply Voltage Range Logic Supply Current I+ I– Any One Channel Selected with Address Inputs at GND or 5 V V+ to V– 2 5 –1.8 –2 2 5 mA –1.8 –2 Full 10 21 10 Full –5.5 0 –5.5 0 V+ to GND Full 10 21 10 21 IL Full 150 tRW Room Full –22 tMPW Room Full 60 tDW Room Full 20 –20 25 V– to GND Functional Test Only 500 21 500 V A Timing Reset to Write WR, RS Minimum Pulse Width A0, A1, EN Data Valid to Strobe See Figure 1 A0, A1, EN Data Valid after Strobe tWD Room Full Address Bus Tri-Statee tAZ Room Address Bus Output tAO Room 95 Address Bus Input tAI Room 110 50 50 200 200 100 100 50 50 ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Defined by system bus requirements. f. Each individual pin shown as GND must be grounded. g. Guaranteed by design, not subject to production test. Document Number: 70069 S-05734—Rev. G, 29-Jan-02 www.vishay.com 5 DG534A/538A Vishay Siliconix CONTROL CIRCUITRY SA1 SA2 SA3 SA4 DA DB SA1 – SA4 SB1 – SB4 SB1 SB2 SB3 SB4 V– DA, DB V– Decode A0 EN A0 A1 A1 A2 A2 V– Latch VREF 8/4 I/O Decode Tri-State Buffer VL V– VREF VREF * V+ I/O V– * EN VREF VREF VREF VREF VREF VL A0 A1 A2 RS WR VL *Typical all Readback (AX, EN) pins www.vishay.com 6 Document Number: 70069 S-05734—Rev. G, 29-Jan-02 DG534A/538A Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Supply Currents vs. Temperature Leakage vs. Temperature 1 A 1.4 1.0 V+ = 15 V V– = –3 V VL = 5 V I+ 100 nA 0.6 10 nA IL Leakage Current (mA) V+ = 15 V V– = –3 V VL = 5 V 0.2 –0.2 ID(on) 1 nA ID(off) 100 pA I– –0.6 IS(off) 10 pA –1.0 1 pA –1.4 –40 –20 0 20 40 60 80 100 120 –40 –20 0 Temperature (_C) r DS(on)– Drain-Source On-Resistance (
) (Source) Current (mA) 80 100 120 70 VAO = 0.4 V 0 –8 –16 VAO = 2.7 V (Sink) V+ = 15 V V– = –3 V VL = 5 V –24 –32 VD = 0 V VL = 5 V IS = –10 mA V+ = 10 V 60 V+ = 12 V 50 V+ = 15 V 40 30 –40 –20 0 20 40 60 80 100 –6 120 –5 –4 –3 –2 –1 0 V– – Negative Supply (V) Temperature (_C) rDS(on) vs. VD and Temperature Adjacent Input Crosstalk vs. Frequency 200 –100 V+ = 15 V V– = –3 V VL = 5 V IS = – 10 mA V+ = 15 V V– = –3 V VL = 5 V RIN = 10
RL = 10 k
DIP –80 140 X TALK(AI) (dB) r DS(on)– Drain-Source On-Resistance (
) 60 rDS(on) vs. V–, V+ Address, EN Output Current vs. Temperature 160 40 Temperature (_C) 8 180 20 25_C 120 100 125_C 80 PLCC –60 –40 60 40 –55_C –20 20 –2 0 2 4 6 VD – Drain Voltage (V) Document Number: 70069 S-05734—Rev. G, 29-Jan-02 8 10 1 10 100 f – Frequency (MHz) www.vishay.com 7 DG534A/538A Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Adjacent Input Crosstalk vs. Frequency Adjacent Input Crosstalk vs. Frequency –100 –100 V+ = 15 V V– = –3 V VL = 5 V RIN = RL = 75
PLCC –60 PLCC –80 X TALK(AI) (dB) X TALK(AI) (dB) –80 DIP –40 DIP –60 V+ = 15 V V– = –3 V VL = 5 V RIN = 10
RL = 10 k
–40 –20 –20 1 10 100 1 10 f – Frequency (MHz) f – Frequency (MHz) All Hostile Crosstalk vs. Frequency –100 –80 –80 PLCC X TALK(AH) (dB) X TALK(AH) (dB) All Hostile Crosstalk vs. Frequency –100 DIP –60 V+ = 15 V V– = –3 V VL = 5 V RIN = 10
RL = 10 k
–40 100 PLCC DIP –60 V+ = 15 V V– = –3 V VL = 5 V RIN = RL = 75
–40 –20 –20 1 10 1 100 10 f – Frequency (MHz) 100 f – Frequency (MHz) Differential Crosstalk vs. Frequency Differential Crosstalk vs. Frequency –100 –100 –80 –80 PLCC –60 X TALK(DIFF) (dB) X TALK(DIFF) (dB) PLCC DIP V+ = 15 V V– = –3 V VL = 5 V RIN = 10
RL = 10 k
–40 V+ = 15 V V– = –3 V VL = 5 V RIN = 75
RL = 75
–40 –20 –20 1 10 f – Frequency (MHz) www.vishay.com 8 DIP –60 100 1 10 100 f – Frequency (MHz) Document Number: 70069 S-05734—Rev. G, 29-Jan-02 DG534A/538A Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Switching Times vs. Temperature Transition Time vs. Temperature 225 250 200 225 200 175 Time (ns) Time (ns) tON 150 tOFF 125 tTRANS 175 150 125 100 tBBM 100 75 75 50 –40 –20 0 20 40 60 80 100 120 –40 Temperature (_C) –20 0 20 40 60 80 100 120 Temperature (_C) OUTPUT TIMING REQUIREMENTS WR tMPW 3V 0V tWD tDW 3V A0, A1, A2, EN Don’t Care Write Data Don’t Care 0V Writing Data to Device WR 3V 0V 3V A0, A1, A2, EN Don’t Care New Data Don’t Care 0V RS 3V 0V tMPW tRW Delay Time Required after Reset before Write WR 3V 0V 3V A0, A1, A2, EN Driven Bus Hi Z Device Data* Out Hi Z Driven Bus 0V I/O 3V 0V Reading Data From Device tAZ tAO tAI FIGURE 1. Document Number: 70069 S-05734—Rev. G, 29-Jan-02 www.vishay.com 9 DG534A/538A Vishay Siliconix TEST CIRCUITS +15 V + 10 F Logic Input tr