DG540AP/883

DG540, DG541, DG542 Vishay Siliconix Wideband/Video “T” Switches DESCRIPTION FEATURES The DG540, DG541, DG542 are high performance monolithic wideband/video switches designed for switching RF, video and digital signals. By utilizing a "T" switch configuration on each channel, these devices achieve exceptionally low crosstalk and high off-isolation. The crosstalk and off-isolation of the DG540 are further improved by the introduction of extra GND pins between signal pins. To achieve TTL compatibility, low channel capacitances and fast switching times, the DG540 family is built on the Vishay Siliconix proprietary D/CMOS process. Each switch conducts equally well in both directions when on. • Halogen-free according to IEC 61249-2-21 Definition • Wide Bandwidth: 500 MHZ • Low Crosstalk: - 85 dB • High Off-Isolation: - 80 dB at 5 MHz • "T" Switch Configuration • TTL and CMOS Logic Compatible • Fast Switching - tON: 45 ns • Low RDS(on): 30  • Compliant to RoHS Directive 2002/95/EC BENEFITS • • • • • • • Flat Frequency Response High Color Fidelity Low Insertion Loss Improved System Performance Reduced Board Space Reduced Power Consumption Improved Data Throughput APPLICATIONS • • • • • • • • RF and Video Switching RGB Switching Local and Wide Area Networks Video Routing Fast Data Acquisition ATE Radar/FLR Systems Video Multiplexing FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG540 Dual-In-Line DG540 18 GND S1 4 17 S2 V- 5 16 V+ GND 6 15 GND S4 7 14 S3 GND 8 13 GND D4 9 12 D3 IN4 10 11 IN3 3 2 1 20 19 D2 3 IN 2 GND S1 4 18 GND V- 5 17 S2 GND 6 16 V+ S4 7 15 GND GND 8 14 S3 9 10 11 12 13 GND D2 IN 1 19 D3 2 IN3 D1 GND IN2 D4 20 IN4 1 D1 PLCC IN1 Top View Top View TRUTH TABLE Logic 0 1 Switch OFF ON Logic “0” 0.8 V Logic “1” 2 V Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG542 DG541 Dual-In-Line and SOIC Dual-In-Line and SOIC IN1 1 16 IN2 IN1 1 16 IN2 D1 2 15 D2 D1 2 15 D2 S1 3 14 S2 GND 3 14 GND V- 4 13 V+ S1 4 13 S2 GND 5 12 GND V- 5 12 V+ S4 6 11 S3 S4 6 11 S3 D4 7 10 D3 GND 7 10 GND IN4 8 9 IN3 D4 8 9 D3 Top View Top View TRUTH TABLE - DG541 TRUTH TABLE - DG542 Logic Switch Logic SW1, SW2 0 OFF 0 OFF ON 1 ON 1 ON OFF Logic "0" 0.8 V Logic "1" 2 V SW3, SW4 Logic "0" 0.8 V Logic "1" 2 V ORDERING INFORMATION Temp Range DG540 Package - 40 to 85 °C 20-Pin Plastic DIP 20-Pin PLCC - 55 to 125 °C 20-Pin Sidebraze Part Number DG540DJ-E3 DG540DN-E3 DG540AP DG540AP/883 DG541 - 40 to 85 °C 16-Pin Plastic DIP 16-Pin Narrow SOIC - 55 to 125 °C 16-Pin Sidebraze DG541DJ-E3 DG541DY-T1-E3 DG541AP DG541AP/883, 5962-9076401MEA DG542 - 40 to 85 °C 16-Pin Plastic DIP 16-Pin Narrow SOIC - 55 to 125 °C 16-Pin Sidebraze www.vishay.com 2 DG542DJ-E3 DG542DY-T1-E3 DG542AP DG542AP/883, 5962-91555201MEA Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Symbol Parameter Limit Unit - 0.3 to 21 V+ to VV+ to GND - 0.3 to 21 V- to GND - 19 to + 0.3 (V-) - 0.3 to (V+) + 0.3 or 20 mA, whichever occurs first (V-) - 0.3 to (V+) + 14 or 20 mA, whichever occurs first 20 Digital Inputs VS, VD Continuous Current (Any Terminal) 40 Current, S or D (Pulsed at 1 ms, 10 % duty cycle max) (AP Suffix) Storage Temperature (DJ, DN, DY Suffixes) - 65 to 150 20-Pin Plastic 470 20-Pin PLCC 800 DIPc 16-Pin Narrow Body mA °C - 65 to 125 16-Pin Plastic DIPb Power Dissipation (Package)a V 640 SOICd mW 800 d 900 16-, 20-Pin Sidebraze DIPe Notes: a. All leads welded or soldered to PC Board. b. Derate 6.5 mW/°C above 25 °C. c. Derate 7 mW/°C above 25 °C. d. Derate 10 mW/°C above 75 °C. e. Derate 12 mW/°C above 75 °C. SCHEMATIC DIAGRAM (typical channel) V+ GND VREF S IN + D V- Figure 1. Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix SPECIFICATIONSa A Suffix D Suffixes - 55 °C to 125 °C - 40 °C to 85 °C Test Conditions Unless Specified V+ = 15 V, V- = - 3 V Parameter Analog Switch Symbol VINH = 2 V, VINL = 0.8 Vf Temp.b Analog Signal Range Drain-Source On-Resistance RDS(on) Match VANALOG V- = - 5 V, V+ = 12 Full Room Full Room Room Full Room Full Room Full RDS(on) RDS(on) IS = - 10 mA, VD = 0 V Source Off Leakage Current IS(off) VS = 0 V, VD = 10 V Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Channel On Leakage Current ID(on) VS = V D = 0 V Typ.c Min.d Max.d Min.d Max.d Unit -5 5 60 100 6 10 500 10 500 10 1000 -5 5 60 75 6 10 100 10 100 10 100 V 30 2 - 0.05 - 0.05 - 0.05 - 10 - 500 - 10 - 500 - 10 - 1000 - 10 - 100 - 10 - 100 - 10 - 100  nA Digital Control Input Voltage High VINH Full Input Voltage Low VINL Full Room Full 0.05 2 -1 - 20 2 0.8 1 20 -1 - 20 0.8 1 20 IIN VIN = GND or V+ On State Input Capacitancee CS(on) VS = V D = 0 V Room 14 20 Off State Input Capacitancee CS(off) VS = 0 V Room 2 4 4 CD(off) VD = 0 V Room 2 4 4 BW RL = 50 , See Figure 5 Room Room Full Room Full Room Full Room Full 500 Input Current V µA Dynamic Characteristics Off State Output Bandwidth Capacitancee Turn-On Time Turn-Off Time tON tOFF DG540 DG541 RL = 1 k CL = 35 pF 50 % to 90 % See Figure 2 DG542 DG540 DG541 DG542 Charge Injection Off Isolation All Hostile Crosstalk Q OIRR XTALK(AH) 70 130 100 160 50 85 60 85 55 20 25 Room - 25 Room - 80 Room - 60 Room - 75 RIN = 10 , RL = 75  f = 5 MHz, See Figure 6 Room - 85 3.5 All Channels On or Off Room Full Room Full pF MHz 45 CL = 1000 pF, VS = 0 V See Figure 3 RIN = 75 RL = 75  DG540 DG541 f = 5 MHz See Figure 4 DG542 20 70 130 100 160 50 85 60 85 ns pC dB Power Supplies Positive Supply Current I+ Negative Supply Current I- - 3.2 6 9 -6 -9 6 9 -6 -9 mA Notes: a. Refer to PROCESS OPTION FLOWCHART . b. Room = 25 °C, full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 4 Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted) 6 100 nA 5 10 nA 4 I+ I S(off), I D(off)– Leakage 3 I (mA) 2 1 IGND 0 -1 -2 I-3 1 nA 100 pA 10 pA 1 pA -4 -5 - 55 0.1 pA - 35 - 15 5 25 45 65 Temperature (°C) 85 105 - 55 125 Supply Curent vs. Temperature 0 25 50 75 Temperature (°C) 42 120 RDS(on) – Drain-Source On-Resistance (Ω) V+ = 15 V V- = - 3 V 140 125 °C 100 80 25 °C 60 - 55 °C 40 20 -1 1 3 5 7 9 42 40 40 38 38 V- = - 5 V 36 36 V+ = 12 V 34 34 32 32 V- = - 3 V V+ = 15 V 30 30 20 20 11 V- = - 1 V 18 -5 -4 -3 -2 -1 0 10 11 12 13 14 15 16 VD – Drain Voltage (V) V- – Negative Supply (V) V+ – Positive Supply (V) RDS(on) vs. Drain Voltage V+ Constant V- Constant 22 - 110 20 - 100 RL = 75 Ω - 90 18 - 80 ISO (dB) 16 C (pF) 125 V+ = 10 V 18 0 -3 100 ID(off), IS(off) vs. Temperature 160 r DS(on) – Drain-Source On-Resistance (Ω) - 25 14 DG540 - 70 DG542 - 60 - 50 12 DG541 - 40 10 - 30 8 - 20 - 10 6 0 2 4 6 8 10 VD – Drain Voltage (V) On Capacitance Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 12 14 1 10 f – Frequency (MHz) 100 Off Isolation www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted) - 100 - 110 - 90 - 100 RL = 75 Ω - 80 - 70 - 80 1 k - 60 X TALK (dB) OIRR (dB) DG540 - 90 180 Ω 10 k - 50 - 40 DG542 - 70 - 60 DG541 - 50 - 30 - 40 - 20 - 30 - 10 - 20 - 10 0 1 10 f – Frequency (MHz) 1 100 10 f - Frequency (MHz) Off Isolation vs. Frequency and Load Resistance (DG540) 100 All Hostile Crosstalk 90 40 80 30 70 20 60 Time (ns) Q (pC) 10 0 - 10 tON 50 40 30 - 20 tOFF 20 CL = 1000 pF - 30 10 0 - 40 -3 -2 -1 0 1 2 3 4 5 VS – Source Voltage (V) 6 7 8 - 55 Charge Injection vs. VS - 25 0 25 50 75 Temperature (°C) 100 125 Switching Times vs. Temperature (DG540/541) 20 90 80 18 V+ – Positive Supply (V) tON 70 Time (ns) 60 tBBM 50 40 tOFF 30 20 16 Operating Voltage Area 14 12 10 10 0 - 55 - 25 0 25 50 Temperature (°C) 75 100 Switching and Break-Before-Make Time vs. Temperature (DG542) www.vishay.com 6 125 0 -1 -2 -3 -4 -5 -6 V- – Negative Supply (V) Operating Supply Voltage Range Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix TEST CIRCUITS + 15 V 3V tr < 20 ns tf < 20 ns 3V V+ D S VO IN CL 35 pF RL 1 kΩ V- GND Logic Input Switch Input 50 % VS 90 % Switch Output 0 -3V tON tOFF CL (includes fixture and stray capacitance) RL VO = VS RL + rDS(on) Figure 2. Switching Time ΔV O + 15 V V+ Rg VO D S VO IN Vg CL 1000 pF 3V INX V- GND ON OFF ON ΔVO = measured voltage error due to charge injection The charge injection in coulombs is ΔQ = C L x DV O -3V Figure 3. Charge Injection + 15 V C V+ S VS Rg = 75 Ω 0 V, 2.4 V + 15 V VO D RL 75 Ω IN C V+ S VS VO D Rg = 50 Ω GND V- RL 50 Ω C 0 V, 2.4 V IN GND V- C -3V Off Isolation = 20 log VS VO C = RF Bypass Figure 4. Off Isolation Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 -3V Figure 5. Bandwidth www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix TEST CIRCUITS C + 15 V V+ S1 10 Ω 2.4 V D1 VO RL 75 Ω INX S2 D2 S3 D3 S4 D4 GND V- RL RL RL C - 15 V VOUT XTA LK(AH) = 20 log10 V IN Figure 6. All Hostile Crosstalk APPLICATIONS Device Description Frequency Response The DG540, DG541, DG542 family of wideband switches A single switch on-channel exhibits both resistance (RDS(on)) offers true bidirectional switching of high frequency analog or and capacitance (CS(on)). This RC combination has an digital signals with minimum signal crosstalk, low insertion attenuation effect on the analog signal – which is frequency loss, and negligible non-linearity distortion and group delay. dependent (like an RC low-pass filter). The - 3-dB bandwidth Built on the Siliconix D/CMOS process, these "T" switches of the DG540 is typically 500 MHz (into 50 ). This measured provide excellent off-isolation with a bandwidth of around figure of 500 MHz illustrates that the switch channel can not 500 MHz (350 MHz for DG541). Silicon-gate D/CMOS be represented by a two stage RC combination. The on processing also yields fast switching speeds. capacitance of the channel is distributed along the on- An on-chip regulator circuit maintains TTL input compatibility resistance, and hence becomes a more complex multi stage over the whole operating supply voltage range, easing network of R’s and C’s making up the total RDS(on) and CS(on). See Application Note AN502 for more details. control logic interfacing. Circuit layout is facilitated by the interchangeability of source and drain terminals. Off-Isolation and Crosstalk Off-isolation and crosstalk are affected by the load resistance and parasitic inter-electrode capacitances. Higher off-isolation is achieved with lower values of RL. However, low values of RL increase insertion loss requiring gain adjustments down the line. Stray capacitances, even a fraction of 1 pF, can cause a large crosstalk increase. Good layout and ground shielding techniques can considerably improve your ac circuit performance. www.vishay.com 8 Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix APPLICATIONS Power Supplies A useful feature of the DG54X family is its power supply flexibility. It can be operated from a single positive supply + 15 V (V+) if required (V- connected to ground). Note that the analog signal must not exceed V- by more than + - 0.3 V to prevent forward biasing the substrate p-n junction. C1 The use of a V- supply has a number of advantages: 1. C2 V+ It allows flexibility in analog signal handling, i.e., with V- = - 5 V and V+ = 12 V; up to ± 5 V ac signals can S1 D1 S2 D2 be controlled. 2. The value of on capacitance [CS(on)] may be reduced. DG540 S3 A property known as ‘the body-effect’ on the DMOS switch devices causes various parametric effects to D3 S4 D4 occur. One of these effects is the reduction in CS(on) GNDs for an increasing V body-source. Note, however, that V- to increase V- normally requires V+ to be reduced (since V+ to V- = 21 V max.). Reduction in V+ causes C1 = 10 μF Tantalum C2 = 0.1 μF Ceramic an increase in RDS(on), hence a compromise has to C1 C2 + be achieved. It is also useful to note that optimum -3V video linearity performance (e.g., differential phase and gain) occurs when V- is around - 3 V. 3. Figure 7. Supply Decoupling V- eliminates the need to bias the analog signal using potential dividers and large coupling capacitors. Decoupling It is an established RF design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance of the DG54X is adversely affected by Board Layout PCB layout rules for good high frequency performance must be observed to achieve the performance boasted by the DG540. Some tips for minimizing stray effects are: 1. Use extensive ground planes on double sided PCB, poor decoupling of power supply pins. Also, of even more separating adjacent signal paths. Multilayer PCB is significance, since the substrate of the device is connected even better. to the negative supply, adequate decoupling of this pin is essential. 2. with all channel paths of near equal length. Rules: 1. 2. 3. Keep signal paths as short as practically possible, Decoupling capacitors should be incorporated on all power supply pins (V+, V-). (See Figure 7.) They should be mounted as close as possible to the device pins. 3. Careful arrangement of ground connections is also very important. Star connected system grounds eliminate signal current flowing through ground path parasitic resistance from coupling between channels. Capacitors should have good high frequency characteristics - tantalum bead and/or monolithic ceramic types are adequate. Suitable decoupling capacitors are 1- to 10 µF tantalum bead, plus 10- to 100 nF ceramic. Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 www.vishay.com 9 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG540, DG541, DG542 Vishay Siliconix APPLICATIONS Figure 8 shows a 4 Channel video multiplexer using a DG540. + 15 V V+ CH1 CH2 75 Ω Si582 75 Ω + CH3 A=2 75 Ω CH4 - 75 Ω DG540 V75 Ω DIS 250 Ω 250 Ω -3V TTL Channel Select Figure 8. 4 by 1 Video Multiplexing Using the DG540 Figure 9 shows an RGB selector switch using two DG542s. + 15 V V+ R1 75 Ω Red Out R2 75 Ω G1 75 Ω Green Out G2 75 Ω DG542 V-3V Si584 + 15 V V+ B1 75 Ω Blue Out B2 75 Ω Sync 1 75 Ω Sync Out Sync 2 75 Ω DG542 RGB Source Select V-3V Figure 9. RGB Selector Using Two DG542s Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70055. www.vishay.com 10 Document Number: 70055 S11-1429–Rev. H, 18-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOIC (NARROW): 16ĆLEAD JEDEC Part Number: MS-012 MILLIMETERS 16 15 14 13 12 11 10 Dim A A1 B C D E e H L Ĭ 9 E 1 2 3 4 5 6 7 8 INCHES Min Max Min Max 1.35 1.75 0.053 0.069 0.10 0.20 0.004 0.008 0.38 0.51 0.015 0.020 0.18 0.23 0.007 0.009 9.80 10.00 0.385 0.393 3.80 4.00 0.149 0.157 1.27 BSC 0.050 BSC 5.80 6.20 0.228 0.244 0.50 0.93 0.020 0.037 0_ 8_ 0_ 8_ ECN: S-03946—Rev. F, 09-Jul-01 DWG: 5300 H D C All Leads e Document Number: 71194 02-Jul-01 B A1 L Ĭ 0.101 mm 0.004 IN www.vishay.com 1 Package Information Vishay Siliconix PDIP: 16ĆLEAD 16 15 14 13 12 11 10 9 E E1 1 2 3 4 5 6 7 8 D S Q1 A A1 L 15° MAX C B1 e1 Dim A A1 B B1 C D E E1 e1 eA L Q1 S B eA MILLIMETERS Min Max INCHES Min Max 3.81 5.08 0.150 0.200 0.38 1.27 0.015 0.050 0.38 0.51 0.015 0.020 0.89 1.65 0.035 0.065 0.20 0.30 0.008 0.012 18.93 21.33 0.745 0.840 7.62 8.26 0.300 0.325 5.59 7.11 0.220 0.280 2.29 2.79 0.090 0.110 7.37 7.87 0.290 0.310 2.79 3.81 0.110 0.150 1.27 2.03 0.050 0.080 0.38 1.52 .015 0.060 ECN: S-03946—Rev. D, 09-Jul-01 DWG: 5482 Document Number: 71261 06-Jul-01 www.vishay.com 1 Package Information Vishay Siliconix PDIP: 20ĆLEAD 20 19 18 17 16 15 14 13 12 11 E1 1 2 3 4 5 6 7 8 9 E 10 D S Q1 A A A1 L 15° MAX C B1 e1 B Dim A A1 B B1 C D E E1 e1 eA L Q1 S MILLIMETERS Min Max eA INCHES Min Max 3.81 5.08 0.150 0.200 0.38 1.27 0.015 0.050 0.38 0.51 0.015 0.020 0.89 1.65 0.035 0.065 0.20 0.30 0.008 0.012 24.89 26.92 0.980 1.060 7.62 8.26 0.300 0.325 5.59 7.11 0.220 0.280 2.29 2.79 0.090 0.110 7.37 7.87 0.290 0.310 3.175 3.81 0.123 0.150 1.27 2.03 0.050 0.080 1.02 2.03 0.040 0.080 ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5484 Document Number: 71262 06-Jul-01 www.vishay.com 1 Package Information Vishay Siliconix PLCC: 2OĆLEAD D–SQUARE A2 MILLIMETERS D1–SQUARE B1 B e1 D2 Document Number: 71263 02-Jul-01 INCHES Min Max Min Max 4.20 4.57 0.165 0.180 2.29 3.04 0.090 0.120 0.51 – 0.020 – 0.331 0.553 0.013 0.021 0.661 0.812 0.026 0.032 9.78 10.03 0.385 0.395 8.890 9.042 0.350 0.356 7.37 8.38 0.290 0.330 1.27 BSC 0.050 BSC ECN: S-03946—Rev. C, 09-Jul-01 DWG: 5306 A1 A Dim A A1 A2 B B1 D D1 D2 e1 0.101 mm 0.004″ www.vishay.com 1 Package Information Vishay Siliconix SIDEBRAZE: 16ĆLEAD 16 15 14 13 12 11 10 9 E 1 2 3 4 5 6 7 8 D S1 S2 A Q L e b c b2 eA Dim A b b2 c D E e eA L Q S2 S1 MILLIMETERS Min Max INCHES Min Max 2.67 4.45 0.105 0.175 0.38 0.53 0.015 0.021 1.14 1.65 0.045 0.065 0.20 0.30 0.008 0.012 19.56 21.08 0.770 0.830 7.11 7.87 0.280 0.310 2.54 BSC 0.100 BSC 7.62 BSC 0.300 BSC 3.18 4.45 0.125 0.175 0.64 1.40 0.025 0.055 0.25 – 0.010 – 0.13 – 0.005 – ECN: S-03946—Rev. G, 09-Jul-01 DWG: 5418 Document Number: 71270 03-Jul-01 www.vishay.com 1 Package Information Vishay Siliconix SIDEBRAZE: 20ĆLEAD Meets MIL-STD-1835, D8, Configuration C 20 E 1 2 3 D S1 S2 A Q L b e C b2 eA Dim A b b2 c D E e eA L Q S2 S1 MILLIMETERS Min Max INCHES Min Max 2.67 4.45 0.105 0.175 0.38 0.53 0.015 0.021 1.14 1.65 0.045 0.065 0.20 0.30 0.008 0.012 24.89 26.16 0.980 1.030 7.11 7.87 0.280 0.310 2.54 BSC 0.100 BSC 7.62 BSC 0.300 BSC 3.18 4.45 0.125 0.175 0.64 1.40 0.025 0.055 0.25 – 0.010 – 0.13 – 0.005 – ECN: S-03946—Rev. D, 09-Jul-01 DWG: 5309 Document Number: 71271 02-Jul-01 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-16 RECOMMENDED MINIMUM PADS FOR SO-16 0.372 (9.449) 0.152 0.022 0.050 0.028 (0.559) (1.270) (0.711) (3.861) 0.246 (6.248) 0.047 (1.194) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 24 Document Number: 72608 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000