IRF530S, SiHF530S
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Vishay Siliconix
Power MOSFET
FEATURES
D
•
•
•
•
•
•
•
•
D2PAK (TO-263)
G
G D
S
S
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
100
VGS = 10 V
26
Qgs (nC)
5.5
Qgd (nC)
11
Configuration
DESCRIPTION
0.16
Qg max. (nC)
Surface-mount
Available in tape and reel
Dynamic dv/dt rating
Available
Repetitive avalanche rated
175 °C operating temperature
Available
Fast switching
Ease of paralleling
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface-mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface-mount package. The
D2PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface-mount application.
Single
ORDERING INFORMATION
Package
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
Lead (Pb)-free and halogen-free
SiHF530S-GE3
SiHF530STRL-GE3 a
SiHF530STRR-GE3 a
Lead (Pb)-free
IRF530SPbF
IRF530STRLPbF a
IRF530STRRPbF a
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
SYMBOL
LIMIT
VDS
VGS
100
± 20
14
10
ID
IDM
UNIT
V
A
56
Linear derating factor
0.59
Linear derating factor (PCB mount) e
0.025
W/°C
Single pulse avalanche energy b
EAS
69
Avalanche current a
IAR
14
A
Repetitive avalanche energy a
EAR
8.8
mJ
Maximum power dissipation
TC = 25 °C
Maximum power dissipation (PCB mount) e
TA = 25 °C
Peak diode recovery dv/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
for 10 s
PD
88
3.7
dv/dt
5.5
TJ, Tstg
-55 to +175
300
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 528 μH, Rg = 25 , IAS = 14 A (see fig. 12)
c. ISD 14 A, di/dt 140 A/μs, VDD VDS, TJ 175 °C
d. 1.6 mm from case
e. When mounted on 1" square PCB (FR-4 or G-10 material)
S20-0683-Rev. D, 07-Sep-2020
Document Number: 91020
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF530S, SiHF530S
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-ambient
(PCB mount) a
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VDS
VGS = 0, ID = 250 μA
100
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.12
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-source leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 100 V, VGS = 0 V
-
-
25
VDS = 80 V, VGS = 0 V, TJ = 150 °C
-
-
250
Drain-source on-state resistance
Forward transconductance
μA
-
-
0.16
gfs
VDS = 50 V, ID = 8.4 A b
5.1
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
670
-
-
250
-
-
60
-
-
-
26
-
-
5.5
RDS(on)
ID = 8.4 A b
VGS = 10 V
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
ID = 14 A, VDS = 80 V,
see fig. 6 and 13 b
Gate-drain charge
Qgd
-
-
11
Turn-on delay time
td(on)
-
10
-
Rise time
tr
Turn-off delay time
td(off)
Fall time
tf
Gate input resistance
Rg
Internal drain inductance
LD
Internal source inductance
LS
VDD = 50 V, ID = 14 A,
Rg = 12 , RD = 3.6 , see fig. 10 b
-
34
-
-
23
-
-
24
-
f = 1 MHz, open drain
1.0
-
4.7
-
4.5
-
-
7.5
-
-
-
14
-
-
56
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current
a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 14 A, VGS = 0 V b
TJ = 25 °C, IF = 14 A, di/dt = 100 A/μs b
-
-
2.5
V
-
150
280
ns
-
0.85
1.7
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
S20-0683-Rev. D, 07-Sep-2020
Document Number: 91020
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF530S, SiHF530S
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Vishay Siliconix
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
ID, Drain Current (A)
Top
101
4.5 V
100
20 µs Pulse Width
TC = 25 °C
10-1
100
3.5
3.0
ID = 14 A
VGS = 10 V
2.5
2.0
1.5
1.0
0.5
0.0
- 60- 40 - 20 0
101
VDS, Drain-to-Source Voltage (V)
91020_01
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TJ, Junction Temperature (°C)
91020_04
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
1400
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
1200
4.5 V
Capacitance (pF)
ID, Drain Current (A)
Top
101
1000
Ciss
800
600
Coss
400
100
10-1
100
0
101
100
VDS, Drain-to-Source Voltage (V)
91020_02
Crss
200
20 µs Pulse Width
TC = 175 °C
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
ID, Drain Current (A)
175 °C
101
100
20 µs Pulse Width
VDS = 50 V
4
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S20-0683-Rev. D, 07-Sep-2020
VGS, Gate-to-Source Voltage (V)
20
25 °C
101
VDS, Drain-to-Source Voltage (V)
91020_05
Fig. 2 - Typical Output Characteristics, TC = 175 °C
91020_03
20 40 60 80 100 120 140 160 180
ID = 14 A
VDS = 80 V
16
VDS = 50 V
VDS = 20 V
12
8
4
For test circuit
see figure 13
0
10
0
91020_06
5
10
15
20
25
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91020
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF530S, SiHF530S
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Vishay Siliconix
12
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
14
175 °C
101
25 °C
100
10
8
6
4
2
VGS = 0 V
0.4
0.8
1.2
0
2.0
1.6
25
VSD, Source-to-Drain Voltage (V)
91020_07
50
Operation in this area limited
by RDS(on)
VGS
102
5
10 µs
2
100 µs
10
175
D.U.T.
Rg
+
- VDD
10 V
1 ms
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
5
10 ms
2
150
RD
VDS
5
2
125
Fig. 9 - Maximum Drain Current vs. Case Temperature
103
ID, Drain Current (A)
100
TC, Case Temperature (°C)
91020_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
75
1
Fig. 10a - Switching Time Test Circuit
5
TC = 25 °C
TJ = 175 °C
Single Pulse
2
0.1
0.1
2
5
1
2
5
10
2
VDS
5
2
102
5
90 %
103
VDS, Drain-to-Source Voltage (V)
91020_08
Fig. 8 - Maximum Safe Operating Area
10 %
VGS
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
0 - 0.5
0.2
PDM
0.1
0.1
0.05
t1
0.02
0.01
t2
Single Pulse
(Thermal Response)
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
91020_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S20-0683-Rev. D, 07-Sep-2020
Document Number: 91020
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF530S, SiHF530S
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Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
Rg
+
V DD
-
I AS
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
200
ID
5.7 A
9.9 A
Bottom 14 A
Top
160
120
80
40
0
VDD = 25 V
25
91020_12c
50
75
100
125
175
150
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S20-0683-Rev. D, 07-Sep-2020
Fig. 13b - Gate Charge Test Circuit
Document Number: 91020
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF530S, SiHF530S
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91020.
S20-0683-Rev. D, 07-Sep-2020
Document Number: 91020
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
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with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
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Revision: 01-Jan-2022
1
Document Number: 91000