IRF640STRLPBF

IRF640S, SiHF640S, SiHF640L www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • • 200 RDS(on) () VGS = 10 V 0.18 Qg max. (nC) 70 Qgs (nC) 13 Qgd (nC) 39 Configuration Single D Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. D2PAK (TO-263) I2PAK (TO-262) G G G D S Surface mount Low-profile through-hole Available in tape and reel Available Dynamic dV/dt rating 150 °C operating temperature Available Fast switching Fully avalanche rated Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 D DESCRIPTION S Third generation power MOSFETs from Vishay provide the designer with the best combinations of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capable of accommodating die size up to HEX-4. It provides the highest power capability and the last lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (SiHF640L) is available for low-profile applications. S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) SiHF640S-GE3 IRF640SPbF D2PAK (TO-263) SiHF640STRL-GE3 a IRF640STRLPbF a D2PAK (TO-263) SiHF640STRR-GE3 a IRF640STRRPbF a I2PAK (TO-262) SiHF640L-GE3 - Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage SYMBOL VDS VGS Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a, e Linear Derating Factor Single Pulse Avalanche Energy b, e Avalanche Current a Repetitive Avalanche Energy a Maximum Power Dissipation c, e ID IDM EAS IAR EAR TC = 25 °C TA = 25 °C PD dV/dt Peak Diode Recovery dV/dt Operating Junction and Storage Temperature Range TJ, Tstg for 10 s Soldering Recommendations (Peak temperature) d Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 2.7 mH, Rg = 25 , IAS = 18 A (see fig. 12). c. ISD  18 A, dI/dt  150 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. Uses IRF640, SiHF640 data and test conditions. S16-0014-Rev. E, 18-Jan-16 LIMIT 200 ± 20 18 11 72 1.0 580 18 13 130 3.1 5.0 -55 to +150 300 UNIT V A W/°C mJ A mJ W V/ns °C Document Number: 91037 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF640S, SiHF640S, SiHF640L www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient  (PCB mounted, steady-state) a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 μA 200 - - V VDS/TJ Reference to 25 °C, ID = 1 mA c - 0.29 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 200 V, VGS = 0 V - - 25 VDS = 160 V, VGS = 0 V, TJ = 125 °C - - 250 μA - - 0.18  gfs VDS = 50 V, ID = 11 A d 6.7 - - S Input Capacitance Ciss - 1300 - Output Capacitance Coss - 430 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 d - 130 - - - 70 - - 13 Drain-Source On-State Resistance Forward Transconductance RDS(on) ID = 11 A b VGS = 10 V Dynamic Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 39 Turn-On Delay Time td(on) - 14 - tr VDD = 100 V, ID = 18 A, Rg = 9.1 , RD = 5.4 , see fig. 10 b, c - 51 - - 45 - - 36 - f = 1 MHz, open drain 0.5 - 3.6 - - 18 - - 72 Rise Time Turn-Off Delay Time td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 18 A, VDS = 160 V, see fig. 6 and 13 b, c pF nC ns  Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current a ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the  integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 18 A, VGS = 0 V b TJ = 25 °C, IF = 18 A, dI/dt = 100 A/μs b, c - - 2.0 V - 300 610 ns - 3.4 7.1 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. c. Uses IRF640/SiHF640 data and test conditions. S16-0014-Rev. E, 18-Jan-16 Document Number: 91037 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF640S, SiHF640S, SiHF640L www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V ID, Drain Current (A) Top 101 100 4.5 V 20 µs Pulse Width TC = 25 °C 100 10-1 101 VDS, Drain-to-Source Voltage (V) 91037_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 ID = 18 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 TJ, Junction Temperature (°C) 91037_04 Fig. 1 - Typical Output Characteristics, TJ = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature 3000 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 2500 4.5 V 100 Capacitance (pF) ID, Drain Current (A) Top 101 2000 Ciss 1500 1000 Coss 500 Crss 20 µs Pulse Width TC = 150 °C 10-1 100 0 101 100 VDS, Drain-to-Source Voltage (V) 91037_02 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 25 °C 100 20 µs Pulse Width VDS = 50 V 10-1 VGS, Gate-to-Source Voltage (V) ID, Drain Current (A) 20 150 °C 101 VDS, Drain-to-Source Voltage (V) 91037_05 Fig. 2 - Typical Output Characteristics, TJ = 175 °C 101 20 40 60 80 100 120 140 160 ID = 18 A VDS = 160 V 16 VDS = 100 V VDS = 40 V 12 8 4 For test circuit see figure 13 0 4 91037_03 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S16-0014-Rev. E, 18-Jan-16 10 0 91037_06 15 30 45 60 75 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91037 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF640S, SiHF640S, SiHF640L www.vishay.com Vishay Siliconix 150 °C ID, Drain Current (A) ISD, Reverse Drain Current (A) 20 25 °C 101 16 12 8 4 100 VGS = 0 V 0.50 0.70 0.90 0 1.50 1.30 1.10 25 VSD, Source-to-Drain Voltage (V) 91037_07 VGS 102 100 µs 2 10 5 1 ms 2 10 ms 150 D.U.T. Rg 10 µs 5 125 RD VDS 2 ID, Drain Current (A) 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91037_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 103 50 + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit 1 TC = 25 °C TJ = 150 °C Single Pulse 5 2 0.1 0.1 2 5 1 2 5 10 2 VDS 5 102 2 5 90 % 103 VDS, Drain-to-Source Voltage (V) 91037_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 0.1 0 − 0.5 0.2 0.1 0.05 0.02 0.01 PDM 10-3 10-5 91037_11 t1 Single Pulse (Thermal Response) 10-2 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 10 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S16-0014-Rev. E, 18-Jan-16 Document Number: 91037 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF640S, SiHF640S, SiHF640L www.vishay.com Vishay Siliconix 15 V QG 10 V Rg + A - VDD IAS Charge 0.01 Ω tp QGD VG D.U.T. 20 V QGS Driver L VDS Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS tp 50 kΩ 12 V 0.2 µF 0.3 µF + D.U.T. - VDS VGS IAS 3 mA IG ID Current sampling resistors Fig. 12b - Unclamped Inductive Waveforms Fig. 13b - Gate Charge Test Circuit EAS, Single Pulse Energy (mJ) 1400 ID Top 8.0 A 11.0 A Bottom 18.0 A 1200 1000 800 600 400 200 0 VDD = 50 V 25 91037_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current S16-0014-Rev. E, 18-Jan-16 Document Number: 91037 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF640S, SiHF640S, SiHF640L www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel          Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91037. S16-0014-Rev. E, 18-Jan-16 Document Number: 91037 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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