IRF737LCPBF

IRF737LC, SiHF737LC Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • 300 RDS(on) (Ω) VGS = 10 V 0.75 Qg (Max.) (nC) 17 Qgs (nC) 4.8 Qgd (nC) 7.6 Configuration Single COMPLIANT This new series of low charge Power MOSFETs achieve significantly lower gate charge over conventional Power MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition, reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge Power MOSFETs. These device improvements combined with the proven ruggedness and reliability that are characteristics of Power MOSFETs offer the designer a new standard in power transistors for switching applications. G S G Available RoHS* DESCRIPTION D TO-220 Reduced Gate Drive Requirement Enhanced 30 V VGS Rating Reduced Ciss, Coss, Crss Extremely High Frequency Operation Repetitive Avalanche Rated Lead (Pb)-free Available D S N-Channel MOSFET ORDERING INFORMATION Package TO-220 IRF737LCPbF SiHF737LC-E3 IRF737LC SiHF737LC Lead (Pb)-free SnPb ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current SYMBOL VDS VGS VGS at 10 V TC = 25 °C TC = 100 °C Currenta Pulsed Drain Linear Derating Factor Single Pulse Avalanche Energyb Avalanche Currenta Repetiitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque ID IDM TC = 25 °C for 10 s 6-32 or M3 screw EAS IAR EAR PD dV/dt TJ, Tstg LIMIT 300 ± 30 6.1 3.9 24 0.59 120 6.1 7.4 74 3.4 - 55 to + 150 300d 10 1.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 5.7 mH, RG = 25 Ω, IAS = 6.1 A (see fig. 12). c. ISD ≤ 6.1 A, dI/dt ≤ 270 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91050 S-82998-Rev. A, 12-Jan-09 www.vishay.com 1 IRF737LC, SiHF737LC Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - 62 Case-to-Sink, Flat, Greased Surface RthCS 0.50 - Maximum Junction-to-Case (Drain) RthJC - 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 µA 300 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.391 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VGS = ± 20 V - - ± 100 VDS = 300 V, VGS = 0 V - - 25 VDS = 240 V, VGS = 0 V, TJ = 150 °C - - 250 - - 0.75 Ω 2.7 - - S IGSS IDSS RDS(on) gfs ID = 3.7 Ab VGS = 10 V VDS = 50 V, ID = 3.7 Ab µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 10 V ID = 6.1 A, VDS = 240 V, see fig. 6 and 13b - 430 - - 120 - - 9.2 - - - 17 - - 4.8 Gate-Drain Charge Qgd - - 7.6 Turn-On Delay Time td(on) - 6.6 - - 21 - - 13 - - 12 - - 4.5 - - 7.5 - - - 6.1 - - 24 Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 150 V, ID = 6.1 A, RG = 12 Ω, RD = 24 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 6.1 A, VGS = 0 S Vb TJ = 25 °C, IF = 6.1 A, dI/dt = 100 A/µsb - - 1.6 V - 320 490 ns - 1.5 2.2 µC Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91050 S-82998-Rev. A, 12-Jan-09 IRF737LC, SiHF737LC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 102 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V ID, Drain-to-Source Current (A) Top 10 1 4.5 V 0.1 20 µs Pulse Width TC = 25 °C 10-2 0.1 1 10 TJ = 150 °C 0.1 4 ID, Drain-to-Source Current (A) 4.5 V 0.1 20 µs Pulse Width TC = 150 °C 10-2 0.1 91050_02 1 10 102 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 150 °C Document Number: 91050 S-82998-Rev. A, 12-Jan-09 6 7 8 9 10 Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On Resistance (Normalized) VGS 15 V 10 V 8.0 V 10 7.0 V 6.0 V 5.5 V 5.0 V 1 Bottom 4.5 V 5 VGS, Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, TC = 25 °C Top 20 µs Pulse Width VDS = 50 V 10-2 91050_03 102 TJ = 25 °C 1 102 10 VDS, Drain-to-Source Voltage (V) 91050_01 ID, Drain-to-Source Current (A) 102 91050_04 3.0 ID = 6.1 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 IRF737LC, SiHF737LC Vishay Siliconix VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 700 C, Capacitance (pF) 600 500 Ciss 400 300 Coss 200 100 Crss 102 ISD, Reverse Drain Current (A) 800 10 TJ = 150 °C TJ = 25 °C 1 0 102 10 VDS, Drain-to-Source Voltage (V) 91050_05 0.2 VDS = 150 V 12 8 4 For test circuit see figure 13 0 0 91050_06 4 8 12 Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 1.2 1.4 10 µs 10 100 µs 1 ms 1 1 91050_08 10 ms TC = 25 °C TJ = 150 °C Single Pulse 0.1 16 QG, Total Gate Charge (nC) 0.8 Operation in this area limited by RDS(on) VDS = 240 V ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 102 VDS = 60 V 0.6 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID = 6.1 A 16 0.4 1.0 VSD, Source-to-Drain Voltage (V) 91050_07 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 20 VGS = 0 V 0.1 1 10 102 103 VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 91050 S-82998-Rev. A, 12-Jan-09 IRF737LC, SiHF737LC Vishay Siliconix RD VDS VGS 7.0 D.U.T. RG + - VDD ID, Drain Current (A) 6.0 10 V 5.0 Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 4.0 Fig. 10a - Switching Time Test Circuit 3.0 VDS 2.0 90 % 1.0 0.0 25 50 75 100 125 150 10 % VGS TC, Case Temperature (°C) 91050_09 td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.50 0.20 PDM 0.10 0.05 0.02 0.01 0.1 t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 10-4 10-3 10-2 0.1 1 t1, Rectangular Pulse Duration (s) 91050_11 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T. RG + - I AS V DD VDS 10 V tp 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91050 S-82998-Rev. A, 12-Jan-09 IAS Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 IRF737LC, SiHF737LC EAS, Single Pulse Avalanche Energy (mJ) Vishay Siliconix 240 ID 2.7 A 3.9 A Bottom 6.1 A Top 200 160 120 91050_12c 80 40 0 VDD = 50 V 25 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91050 S-82998-Rev. A, 12-Jan-09 IRF737LC, SiHF737LC Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91050. Document Number: 91050 S-82998-Rev. A, 12-Jan-09 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. 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