IRF740LC
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
D
•
•
•
•
•
•
•
TO-220AB
G
G
D
S
S
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
400
VGS = 10 V
39
Qgs (nC)
10
Qgd (nC)
19
Configuration
DESCRIPTION
0.55
Qg (Max.) (nC)
Ultra low gate charge
Reduced gate drive requirement
Available
Enhanced 30 V VGS rating
Reduced Ciss, Coss, Crss
Extremely high frequency operation
Repetitive avalanche rated
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
This new series of low charge Power MOSFETs achieve
significantly lower gate charge over conventional MOSFETs.
Utilizing the new LCDMOS technology, the device
improvements are achieved without added product cost,
allowing for reduced gate drive requirements and total
system savings. In addition, reduced switching losses and
improved efficiency are achievable in a variety of high
frequency applications. Frequencies of a few MHz at high
current are possible using the new Low Charge MOSFETs.
These device improvements combined with the proven
ruggedness and reliability that are characteristic of Power
MOSFETs ofter the designer a new standard in power
transistors for switching applications.
Single
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and halogen-free
TO-220AB
IRF740LCPbF
IRF740LCPbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current
Pulsed drain current a
Linear derating factor
Single pulse avalanche energy b
Repetitive avalanche current a
Repetitive avalanche energy a
Maximum power dissipation
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
Mounting torque
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
TC = 25 °C
For 10 s
6-32 or M3 screw
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
LIMIT
400
± 30
10
6.3
32
1.0
520
10
13
125
4.0
- 55 to + 150
300d
10
1.1
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 9.1 mH, Rg = 25 Ω, IAS = 10 A (see fig. 12)
c. ISD ≤ 10 A, dI/dt ≤ 120 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
S21-0853-Rev. C, 16-Aug-2021
Document Number: 91053
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740LC
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Case-to-sink, flat, greased surface
RthCS
0.50
-
Maximum junction-to-case (drain)
RthJC
-
1.0
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
Gate-source leakage
Zero gate voltage drain current
Drain-source on-state resistance
Forward transconductance
VDS
VGS = 0 V, ID = 250 μA
400
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.76
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
IGSS
VGS = ± 20 V
-
-
± 100
nA
VDS = 400 V, VGS = 0 V
-
-
25
VDS = 320 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
0.55
Ω
3.0
-
-
S
IDSS
RDS(on)
gfs
ID = 6.0 Ab
VGS = 10 V
VDS = 50 V, ID = 6.0
Ab
μA
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Total gate charge
Qg
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 10 A, VDS = 320 V
see fig. 6 and 13b
-
1100
-
-
190
-
-
18
-
-
-
39
-
-
10
Gate-source charge
Qgs
Gate-drain charge
Qgd
-
-
19
Turn-on delay time
td(on)
-
11
-
tr
-
31
-
-
25
-
-
20
-
-
4.5
-
Rise time
Turn-off delay time
td(off)
Fall time
tf
Internal drain inductance
LD
Internal source inductance
LS
VDD = 200 V, ID = 10 A ,
Rg = 9.1 Ω, RD = 20 Ω, see fig. 10b
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
-
7.5
-
-
-
10
-
-
32
-
-
2.0
-
380
570
ns
-
2.8
4.2
μC
S
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 10 A, VGS = 0
S
Vb
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
S21-0853-Rev. C, 16-Aug-2021
Document Number: 91053
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740LC
www.vishay.com
Vishay Siliconix
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
Top
ID, Drain Current (A)
101
100
4.5 V
10-1
20 µs Pulse Width
TC = 25 °C
10-2
10-2
10-1
100
101
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
VDS, Drain-to-Source Voltage (V)
91053_01
91053 04
Fig. 1 - Typical Output Characteristics, TC = 25 °C
20 40 60 80 100 120 140 160
T Junction Temperature (°C)
Fig. 3 - Normalized On-Resistance vs. Temperature
2000
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Top
100
1600
Capacitance (pF)
101
ID, Drain Current (A)
ID = 10 A
VGS = 10 V
4.5 V
10-1
Ciss
1200
Coss
800
400
10-2
10-2
10-1
0
101
100
100
VDS, Drain-to-Source Voltage (V)
91053_02
Crss
20 µs Pulse Width
TC = 150 °C
VDS, Drain-to-Source Voltage (V)
91053_05
Fig. 1 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
ID, Drain Current (A)
150 °C
100
25 °C
10-1
20 µs Pulse Width
VDS = 50 V
10-2
4
91053_03
5
6
7
8
9
Fig. 2 - Typical Transfer Characteristics
ID = 11 A
VDS = 320 V
16
VDS = 200 V
VDS = 80 V
12
8
4
For test circuit
see figure 13
0
10
VGS, Gate-to-Source Voltage (V)
S21-0853-Rev. C, 16-Aug-2021
VGS, Gate-to-Source Voltage (V)
20
101
101
0
91053_06
6
12
18
24
30
36
42
QG, Total Gate Charge (nC)
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91053
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740LC
www.vishay.com
Vishay Siliconix
RD
ISD, Reverse Drain Current (A)
VDS
VGS
150 °C
D.U.T.
RG
+
- VDD
101
25 °C
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VGS = 0 V
100
0.6
0.8
1.0
1.4
1.2
1.6
1.8
VDS
90 %
VSD, Source-to-Drain Voltage (V)
91053_07
Fig. 6 - Typical Source-Drain Diode Forward Voltage
10 %
VGS
103
td(on)
Operation in this area limited
by RDS(on)
5
td(off) tf
Fig. 10b - Switching Time Waveforms
2
ID, Drain Current (A)
tr
102
5
10 µs
2
10
100 µs
5
1 ms
2
1
10 ms
5
TC = 25 °C
TJ = 150 °C
Single Pulse
2
0.1
1
2
5
10
2
5
102
2
5
103
VDS, Drain-to-Source Voltage (V)
91053_08
Fig. 7 - Maximum Safe Operating Area
10
ID, Drain Current (A)
8
6
4
2
0
25
91053_09
50
75
100
125
150
TC, Case Temperature (°C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
S21-0853-Rev. C, 16-Aug-2021
Document Number: 91053
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740LC
www.vishay.com
Vishay Siliconix
Thermal Response (ZthJC)
10
1
0 − 0.5
PDM
0.2
0.1
0.05
0.1
t1
t2
0.02
0.01
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
10-2
10-5
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
91053_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
IAS
V DD
VDS
A
10 V
tp
0.01 Ω
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
1200
ID
4.5 A
6.3 A
Bottom 10 A
Top
1000
800
600
400
200
0
VDD = 50 V
25
91053_12c
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
S21-0853-Rev. C, 16-Aug-2021
Document Number: 91053
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740LC
www.vishay.com
Vishay Siliconix
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0853-Rev. C, 16-Aug-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91053
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF740LC
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91053.
S21-0853-Rev. C, 16-Aug-2021
Document Number: 91053
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-220-1
A
E
F
D
H(1)
Q
ØP
3
2
L(1)
1
M*
L
b(1)
C
b
e
J(1)
e(1)
MILLIMETERS
DIM.
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.24
4.65
0.167
0.183
b
0.69
1.02
0.027
0.040
b(1)
1.14
1.78
0.045
0.070
c
0.36
0.61
0.014
0.024
D
14.33
15.85
0.564
0.624
E
9.96
10.52
0.392
0.414
e
2.41
2.67
0.095
0.105
e(1)
4.88
5.28
0.192
0.208
F
1.14
1.40
0.045
0.055
H(1)
6.10
6.71
0.240
0.264
J(1)
2.41
2.92
0.095
0.115
L
13.36
14.40
0.526
0.567
L(1)
3.33
4.04
0.131
0.159
ØP
3.53
3.94
0.139
0.155
Q
2.54
3.00
0.100
0.118
ECN: E21-0621-Rev. D, 04-Nov-2021
DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
Document Number: 66542
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revison: 04-Nov-2021
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Vishay
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Revision: 01-Jan-2022
1
Document Number: 91000