IRF840B
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Vishay Siliconix
D Series Power MOSFET
FEATURES
D
• Optimal design
- Low area specific on-resistance
- Low input capacitance (Ciss)
Available
- Reduced capacitive switching losses
- High body diode ruggedness
- Avalanche energy rated (UIS)
• Optimal efficiency and operation
- Low cost
- Simple gate drive circuitry
- Low figure-of-merit (FOM): Ron x Qg
- Fast switching
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
TO-220AB
G
G
D
S
S
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) max. (Ω) at 25 °C
550
VGS = 10 V
Qg max. (nC)
0.85
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
30
Qgs (nC)
4
Qgd (nC)
7
Configuration
Single
APPLICATIONS
• Consumer electronics
- Displays (LCD or plasma TV)
• Server and telecom power supplies
- SMPS
• Industrial
- Welding
- Induction heating
- Motor drives
• Battery chargers
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and halogen-free
TO-220AB
IRF840BPbF
IRF840BPbF-BE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source Voltage
Gate-source voltage AC (f > 1 Hz)
Continuous drain current (TJ = 150 °C)
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
current a
Pulsed drain
Linear derating factor
Single pulse avalanche energy b
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
Reverse diode dV/dt d
Soldering recommendations (peak temperature) c
ID
IDM
EAS
PD
TJ, Tstg
TJ = 125 °C
For 10 s
dV/dt
LIMIT
500
± 30
30
8.7
5.5
18
1.25
56
156
-55 to +150
24
0.37
300
UNIT
V
A
W/°C
mJ
W
°C
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 Ω, IAS = 7 A
c. 1.6 mm from case
d. ISD ≤ ID, starting TJ = 25 °C
S21-1262-Rev. B, 27-Dec-2021
Document Number: 91521
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840B
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Maximum junction-to-case (drain)
RthJC
-
0.8
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 250 μA
-
0.58
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
3
-
5
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate boltage drain current
IDSS
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
10
-
0.70
0.85
Ω
S
Drain-source on-state resistance
Forward
transconductance a
RDS(on)
VGS = 10 V
ID = 4 A
gfs
VDS = 20 V, ID = 4 A
-
3
-
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
527
-
-
52
-
-
8
-
-
46
-
-
64
-
μA
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Effective output capacitance,
energy related b
Co(er)
Effective output capacitance,
time related c
Co(tr)
pF
VDS = 0 V to 400 V, VGS = 0 V
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
-
15
30
-
4
-
Qgd
-
7
-
td(on)
-
13
26
tr
-
16
32
-
17
34
-
11
22
-
1.8
-
-
-
8
-
-
32
-
-
1.2
-
308
-
ns
-
1.8
-
μC
-
11
-
A
td(off)
Fall time
tf
Gate input resistance
Rg
VGS = 10 V
ID = 4 A, VDS = 400 V
VDD = 400 V, ID = 4 A
Rg = 9.1 Ω, VGS = 10 V
f = 1 MHz, open drain
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 4 A, VGS = 0 V
TJ = 25 °C, IF = IS = 4 A,
dI/dt = 100 A/μs, VR = 20 V
S
V
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
c. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
S21-1262-Rev. B, 27-Dec-2021
Document Number: 91521
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840B
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
16
12
TJ = 25 °C
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
20
8
4
2.5
2
1.5
1
VGS = 10 V
0.5
0
0
5
10
15
20
25
ID = 4 A
0
- 60 - 40 - 20 0
30
VDS, Drain-to-Source Voltage (V)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
1000
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
12
9
Ciss
TJ = 150 °C
Capacitance (pF)
ID, Drain-to-Source Current (A)
15
6
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
100
Crss
10
3
0
1
0
5
10
15
20
25
30
0
VDS, Drain-to-Source Voltage (V)
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
20
24
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
16
12
8
TJ = 150 °C
4
TJ = 25 °C
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
16
12
8
4
0
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-1262-Rev. B, 27-Dec-2021
25
0
5
10
15
20
25
Qg, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91521
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840B
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Vishay Siliconix
10
ISD, Reverse Drain Current (A)
100
ID, Drain Current (A)
TJ = 150 °C
TJ = 25 °C
10
1
8
6
4
2
VGS = 0 V
0
0.1
0.2
0.4
0.6
0.8
1
1.2
1.4
25
1.6
VSD, Source-Drain Voltage (V)
50
75
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
100
625
Operation in this area limited by RDS(on)
100 μs
1
1 ms
Limited by R DS(on)*
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
VDS, Drain-to-Source
Breakdown Voltage (V)
ID, Drain Current (A)
600
10
575
550
525
500
BVDSS Limited
0.01
475
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Maximum Safe Operating Area
Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S21-1262-Rev. B, 27-Dec-2021
Document Number: 91521
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840B
www.vishay.com
Vishay Siliconix
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
10 %
VGS
+
D.U.T.
td(on)
-
VDS
td(off) tf
tr
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
L
Vary tp to obtain
required IAS
VDS
Fig. 17 - Gate Charge Test Circuit
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S21-1262-Rev. B, 27-Dec-2021
Document Number: 91521
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840B
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91521.
S21-1262-Rev. B, 27-Dec-2021
Document Number: 91521
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-220-1
A
E
F
D
H(1)
Q
ØP
3
2
L(1)
1
M*
L
b(1)
C
b
e
J(1)
e(1)
MILLIMETERS
DIM.
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.24
4.65
0.167
0.183
b
0.69
1.02
0.027
0.040
b(1)
1.14
1.78
0.045
0.070
c
0.36
0.61
0.014
0.024
D
14.33
15.85
0.564
0.624
E
9.96
10.52
0.392
0.414
e
2.41
2.67
0.095
0.105
e(1)
4.88
5.28
0.192
0.208
F
1.14
1.40
0.045
0.055
H(1)
6.10
6.71
0.240
0.264
J(1)
2.41
2.92
0.095
0.115
L
13.36
14.40
0.526
0.567
L(1)
3.33
4.04
0.131
0.159
ØP
3.53
3.94
0.139
0.155
Q
2.54
3.00
0.100
0.118
ECN: E21-0621-Rev. D, 04-Nov-2021
DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
Document Number: 66542
1
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revison: 04-Nov-2021
Legal Disclaimer Notice
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Vishay
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Revision: 01-Jan-2022
1
Document Number: 91000