IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
D2PAK (TO-263)
I2PAK (TO-262)
S
•
•
•
•
•
•
•
•
D
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
G
G
G
D
S
D
S
P-Channel MOSFET
PRODUCT SUMMARY
VDS (V)
DESCRIPTION
-60
RDS(on) (Ω)
VGS = -10 V
Qg max. (nC)
12
3.8
Qgd (nC)
Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D2PAK is a surface-mount power package capable of
accommodating die size up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface-mount package. The
D2PAK is suitable for high current applications because of is
low internal connection resistance and can dissipate up to
2.0 W in a typical surface mount application.
The through-hole version (IRF9Z14L, SiHF9Z14L) is
available for low-profile applications.
0.50
Qgs (nC)
5.1
Configuration
Advanced process technology
Surface-mount (IRF9Z14S, SiHF9Z14S)
Low-profile through-hole (IRF9Z14L, SiHF9Z14L) Available
175 °C operating temperature
Fast switching
Available
P-channel
Fully avalanche rated
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Single
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHF9Z14S-GE3
IRF9Z14SPbF
IRF9Z14STRRPbF
D2PAK (TO-263)
SiHF9Z14STRL-GE3 a
IRF9Z14STRLPbF a
-
I2PAK (TO-262)
SiHF9Z14L-GE3
IRF9Z14LPbF
-
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current e
SYMBOL
VDS
VGS
VGS at -10 V
TC = 25 °C
TC = 100 °C
Current a, e
IDM
Pulsed Drain
Linear Derating Factor
Single Pulse Avalanche Energy b, e
Avalanche Current a
Repetiitive Avalanche Energy a
Maximum Power Dissipation
ID
EAS
IAR
EAR
TC = 25 °C
TA = 25 °C
PD
dV/dt
Peak Diode Recovery dV/dt c, e
Operating Junction and Storage Temperature Range
TJ, Tstg
For 10 s
Soldering Recommendations (Peak temperature) d
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = -25 V, starting TJ = 25 °C, L = 3.6 mH, Rg = 25 Ω, IAS = -6.7 A (see fig. 12)
c. ISD ≤ -6.7 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
d. 1.6 mm from case
e. Uses IRF9Z14, SiHF9Z14 data and test conditions
S21-0904-Rev. D, 30-Aug-2021
LIMIT
-60
± 20
-6.7
-4.7
-27
0.29
140
-6.7
4.3
43
3.7
-4.5
-55 to +175
300
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Document Number: 91089
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient (PCB
Mounted, steady-state)a
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
3.5
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
VDS
VGS = 0, ID = -250 μA
MIN.
TYP.
MAX.
UNIT
-60
-
-
V
-
-0.06
-
V/°C
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
ΔVDS/TJ
Reference to 25 °C, ID = -1
mA c
VGS(th)
VDS = VGS, ID = -250 μA
-2.0
-
-4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = -60 V, VGS = 0 V
-
-
-100
VDS = -48 V, VGS = 0 V, TJ = 150 °C
-
-
-500
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = -4.0 A b
VGS = -10 V
VDS = -25 V, ID = -4.0 A c
μA
-
-
0.5
Ω
1.4
-
-
S
-
270
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = -25 V,
f = 1.0 MHz, see fig. 5 c
-
170
-
-
31
-
-
-
12
-
-
3.8
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
5.1
Turn-On Delay Time
td(on)
-
11
-
tr
-
63
-
-
10
-
-
31
-
Rise Time
Turn-Off Delay Time
td(off)
VGS = -10 V
ID = -6.7 A, VDS = -48 V,
see fig. 6 and 13 b, c
VDD = -30 V, ID = -6.7 A,
Rg = 24 Ω, RD = 4.0 Ω, see fig. 10 b
pF
nC
ns
Fall Time
tf
Gate Input Resistance
Rg
f = 1 MHz, open drain
1.4
-
8.7
Ω
Internal Source Inductance
LS
Between lead, and center of die contact
-
7.5
-
nH
-
-
-6.7
S
-
-
-27
Vb
-
-
-5.5
V
-
80
160
ns
-
96
190
nC
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current a
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = -6.7 A, VGS = 0
TJ = 25 °C, IF = -6.7 A, dI/dt = 100 A/μs b, c
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Uses IRF9Z14, SiHF9Z14 data and test conditions
S21-0904-Rev. D, 30-Aug-2021
Document Number: 91089
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L
www.vishay.com
Vishay Siliconix
VGS
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
Top
- ID, Drain Current (A)
101
100
- 4.5 V
20 µs Pulse Width
TC = 25 °C
10-1
10-1
100
101
- VDS, Drain-to-Source Voltage (V)
91089_01
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40- 20 0 20 40 60 80 100 120 140 160 180
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
600
VGS
- 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom - 4.5 V
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Top
100
480
- 4.5 V
Capacitance (pF)
101
- ID, Drain Current (A)
ID = - 6.7 A
VGS = - 10 V
91089_04
Fig. 1 - Typical Output Characteristics
360
Ciss
Coss
240
120
Crss
20 µs Pulse Width
TC = 175 °C
10-1
10-1
100
0
101
100
- VDS, Drain-to-Source Voltage (V)
91089_02
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
175 °C
100
10-1
20 µs Pulse Width
VDS = - 25 V
- VGS, Gate-to-Source Voltage (V)
20
101
25 °C
101
- VDS, Drain-to-Source Voltage (V)
91089_05
Fig. 2 - Typical Output Characteristics
- ID, Drain Current (A)
3.0
ID = - 6.7 A
VDS = - 48 V
16
VDS = - 30 V
12
8
4
For test circuit
see figure 13
0
4
91089_03
5
6
7
8
9
- VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0904-Rev. D, 30-Aug-2021
10
0
91089_06
3
6
9
12
15
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91089
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L
www.vishay.com
Vishay Siliconix
- ISD, Reverse Drain Current (A)
7.5
- ID, Drain Current (A)
101
175 °C
25 °C
100
VGS = 0 V
10-1
1.0
2.0
3.0
5.0
4.0
3.0
1.5
25
50
75
100
125
150
175
TC, Case Temperature (°C)
91089_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
RD
102
VDS
Operation in this area limited
by RDS(on)
5
- ID, Drain Current (A)
4.5
0.0
6.0
- VSD, Source-to-Drain Voltage (V)
91089_07
6.0
VGS
D.U.T.
Rg
10 µs
+VDD
2
100 µs
- 10 V
10
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
5
1 ms
Fig. 10a - Switching Time Test Circuit
TC = 25 °C
TJ = 175 °C
Single Pulse
2
1
2
1
5
10 ms
td(on)
2
10
5
td(off) tf
tr
VGS
102
10 %
- VDS, Drain-to-Source Voltage (V)
91089_08
Fig. 8 - Maximum Safe Operating Area
90 %
VDS
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
D = 0.5
1
0.2
0.1
PDM
0.05
0.1
Single Pulse
(Thermal Response)
0.02
0.01
t1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5
91089_11
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0904-Rev. D, 30-Aug-2021
Document Number: 91089
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L
www.vishay.com
Vishay Siliconix
L
Vary tp to obtain
required IAS
Current regulator
Same type as D.U.T.
VDS
50 kΩ
D.U.T.
Rg
+ V DD
12 V
0.2 µF
0.3 µF
-
IAS
D.U.T.
- 10 V
0.01 Ω
tp
+ VDS
VGS
- 3 mA
Fig. 12a - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
IAS
Fig. 13b - Gate Charge Test Circuit
VDS
VDD
tp
VDS
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
500
ID
- 2.7 A
- 4.7 A
Bottom - 6.7 A
Top
400
300
200
100
VDD = - 25 V
0
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
91089_12c
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
QG
- 10 V
QGS
QGD
VG
Charge
Fig. 13a - Basic Gate Charge Waveform
S21-0904-Rev. D, 30-Aug-2021
Document Number: 91089
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
• dV/dt controlled by Rg
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Note
• Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91089.
S21-0904-Rev. D, 30-Aug-2021
Document Number: 91089
6
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
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about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
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parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
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Revision: 01-Jan-2022
1
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