IRFBC30ASTRRPBF

IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness • Fully Characterized Capacitance and Avalanche Voltage and Current • Effective Coss Specified • Compliant to RoHS Directive 2002/95/EC 600 RDS(on) () VGS = 10 V 2.2 Qg (Max.) (nC) 23 Qgs (nC) 5.4 Qgd (nC) 11 Configuration Single D I2PAK (TO-262) D2PAK (TO-263) APPLICATIONS G • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High Speed Power Switching G D S TYPICAL SMPS TOPOLOGIES S • Single Transistor Flyback N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262) SiHFBC30AS-GE3 SiHFBC30ASTRL-GE3a SiHFBC30ASTRR-GE3a SiHFBC30AL-GE3 IRFBC30ASPbF IRFBC30ASTRLPbFa IRFBC30ASTRRPbFa IRFBC30ALPbF SiHFBC30AS-E3 SiHFBC30ASTL-E3a SiHFBC30ASTR-E3a SiHFBC30AL-E3 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta, e ID IDM Linear Derating Factor Energyb UNIT V 3.6 2.3 A 14 0.69 W/°C mJ EAS 290 Avalanche Currenta IAR 3.6 A Repetiitive Avalanche Energya EAR 7.4 mJ Single Pulse Avalanche Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc, e Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s PD 74 W dV/dt 7.0 V/ns TJ, Tstg - 55 to + 150 300d °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 46 mH, Rg = 25 , IAS = 3.6 A (see fig. 12). c. ISD  3.6 A, dI/dt  170 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. Uses IRFBC30A/SiHFBC30A data and test conditions. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91109 S11-1052-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mounted, steady-state)a PARAMETER RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 1 mAd - 0.67 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.5 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 600 V, VGS = 0 V - - 25 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 2.2 Ab VGS = 10 V VDS = 50 V, ID = 2.2 A μA - - 2.2  2.1 - - S - 510 - - 70 - - 3.5 - - 730 - Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Effective Output Capacitance Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V Coss eff. Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V VDS = 480 V, f = 1.0 MHz - 19 - VDS = 0 V to 480 Vc - 31 - - - 23 - - 5.4 ID = 3.6 A, VDS = 480 V, see fig. 6 and 13b pF nC Gate-Drain Charge Qgd - - 11 Turn-On Delay Time td(on) - 9.8 - - 13 - - 19 - - 12 - - - 3.6 - - 14 - - 1.6 - 400 600 ns - 1.1 1.7 μC Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 300 V, ID = 3.6 A, Rg = 12 , RD = 82 , see fig. 10b, d tf ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 3.6 A, VGS = 0 Vb TJ = 25 °C, IF = 3.6 A, dI/dt = 100 A/μsb, V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. d. Uses IRFBC30A/SiHFBC30A data and test conditions. www.vishay.com 2 Document Number: 91109 S11-1052-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 10 1 0.1 4.5V 20µs PULSE WIDTH TJ = 25 °C 0.01 0.1 1 10 100 I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 10 TJ = 150 ° C 1 TJ = 25 ° C 0.1 0.01 4.0 Fig. 1 - Typical Output Characteristics I D , Drain-to-Source Current (A) 1 4.5V 20µs PULSE WIDTH TJ = 150 ° C 1 10 Fig. 2 - Typical Output Characteristics Document Number: 91109 S11-1052-Rev. C, 30-May-11 100 RDS(on) , Drain-to-Source On Resistance (Normalized) 3.0 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V VDS , Drain-to-Source Voltage (V) 6.0 7.0 8.0 9.0 Fig. 3 - Typical Transfer Characteristics TOP 0.1 0.1 5.0 VGS , Gate-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) 10 V DS = 50V 20µs PULSE WIDTH ID = 3.6A 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature ( °C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL Vishay Siliconix VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd C, Capacitance(pF) 1000 Ciss 100 Coss 10 ISD , Reverse Drain Current (A) 100 10000 10 TJ = 150° C TJ = 25 ° C 1 Crss 1 1 10 100 0.1 0.4 1000 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage OPERATION IN THIS AREA LIMITED BY RDS(on) VDS = 480V VDS = 300V VDS = 120V 16 12 8 10us 10 100us 1 1ms 4 FOR TEST CIRCUIT SEE FIGURE 13 0 4 8 12 16 20 24 QG , Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 1.2 100 ID = 3.6A 0 1.0 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID , Drain Current (A) VGS , Gate-to-Source Voltage (V) 0.8 VSD ,Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V) 20 V GS = 0 V 0.6 0.1 10ms TC = 25 ° C TJ = 150 ° C Single Pulse 10 100 1000 10000 VDS , Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 91109 S11-1052-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL Vishay Siliconix RD VDS 4.0 VGS D.U.T. ID , Drain Current (A) Rg + - VDD 3.0 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 2.0 Fig. 10a - Switching Time Test Circuit VDS 1.0 90 % 0.0 25 50 75 100 125 10 % VGS 150 TC , Case Temperature ( ° C) td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (Z thJC ) 10 1 D = 0.50 0.20 0.10 PDM 0.05 0.1 t1 0.02 0.01 t2 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp L VDS Rg D.U.T. IAS 20 V tp Driver + A - VDD IAS 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91109 S11-1052-Rev. C, 30-May-11 Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL 400 TOP BOTTOM ID 1.6A 2.3A 3.6A 300 200 100 740 V DSav , Avalanche Voltage ( V ) EAS , Single Pulse Avalanche Energy (mJ) Vishay Siliconix 720 700 680 660 640 0.0 0 25 50 75 100 125 1.0 150 Starting TJ , Junction Temperature ( °C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current 2.0 3.0 4.0 IAV , Avalanche Current ( A) Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanache Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91109 S11-1052-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30AS, SiHFBC30AS, IRFBC30AL, SiHFBC30AL Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91109. Document Number: 91109 S11-1052-Rev. C, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-220AB MILLIMETERS A E F D H(1) Q ØP 3 2 L(1) 1 M* L b(1) INCHES DIM. MIN. MAX. MIN. MAX. A 4.25 4.65 0.167 0.183 b 0.69 1.01 0.027 0.040 b(1) 1.20 1.73 0.047 0.068 c 0.36 0.61 0.014 0.024 D 14.85 15.49 0.585 0.610 D2 12.19 12.70 0.480 0.500 E 10.04 10.51 0.395 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 F 1.14 1.40 0.045 0.055 H(1) 6.09 6.48 0.240 0.255 0.115 J(1) 2.41 2.92 0.095 L 13.35 14.02 0.526 0.552 L(1) 3.32 3.82 0.131 0.150 ØP 3.54 3.94 0.139 0.155 Q 2.60 3.00 0.102 0.118 ECN: T14-0413-Rev. P, 16-Jun-14 DWG: 5471 Note * M = 1.32 mm to 1.62 mm (dimension including protrusion) Heatsink hole for HVM C b e J(1) e(1) D2 Document Number: 71195 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revison: 16-Jun-14 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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