IRFBC30STRLPBF

IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount (IRFBC30S, SiHFBC30S) • Low-Profile Through-Hole (IRFBC30L, SiHFBC30L) • Available in Tape and Reel (IRFBC30S, SiHFBC30S) • Dynamic dV/dt Rating • 150 °C Operating Temperature • Fast Switching • Fully Avalanche Rated • Compliant to RoHS Directive 2002/95/EC 600 RDS(on) () VGS = 10 V 2.2 Qg (Max.) (nC) 31 Qgs (nC) 4.6 Qgd (nC) 17 Configuration Single D G G DESCRIPTION D2PAK (TO-263) I2PAK (TO-262) D S Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capable of the accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (IRFBC30L, SiHFBC30L) is a available for low-profile applications. G D S S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) SiHFBC30S-GE3 IRFBC30SPbF SiHFBC30S-E3 D2PAK (TO-263) SiHFBC30STRL-GE3a IRFBC30STRLPbFa SiHFBC30STL-E3a I2PAK (TO-262) SiHFBC30L-GE3 IRFBC30LPbF SiHFBC30L-E3 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage SYMBOL VDS VGS Continuous Drain Currente VGS at 10 V TC = 25 °C TC = 100 °C Currenta, e IDM Pulsed Drain Linear Derating Factor Single Pulse Avalanche Energyb, e Avalanche Currenta Repetiitive Avalanche Energya Maximum Power Dissipation dV/dtc, e Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) ID EAS IAR EAR TA = 25 °C TC = 25 °C PD dV/dt TJ, Tstg for 10 s LIMIT 600 ± 20 3.6 2.3 14 0.59 290 3.6 7.4 3.1 74 3.0 - 55 to + 150 300d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 41 mH, Rg = 25 , IAS = 3.6 A (see fig. 12). c. ISD  3.6 A, dI/dt  60 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. Uses IRFBC30, SiHFBC30 data and test conditions. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91111 S11-1053-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mounted, steady-state)a PARAMETER RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). For recommended footprint and soldering techniques refer to application note #AN-994. SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS VDS VGS = 0, ID = 250 μA MIN. TYP. MAX. UNIT 600 - - V Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS/TJ VGS(th) Reference to 25 °C, ID = 1 - 0.62 - V/°C VDS = VGS, ID = 250 μA 2.0 - 4.0 V nA IGSS IDSS RDS(on) gfs mAc VGS = ± 20 V - - ± 100 VDS = 600 V, VGS = 0 V - - 100 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 500 - - 2.2  2.5 - - S ID = 2.2 Ab VGS = 10 V VDS = 50 V, ID = 2.2 Ac μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5c VGS = 10 V ID = 3.6 A, VDS = 360 V, see fig. 6 and 13b, c - 660 - - 86 - - 19 - - - 31 - - 4.6 Gate-Drain Charge Qgd - - 17 Turn-On Delay Time td(on) - 11 - VDD = 300 V, ID = 3.6 A, Rg = 12 , RD = 82 , see fig. 10b, c - 13 - - 35 - - 14 - Between lead, and center of die contcat - 7.5 - - - 3.6 - - 14 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Internal Source Inductance LS pF nC ns nH Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 3.6 A, VGS = 0 S Vb TJ = 25 °C, IF = 3.6 A, dI/dt = 100 A/μsb, c - - 1.6 V - 370 810 ns - 2.0 4.2 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. c. Uses IRFBC30, SiHFBC30 data and test conditions. www.vishay.com 2 Document Number: 91111 S11-1053-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91111 S11-1053-Rev. C, 30-May-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91111 S11-1053-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix RD VDS VGS D.U.T. Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS VDS VDS tp VDD Rg D.U.T. + - I AS V DD VDS 10 V tp 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91111 S11-1053-Rev. C, 30-May-11 IAS Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Maximum Avalanche Energy vs. Drain Current www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91111 S11-1053-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91111. Document Number: 91111 S11-1053-Rev. C, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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