IRFD224
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
D
• Dynamic dV/dt rating
HVMDIP
• Repetitive avalanche rated
• For automatic Insertion
G
• End stackable
• Fast switching
S
G
• Ease of paralleling
S
D
• Simple drive requirements
N-Channel MOSFET
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
VDS (V)
DESCRIPTION
250
RDS(on) (Ω)
VGS = 10 V
Qg (Max.) (nC)
14
Qgs (nC)
2.7
Qgd (nC)
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
1.1
7.8
Configuration
The 4 pin DIP package is a low cost machine-insertiable
case style which can be stacked in multiple combinations on
standard 0.1" pin centers. The dual drain serveres as a
thermal link to the mounting surface for power dissipation
levels up to 1 W.
Single
ORDERING INFORMATION
Package
HVMDIP
Lead (Pb)-free
IRFD224PbF
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
250
Gate-source voltage
VGS
± 20
VGS at -10 V
Continuous drain current
TA = 25 °C
TA = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
Single pulse avalanche energy
b
Repetitive avalanche current a
Repetitive avalanche
energy a
TA = 25 °C
Maximum power dissipation
Peak diode recovery dv/dt
c
Operating junction and storage temperature range
Soldering rRecommendations (peak temperature)
d
For 10 s
UNIT
V
0.63
0.40
A
5.0
0.0083
W/°C
EAS
60
mJ
IAR
0.63
A
EAR
0.10
mJ
PD
1.0
W
dV/dt
4.8
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 15 mH, Rg = 25 Ω, IAS = 2.5 A (see fig. 12)
c. ISD ≤ 4.4 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
S21-0885-Rev. D, 30-Aug-2021
Document Number: 91132
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD224
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
SYMBOL
TYP.
MAX.
UNIT
RthJA
-
120
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 μA
250
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.36
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 250 V, VGS = 0 V
-
-
25
VDS = 200 V, VGS = 0 V, TJ = 125 °C
-
-
250
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 0.38 Ab
VGS = 10 V
VDS = 50 V, ID = 2.6 A
μA
-
-
1.1
Ω
1.5
-
-
S
-
260
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
77
-
-
15
-
-
-
14
-
-
2.7
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
7.8
Turn-On Delay Time
td(on)
-
7.0
-
tr
-
13
-
-
20
-
-
12
-
-
4.0
-
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
VGS = 10 V
ID = 4.4 A, VDS = 200 V,
see fig. 6 and 13b
VDD = 125 V, ID = 4.4 A,
Rg = 18 Ω, RD = 28 Ω, see fig. 10b
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
-
6.0
-
-
-
0.63
-
-
5.0
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 0.63 A, VGS = 0 Vb
TJ = 25 °C, IF = 4.4 A, dI/dt = 100 A/μsb
-
-
1.8
V
-
200
400
ns
-
0.93
1.9
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
S21-0885-Rev. D, 30-Aug-2021
Document Number: 91132
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD224
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TA = 25 °C
Fig. 1 - Typical Output Characteristics, TA = 25 °C
Fig. 2 - Typical Transfer Characteristics
TA = 150 °C
Fig. 1 - Typical Output Characteristics, TA = 150 °C
S21-0885-Rev. D, 30-Aug-2021
Fig. 3 - Normalized On-Resistance vs. Temperature
Document Number: 91132
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD224
www.vishay.com
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
Vishay Siliconix
Fig. 6 - Typical Source-Drain Diode Forward Voltage
TA = 25 °C
TJ = 150 °C
SINGLE PULSE
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0885-Rev. D, 30-Aug-2021
Fig. 7 - Maximum Safe Operating Area
Document Number: 91132
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD224
www.vishay.com
Vishay Siliconix
VDS
VGS
RD
D.U.T.
Rg
+
- VDD
ID, Drain Current (A)
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
TA, Ambient Temperature (°C)
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJA)
Fig. 8 - Maximum Drain Current vs. Ambient Temperature
t1, Rectangular Pulse Duration (s)
Fig. 9 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
S21-0885-Rev. D, 30-Aug-2021
Document Number: 91132
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD224
www.vishay.com
Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
Rg
+
-
I AS
V DD
VDS
10 V
0.01 W
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0885-Rev. D, 30-Aug-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91132
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFD224
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
•
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 10 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91132.
S21-0885-Rev. D, 30-Aug-2021
Document Number: 91132
7
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
HVM DIP (High voltage)
0.248 [6.29]
0.240 [6.10]
0.043 [1.09]
0.035 [0.89]
0.197 [5.00]
0.189 [4.80]
0.133 [3.37]
0.125 [3.18]
0.180 [4.57]
0.160 [4.06]
0.094 [2.38]
0.086 [2.18]
A
L
0.160 [4.06]
0.140 [3.56]
0° to 15°
2x
0.017 [0.43]
0.013 [0.33]
0.045 [1.14]
2 x 0.035 [0.89]
E min.
0.024 [0.60]
4x
0.020 [0.51]
0.100 [2.54] typ.
E max.
INCHES
MILLIMETERS
DIM.
MIN.
MAX.
MIN.
A
0.310
0.330
7.87
MAX.
8.38
E
0.300
0.425
7.62
10.79
L
0.270
0.290
6.86
7.36
ECN: X10-0386-Rev. B, 06-Sep-10
DWG: 5974
Note
1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
Document Number: 91361
Revision: 06-Sep-10
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1
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Revision: 01-Jan-2022
1
Document Number: 91000