IRFI510G, SiHFI510G
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Isolated Package
• High Voltage Isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
• Sink to Lead Creepage Distance = 4.8 mm
• 175 °C Operating Temperature
• Dynamic dV/dt Rating
• Low Thermal Resistance
• Compliant to RoHS Directive 2002/95/EC
100
RDS(on) ()
VGS = 10 V
0.54
Qg (Max.) (nC)
8.3
Qgs (nC)
2.3
Qgd (nC)
3.8
Configuration
Single
TO-220 FULLPAK
RoHS*
COMPLIANT
DESCRIPTION
D
Third Generation Power MOSFETs from Vishay provides the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost
effectiveness.
The TO-220 FULLPAK eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab and
external heatsink. This isolation is equivalent to using a 100
micron mica barrier with standard TO-220 product. The
FULLPAK is mounted to a heatsink using a single clip or by
a single screw fixing.
G
S
G D S
Available
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-220 FULLPAK
IRFI510GPbF
SiHFI510G-E3
IRFI510G
SiHFI510G
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
VDS
VGS
100
± 20
4.5
3.2
18
0.18
60
4.5
2.7
27
4.5
- 55 to + 175
300d
10
1.1
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
TC = 25 °C
for 10 s
6-32 or M3 screw
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 4.4 mH, Rg = 25 , IAS = 4.5 A (see fig. 12).
c. ISD 5.6 A, dI/dt 75 A/s, VDD VDS, TJ 175 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
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1
IRFI510G, SiHFI510G
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
5.5
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 μA
100
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.63
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
IGSS
VGS = 20
-
-
100
nA
VDS = 100 V, VGS = 0 V
-
-
25
VDS = 80 V, VGS = 0 V, TJ = 150 °C
-
-
250
-
-
0.54
1.2
-
-
S
IDSS
RDS(on)
gfs
ID = 2.7 Ab
VGS = 10 V
VDS = 50 V, ID = 2.7
Ab
μA
Dynamic
Input Capacitance
Ciss
VGS = 0 V
-
180
-
Output Capacitance
Coss
VDS = 25 V
-
81
-
Reverse Transfer Capacitance
Crss
f = 1.0 MHz, see fig. 5
-
15
-
Drain to Sink Capacitance
C
f = 1.0 MHz
-
12
-
Total Gate Charge
Qg
-
-
8.3
-
-
2.3
VGS = 10 V
ID = 5.6 A, VDS = 80 V,
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
3.8
Turn-On Delay Time
td(on)
-
6.9
-
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
see fig. 6 and 13b
pF
nC
VDD = 50 V, ID = 5.6 A
-
16
-
Rg = 24 , RD = 8.4, see fig. 10b
-
15
-
-
9.4
-
-
4.5
-
-
7.5
-
-
-
4.5
-
-
18
-
-
2.5
V
-
100
200
ns
-
0.44
0.88
μC
Between lead,
6 mm (0.25") from
package and center of
die contact
D
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 4.5 A, VGS = 0 Vb
TJ = 25 °C, IF = 5.6 A, di/dt = 100 A/μsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
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Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
IRFI510G, SiHFI510G
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 175 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
www.vishay.com
3
IRFI510G, SiHFI510G
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
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Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
IRFI510G, SiHFI510G
Vishay Siliconix
RD
VDS
VGS
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
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5
IRFI510G, SiHFI510G
Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
Rg
+
-
IAS
V DD
A
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
+
QGD
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
IRFI510G, SiHFI510G
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90178.
Document Number: 90178
S10-2325-Rev. B, 11-Oct-10
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Package Information
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Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Revision: 09-Jul-2021
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Document Number: 91000
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