IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Super Fast Body Diode Eliminates the Need for
External Diodes in ZVS Applications
500
RDS(on) (Ω)
VGS = 10 V
0.67
RoHS
COMPLIANT
Qg (Max.) (nC)
45
Qgs (nC)
13
• Lower Gate Charge Results in Simpler Drive
Reqirements
Qgd (nC)
23
• Enhanced dV/dt Capabilities Offer Improved Ruggedness
Configuration
Single
• Higher Gate Voltage Threshold Offers Improved Noise
Immunity
D
TO-220 FULLPAK
• Lead (Pb)-free
APPLICATIONS
G
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
G D S
• Uninterruptible Power Supplies
S
• Motor Control Applications
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-220 FULLPAK
IRFIB5N50LPbF
SiHFIB5N50L-E3
Lead (Pb)-free
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Single Pulse Avalanche Energyb
Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
TC = 25 °C
for 10 s
6-32 or M3 screw
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
LIMIT
500
± 30
4.7
3.0
16
0.33
140
4.0
3.0
42
19
- 55 to + 150
300d
10
1.1
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 18 mH, RG = 25 Ω, IAS = 4.0 A, dV/dt = 19 V/ns, (see fig. 17).
c. ISD ≤ 4.0 A, dI/dt ≤ 421 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
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IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
SYMBOL
TYP.
MAX.
UNIT
RthJA
RthJC
-
65
3.0
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.43
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
3.0
-
5.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
50
µA
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
2.0
mA
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
-
0.67
0.80
Ω
gfs
VDS = 50 V, ID = 2.4 A
2.8
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1000
-
-
110
-
RDS(on)
Forward Transconductance
ID = 2.4 Ab
VGS = 10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Coss
Coss eff.
Effective Output Capacitance
Effective Output Capacitance
(Energy Related)
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Internal Gate Resistance
RG
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
12
-
1360
-
VDS = 400 V, f = 1.0 MHz
-
31
-
-
75
-
-
55
-
VGS = 0 V
VDS = 0 V to 400 Vc
Coss eff. (ER)
Total Gate Charge
-
VDS = 1.0 V, f = 1.0 MHz
VGS = 10 V
ID = 4.0 A, VDS = 400 V,
see fig. 7 and 16b
f = 1 MHz, open drain
td(on)
tr
td(off)
VDD = 250 V, ID = 4.0 A,
RG = 9.0 Ω, VGS = 10 V,
see fig. 11a and 11bb
tf
-
-
45
-
-
13
23
-
-
-
2.0
-
-
13
-
-
17
-
-
26
-
-
10
-
-
-
4.7
-
-
16
pF
nC
Ω
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
G
TJ = 25 °C, IS = 4.0 A, VGS = 0
A
S
Vb
-
-
1.5
-
73
110
-
99
150
Body Diode Reverse Recovery Time
trr
TJ = 25 °C, IF = 4.0 A,
TJ = 125 °C, dI/dt = 100 A/µsb
Body Diode Reverse Recovery Charge
Qrr
TJ = 25 °C, IS = 4.0 A,
TJ = 125 °C, dI/dt = 100 A/µsb
-
200
310
-
360
540
IRRM
TJ = 25 °C
-
6.7
10
V
ns
nC
Drain-Source Body Diode Characteristics
Body Diode Reverse Recovery Current
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Forward Turn-On Time
ton
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
10
BOTTOM
1
TJ = 150
10
I D, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
0.1
5.5V
0.01
°C
TJ = 25 ° C
1
0.1
20µs PULSE WIDTH
Tj = 25°C
V DS= 50V
20µs PULSE WIDTH
0.001
0.01
0.1
1
10
5.0
100
6.0
Fig. 1 - Typical Output Characteristics
3.0
1
5.5V
0.1
20µs PULSE WIDTH
Tj = 150°C
0.01
0.1
1
10
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
9.0
I D = 4.0A
2.5
100
2.0
(Normalized)
BOTTOM
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (A)
10
8.0
Fig. 3 - Typical Transfer Characteristics
100
TOP
7.0
V GS, Gate-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
160
°
Tj, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
12
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
VDS = 400V
VDS = 250V
VDS = 100V
10
Coss = Cds + Cgd
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
10000
I D = 4.0A
Ciss
1000
Coss
100
Crss
10
1
8
6
4
2
0
1
10
100
1000
0
5
10
15
20
25
30
35
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
10
100
9
8
I SD , Reverse Drain Current (A)
Energy (µJ)
7
6
5
4
3
2
10
T J= 25 ° C
TJ = 150
°C
1
1
V GS = 0 V
0
0.1
0
100
200
300
400
500
600
0.2
0.4
0.6
0.8
1.0
1.2
V SD,Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS
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Fig. 8 - Typical Source-Drain Diode Forward Voltage
Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
ID, Drain-to-Source Current (A)
100
OPERATION IN THIS AREA
LIMITED BY R DS(on)
RD
VDS
VGS
D.U.T.
RG
10
+
- VDD
10 V
100µsec
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1
10msec
0.1
1
Fig. 11a - Switching Time Test Circuit
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
10
100
1000
VDS
90 %
10000
VDS, Drain-to-Source Voltage (V)
Fig. 9 - Maximum Safe Operating Area
10 %
VGS
5.0
t d(on)
tr
t d(off) t f
4.0
ID , Drain Current (A)
Fig. 11b - Switching Time Waveforms
3.0
2.0
1.0
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
Fig. 10 - Maximum Drain Current vs. Case Temperature
(Z thJC )
10
D = 0.50
1
Thermal Response
0.20
0.10
0.05
P DM
0.1
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 / t 2
J = P DM x Z thJC
+TC
1
10
t 1, Rectangular Pulse Duration (sec)
Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
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IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
VGS(th) Gate threshold Voltage (V)
6.0
V DS
tp
5.0
ID = 250µA
4.0
I AS
3.0
Fig. 15b - Unclamped Inductive Waveforms
2.0
-75
-50
-25
0
25
50
75
100
125
QG
150
T J , Temperature ( °C )
10 V
QGS
Fig. 13 - Threshold Voltage vs. Temperature
VG
320
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP
1.8A
BOTTOM
2.5A
4.0A
Q GD
Charge
240
Fig. 16a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
160
50 kΩ
12 V
80
0.2 µF
0.3 µF
D.U.T.
+
V
- DS
0
25
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
VGS
3 mA
Fig. 14 - Maximum Avalanche Energy vs. Drain Current
IG
ID
Current sampling resistors
Fig. 16b - Gate Charge Test Circuit
15 V
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
A
0.01 Ω
Fig. 15a - Unclamped Inductive Test Circuit
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Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
IRFIB5N50L, SiHFIB5N50L
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Body diode
VDD
forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 17 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91173.
Document Number: 91173
S09-0063-Rev. A, 02-Feb-09
www.vishay.com
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Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
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therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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