IRFIB5N65A
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Power MOSFET
FEATURES
D
TO-220 FULLPAK
• Low gate charge Qg results in simple drive
requirement
• Improved gate, avalanche and dynamic dV/dt
ruggedness
G
• Fully characterized capacitance and avalanche voltage
and current
G
D
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
APPLICATIONS
• Switch mode power supply (SMPS)
PRODUCT SUMMARY
VDS (V)
• Uninterruptible power supply
650
RDS(on) (Ω)
VGS = 10 V
• High speed power switching
0.93
• High voltage isolation = 2.5 kVRMS (t = 60 s, f = 60 Hz)
Qg (Max.) (nC)
48
Qgs (nC)
12
TYPICAL SMPS TOPOLOGIES
Qgd (nC)
19
• Single transistor flyback
Configuration
Single
• Single transistor forward
ORDERING INFORMATION
Package
TO-220 FULLPAK
Lead (Pb)-free
IRFIB5N65APbF
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
650
Gate-source voltage
VGS
± 30
Continuous drain current e
Continuous drain current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
UNIT
V
5.1
3.2
A
21
0.48
W/°C
EAS
325
mJ
current a
IAR
5.2
A
Repetitive avalanche energy a
EAR
6
mJ
Single pulse avalanche energy b
Repetitive avalanche
Maximum power dissipation
TC = 25 °C
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
Mounting torque
PD
60
W
dV/dt
2.8
V/ns
TJ, Tstg
-55 to +150
For 10 s
300
M3 screw
0.6
°C
Nm
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 24 mH, RG = 25 Ω, IAS = 5.2 A (see fig. 12)
c. ISD ≤ 5.2 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
e. Drain current limited by maximum junction temperature
S21-0975-Rev. D, 11-Oct-2021
Document Number: 91174
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
65
Maximum junction-to-case (drain)
RthJC
-
2.1
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
VDS
VGS = 0 V, ID = 250 μA
MIN.
TYP.
MAX.
UNIT
650
-
-
V
-
670
-
mV/°C
Static
Drain-ssource breakdown voltage
VDS temperature coefficient
ΔVDS/TJ
Reference to 25 °C, ID = 1
mAd
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 650 V, VGS = 0 V
-
-
25
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
250
Gate-source threshold voltage
Drain-source on-state resistance
Forward transconductance
RDS(on)
gfs
ID = 3.1 A b
VGS = 10 V
VDS = 50 V, ID = 3.1 A
μA
-
-
0.93
Ω
3.9
-
-
S
-
1417
-
-
177
-
-
7.0
-
-
1912
-
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Output capacitance
Effective output capacitance
Total gate charge
Coss
Gate-drain charge
Qgd
Turn-on delay time
td(on)
Fall time
VGS = 0 V
VDS = 520 V, f = 1.0 MHz
-
48
-
VDS = 0 V to 520 V c
-
84
-
-
-
48
-
-
12
-
-
19
-
14
-
Qg
Qgs
Rise time
VDS = 1.0 V, f = 1.0 MHz
Coss eff.
Gate-source charge
Turn-off delay time
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
tr
td(off)
VGS = 10 V
ID = 5.2 A, VDS = 400 V
see fig. 6 and 13 b
VDD = 325 V, ID = 5.2 A
RG = 9.1 Ω, RD = 62 Ω,
see fig. 10 b
tf
pF
nC
-
20
-
-
34
-
-
18
-
-
-
5.2
-
-
21
-
-
1.5
-
493
739
ns
-
2.1
3.2
μC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current a
ISM
Body diode voltage
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 5.2 A, VGS = 0 V b
TJ = 25 °C, IF = 5.2 A, dI/dt = 100 A/μs b
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS
d. t = 60 s, f = 60 Hz
S21-0975-Rev. D, 11-Oct-2021
Document Number: 91174
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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
1
20µs PULSE WIDTH
4.5V TJ = 25 °C
0.1
0.1
1
10
10
TJ = 150 ° C
TJ = 25 ° C
1
0.1
4.0
100
VDS , Drain-to-Source Voltage (V)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
3.0
4.5V
1
20µs PULSE WIDTH
TJ = 150 ° C
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
10
1
6.0
7.0
8.0
9.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.1
5.0
VGS , Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
100
V DS = 100V
20µs PULSE WIDTH
ID = 5.2A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
S21-0975-Rev. D, 11-Oct-2021
Document Number: 91174
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IRFIB5N65A
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2000
100
ISD , Reverse Drain Current (A)
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
1600
C, Capacitance (pF)
Vishay Siliconix
iss
1200
oss
800
400
rss
0
10
100
TJ = 150 ° C
1
TJ = 25 ° C
0.1
0.2
A
1
10
1000
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
0.8
1.0
1.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
ID = 5.2A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 520V
VDS = 325V
VDS = 130V
16
10us
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
0.6
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
20
V GS = 0 V
0.4
12
8
10
100us
1ms
1
10ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
20
30
40
50
0.1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
S21-0975-Rev. D, 11-Oct-2021
10000
Document Number: 91174
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Vishay Siliconix
RD
VDS
6.0
VGS
D.U.T.
RG
5.0
+
ID , Drain Current (A)
- VDD
4.0
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
3.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS
90 %
1.0
0.0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
10 %
VGS
t d(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
t d(off) t f
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
PDM
0.05
0.1
t1
0.02
t2
0.01
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0975-Rev. D, 11-Oct-2021
Document Number: 91174
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IRFIB5N65A
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Vishay Siliconix
800
Driver
L
VDS
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
V DSav , Avalanche Voltage (V)
15 V
A
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
V DS
780
760
740
720
700
A
0
tp
1
2
3
4
5
6
I av , Avalanche Current (A)
Fig. 12d - Typical Drain-to Source Voltage vs.
Avalanche Current
I AS
QG
Fig. 12b - Unclamped Inductive Waveforms
10 V
EAS , Single Pulse Avalanche Energy (mJ)
QGS
800
TOP
BOTTOM
ID
2.3A
3.3A
5.2A
Q GD
VG
600
Charge
Fig. 13a - Basic Gate Charge Waveform
400
Current regulator
Same type as D.U.T.
200
50 kΩ
0
12 V
25
50
75
100
125
0.2 µF
0.3 µF
150
+
Starting TJ , Junction Temperature ( °C)
D.U.T.
-
VDS
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
VGS
3 mA
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
S21-0975-Rev. D, 11-Oct-2021
Document Number: 91174
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IRFIB5N65A
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91174.
S21-0975-Rev. D, 11-Oct-2021
Document Number: 91174
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Package Information
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Vishay Siliconix
TO-220 FULLPAK (High Voltage)
OPTION 1: FACILITY CODE = 9
A
F
G
Q1
E
D
ØR
A3
L1
3 x b2
3 x b1
Mold flash
bleeding
Q
L
Exposed Cu
3xb
2xe
C
Bottom view
MILLIMETERS
DIM.
MIN.
NOM.
A
4.60
4.70
4.80
b
0.70
0.80
0.91
b1
1.20
1.30
1.47
b2
1.10
1.20
1.30
C
0.45
0.50
0.63
D
15.80
15.87
15.97
e
MAX.
2.54 BSC
E
10.00
10.10
F
2.44
2.54
10.30
2.64
G
6.50
6.70
6.90
L
12.90
13.10
13.30
L1
3.13
3.23
3.33
Q
2.65
2.75
2.85
Q1
3.20
3.30
3.40
ØR
3.08
3.18
3.28
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
1
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
OPTION 2: FACILITY CODE = Y
A
A1
E
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.570
4.830
0.180
0.190
A1
2.570
2.830
0.101
0.111
A2
2.510
2.850
0.099
0.112
b
0.622
0.890
0.024
0.035
b2
1.229
1.400
0.048
0.055
b3
1.229
1.400
0.048
0.055
c
0.440
0.629
0.017
0.025
D
8.650
9.800
0.341
0.386
d1
15.88
16.120
0.622
0.635
d3
12.300
12.920
0.484
0.509
E
10.360
10.630
0.408
e
2.54 BSC
0.419
0.100 BSC
L
13.200
13.730
0.520
0.541
L1
3.100
3.500
0.122
0.138
n
6.050
6.150
0.238
0.242
ØP
3.050
3.450
0.120
0.136
u
2.400
2.500
0.094
0.098
V
0.400
0.500
0.016
0.020
ECN: E19-0180-Rev. D, 08-Apr-2019
DWG: 5972
Notes
1. To be used only for process drawing
2. These dimensions apply to all TO-220 FULLPAK leadframe versions 3 leads
3. All critical dimensions should C meet Cpk > 1.33
4. All dimensions include burrs and plating thickness
5. No chipping or package damage
6. Facility code will be the 1st character located at the 2nd row of the unit marking
Revision: 08-Apr-2019
Document Number: 91359
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
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parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.
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Revision: 01-Jan-2022
1
Document Number: 91000