IRFP26N60L

IRFP26N60L, SiHFP26N60L www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Superfast body diode eliminates the need for external diodes in ZVS applications 600 RDS(on) (Ω) VGS = 10 V Qg (Max.) (nC) 0.21 • Lower gate charge results in simpler drive requirements 180 Qgs (nC) 61 Qgd (nC) 85 Configuration • Higher gate voltage threshold offers improved noise immunity D • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 TO-247AC Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. G S D Available • Enhanced dV/dt capabilities offer improved ruggedness Single G Available APPLICATIONS S • Zero voltage switching (SMPS) N-Channel MOSFET • Telecom and server power supplies • Uninterruptible power supplies • Motor control applications ORDERING INFORMATION Package TO-247AC IRFP26N60LPbF Lead (Pb)-free SiHFP26N60L-E3 IRFP26N60L SnPb SiHFP26N60L ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID UNIT V 26 17 A IDM 100 3.8 W/°C EAS 570 mJ Current a IAR 26 A Repetitive Avalanche Energy a EAR 47 mJ Linear Derating Factor Single Pulse Avalanche Energy b Repetitive Avalanche Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dt c Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) d Mounting Torque for 10 s 6-32 or M3 screw PD 470 W dV/dt 21 V/ns TJ, Tstg -55 to +150 300 °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 1.7 mH, Rg = 25 Ω, IAS = 26 A, dV/dt = 21 V/ns (see fig. 12). c. ISD ≤ 26 A, dI/dt ≤ 480 A/μs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. S15-0456-Rev. D, 16-Mar-15 Document Number: 91218 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP26N60L, SiHFP26N60L www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 40 Case-to-Sink, Flat, Greased Surface RthCS 0.24 - Maximum Junction-to-Case (Drain) RthJC - 0.27 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 μA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.33 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 600 V, VGS = 0 V - - 50 μA Drain-Source On-State Resistance Forward Transconductance RDS(on) VDS = 480 V, VGS = 0 V, TJ = 125 °C ID = 10 A b VGS = 10 V - - 2.0 mA - 0.21 0.25 Ω S gfs VDS = 50 V, ID = 16 A 13 - - VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 5020 - - 450 - - 34 - - 230 - - 170 - - - 180 - - 61 - - 85 - 31 - - 110 - - 47 - - 42 - - - 26 - - 100 Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Effective Output Capacitance Coss eff. Effective Output Capacitance (Energy related) Coss eff. (ER) Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VGS = 0 V VDS = 0 V to 480 V c VGS = 10 V ID = 26 A, VDS = 480 V, see fig. 7 and 15b VDD = 300 V, ID = 26 A, Rg = 4.3 Ω,VGS = 10 V see fig. 11a and 11b b tf pF nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current a ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Current Forward Turn-On Time IRRM ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 26 A, VGS = 0 V b - - 1.5 TJ = 25 °C, IF = 26 A - 170 250 TJ = 125 °C, dI/dt = 100 A/μs b - 210 320 TJ = 25 °C, IF = 26 A, VGS = 0 V b - 670 1000 TJ = 125 °C, dI/dt = 100 A/μs b - 1050 1570 TJ = 25 °C - 7.3 11 V ns nC A Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 % to 80 % VDS. S15-0456-Rev. D, 16-Mar-15 Document Number: 91218 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP26N60L, SiHFP26N60L www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) ID, Drain-to-Source Current (A) Top 100 Bottom 1000.00 VGS 15 V 12 V 10 V 8.0 V 7.0 V 6.5 V 6.0 V 5.5 V ID, Drain-to-Source Current (A) 1000 10 1 5.5 V 0.1 100.00 TJ = 150 °C 10.00 TJ = 25 °C 1.00 20 μs PULSE WIDTH TJ = 25 °C 0.10 2.0 0.01 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) RDS(on), Drain-to-Source On Resistance (Normalized) VGS 15 V 12 V 10 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom 5.5 V ID, Drain-to-Source Current (A) 5.5 V 1 20 μs PULSE WIDTH TJ = 150 °C 0.1 0.1 1 10 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics S15-0456-Rev. D, 16-Mar-15 6.0 8.0 10.0 12.0 14.0 16.0 Fig. 3 - Typical Transfer Characteristics Top 10 4.0 VGS, Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics 100 VDS = 50 V 20 μs PULSE WIDTH 100 3.0 ID = 26 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91218 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP26N60L, SiHFP26N60L www.vishay.com VGS = 0 V, Ciss = Cgs + Cgd, Cds Crss = Cgd Coss = Cds + Cgd ID = 26 A VDS = 480 V 10.0 10000 C, Capacitance (pF) 12.0 f = 1 MHz SHORTED VGS, Gate-to-Source Voltage (V) 1000000 Vishay Siliconix Ciss 1000 Coss 100 VDS = 300 V VDS = 120 V 8.0 6.0 4.0 2.0 Crss 10 1 0.0 1000 100 10 0 25 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 100 50 75 Qg, Total Gate Charge (nC) 125 150 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 1000.00 30 ISD, Reverse Drain Current (A) 25 Energy (µJ) 20 15 10 100.00 TJ = 150 °C 10.00 TJ = 25 °C 1.00 5 0 VGS = 0 V 0.10 0 100 200 300 400 500 600 700 VDS, Drain-to-Source Voltage (V) Fig. 6 - Typical Output Capacitance Stored Energy vs.VDS S15-0456-Rev. D, 16-Mar-15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD, Source-to-Drain Voltage (V) Fig. 8 - Typical Source-Drain Diode Forward Voltage Document Number: 91218 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP26N60L, SiHFP26N60L www.vishay.com Vishay Siliconix 1000 30 OPERATING IN THIS AREA LIMITED BY RDS(on) 25 10 ID, Drain Current (A) ID, Drain Current (A) 100 100 µs 20 15 10 1 ms 1 5 TC = 25 °C TJ = 150 °C Single Pulse 0.1 10 ms 0 1 10 1000 100 10000 50 25 VDS, Drain-to-Source Voltage (V) Fig. 9 - Maximum Safe Operating Area 125 100 150 Fig. 10 - Maximum Drain Current vs. Case Temperature RD VDS 75 TC, Case Temperature (°C) VDS 90 % VGS D.U.T. RG + - VDD 10 % VGS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % td(on) tr td(off) tf Fig. 11b - Switching Time Waveforms Fig. 11a - Switching Time Test Circuit Thermal Response (ZthJC) 1 0.1 D = 0.50 0.20 0.10 0.05 0.01 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) 0.001 t2 Notes: 1. Duty factor D = t1/ t2 2. Peak TJ = PDM x ZthJC + TC 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t , Rectangular Pulse Duration (s) Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S15-0456-Rev. D, 16-Mar-15 Document Number: 91218 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP26N60L, SiHFP26N60L www.vishay.com Vishay Siliconix 1050 EAS, Single Pulse Avalanche Energy (mJ) VGS(th), Gate threshold Voltage (V) 6.0 5.0 4.0 ID = 250 μA 3.0 2.0 TOP 900 BOTTOM ID 12 A 16 A 26 A 750 600 450 300 150 0 -75 -50 50 -25 0 75 25 TJ, Temperature (°C) 125 100 150 50 25 75 Fig. 13 - Threshold Voltage vs. Temperature tp QGD VG + A - VDD IAS 20 V QGS Driver D.U.T RG 150 QG VGS V L 125 Fig. 14c - Maximum Avalanche Energy vs. Drain Current 15 V VDS 100 Starting TJ, Junction Temperature (°C) Charge 0.01 Ω Fig. 14a - Unclamped Inductive Test Circuit Fig. 15a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS 50 kΩ tp 12 V 0.2 µF 0.3 µF + D.U.T. - VDS VGS IAS 3 mA IG ID Current sampling resistors Fig. 14b - Unclamped Inductive Waveforms S15-0456-Rev. D, 16-Mar-15 Fig. 15b - Gate Charge Test Circuit Document Number: 91218 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFP26N60L, SiHFP26N60L www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 16 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91218. S15-0456-Rev. D, 16-Mar-15 Document Number: 91218 7 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) VERSION 1: FACILITY CODE = 9 MILLIMETERS DIM. MIN. MAX. A 4.83 A1 2.29 MILLIMETERS NOTES DIM. MIN. MAX. NOTES 5.21 D1 16.25 16.85 5 2.55 D2 0.56 0.76 A2 1.50 2.49 E 15.50 15.87 b 1.12 1.33 E1 13.46 14.16 5 b1 1.12 1.28 E2 4.52 5.49 3 b2 1.91 2.39 b3 1.91 2.34 b4 2.87 3.22 b5 2.87 3.18 c 0.55 0.69 c1 0.55 0.65 D 20.40 20.70 4 6 e L 14.90 15.40 6, 8 L1 3.96 4.16 6 ØP 3.56 3.65 7 6 4 5.44 BSC Ø P1 7.19 ref. Q 5.31 5.69 S 5.54 5.74 Notes (1) Package reference: JEDEC® TO247, variation AC (2) All dimensions are in mm (3) Slot required, notch may be rounded (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body (5) Thermal pad contour optional with dimensions D1 and E1 (6) Lead finish uncontrolled in L1 (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 19-Oct-2020 Document Number: 91360 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = Y A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L See view B 2 x b2 3xb 0.10 M C A M 4 E1 A 0.01 M D B M View A - A C 2x e A1 b4 (b1, b3, b5) Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 MILLIMETERS NOTES DIM. MIN. MAX. D2 0.51 1.30 15.87 A1 2.21 2.59 E 15.29 A2 1.17 2.49 E1 13.72 b 0.99 1.40 e 5.46 BSC b1 0.99 1.35 Øk b2 1.53 2.39 L 14.20 16.25 b3 1.65 2.37 L1 3.71 4.29 b4 2.42 3.43 ØP 3.51 3.66 b5 2.59 3.38 Ø P1 - 7.39 c 0.38 0.86 Q 5.31 5.69 4.52 c1 0.38 0.76 R D 19.71 20.82 S D1 13.08 - NOTES 0.254 5.49 5.51 BSC Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 19-Oct-2020 Document Number: 91360 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 3: FACILITY CODE = N A E R/2 D2 B A P A2 D1 L1 D D K M D BM R S Q N P1 b2 L C e b b4 C E1 A1 0.01 M D B M 0.10 M C A M b1, b3, b5 c c1 Base metal Plating b, b2, b4 MILLIMETERS MILLIMETERS DIM. MIN. MAX. DIM. MIN. A 4.65 5.31 D2 0.51 MAX. 1.35 A1 2.21 2.59 E 15.29 15.87 13.46 A2 1.17 1.37 E1 b 0.99 1.40 e - b1 0.99 1.35 k b2 1.65 2.39 L 14.20 b3 1.65 2.34 L1 3.71 b4 2.59 3.43 N b5 2.59 3.38 P 3.56 c 0.38 0.89 P1 - 7.39 c1 0.38 0.84 Q 5.31 5.69 D 19.71 20.70 R 4.52 D1 13.08 - S 5.46 BSC 0.254 16.10 4.29 7.62 BSC 3.66 5.49 5.51 BSC ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971 Notes (1) Dimensioning and tolerancing per ASME Y14.5M-1994 (2) Contour of slot optional (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (4) Thermal pad contour optional with dimensions D1 and E1 (5) Lead finish uncontrolled in L1 (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 19-Oct-2020 Document Number: 91360 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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