IRFP460A, SiHFP460A
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Available
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt RoHS*
COMPLIANT
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Effective Coss Specified
• Compliant to RoHS Directive 2002/95/EC
500
RDS(on) (Ω)
VGS = 10 V
0.27
Qg (Max.) (nC)
105
Qgs (nC)
26
Qgd (nC)
42
Configuration
Single
D
APPLICATIONS
TO-247
• Switch Mode Power Supply (SMPS)
• Uninterruptable Power Supply
• High Speed Power Switching
G
TYPICAL SMPS TOPOLOGIES
S
D
• Full Bridge
• PFC Boost
S
G
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247
IRFP460APbF
SiHFP460A-E3
IRFP460A
SiHFP460A
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
Pulsed Drain
VGS at 10 V
TC = 25 °C
TC = 100 °C
Currenta
ID
IDM
Linear Derating Factor
UNIT
V
20
13
A
80
2.2
W/°C
mJ
Single Pulse Avalanche Energyb
EAS
960
Repetitive Avalanche Currenta
IAR
20
A
Repetitive Avalanche Energya
EAR
28
mJ
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
PD
280
W
dV/dt
3.8
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 4.3 mH, Rg = 25 Ω, IAS = 20 A (see fig. 12).
c. ISD ≤ 20 A, dI/dt ≤ 125 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
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1
IRFP460A, SiHFP460A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.45
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.61
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
0.27
Ω
11
-
-
S
-
3100
-
-
480
-
18
-
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 12 Ab
VGS = 10 V
VDS = 50 V, ID = 12
Ab
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Turn-On Delay Time
Turn-Off Delay Time
Fall Time
VGS = 0 V
Coss eff.
Total Gate Charge
Rise Time
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
VDS = 1.0 V, f = 1.0 MHz
4430
VDS = 400 V, f = 1.0 MHz
130
VDS = 0 V to 400 Vc
140
-
-
105
-
-
26
Qgd
-
-
42
td(on)
-
18
-
tr
-
55
-
-
45
-
-
39
-
-
-
20
-
-
80
td(off)
VGS = 10 V
ID = 20 A, VDS = 400 V,
see fig. 6 and 13b
VDD = 250 V, ID = 20 A,
RG = 4.3 Ω, RD = 13 Ω, see fig. 10b
tf
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 20A, VGS = 0
S
Vb
TJ = 25 °C, IF = 20 A, dI/dt = 100 A/µsb
-
-
1.8
V
-
480
710
ns
-
5.0
7.5
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
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Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
102
VGS
Top
10
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
1
4.5 V
20 µs Pulse Width
TC = 25 °C
0.1
0.1
VDS, Drain-to-Source Voltage (V)
91234_01
150 °C
10
25 °C
1
4.0
10
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
4.5 V
20 µs Pulse Width
TC = 150 °C
1
10
1
91234_02
Fig. 2 - Typical Output Characteristics
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
3.0
2.5
7.0
8.0
9.0
ID = 20 A
VGS = 10 V
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20
102
VDS, Drain-to-Source Voltage (V)
6.0
Fig. 3 - Typical Transfer Characteristics
RDS(on), Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
VGS
Top
5.0
VGS, Gate-to-Source Voltage (V)
91234_03
Fig. 1 - Typical Output Characteristics
102
20 µs Pulse Width
VDS = 50 V
0.1
102
10
1
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
102
91234_04
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFP460A, SiHFP460A
Vishay Siliconix
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Capacitance (pF)
104
Ciss
103
102
Coss
10
Crss
102
ISD, Reverse Drain Current (A)
105
VGS = 0 V
0.1
1
102
10
103
VDS, Drain-to-Source Voltage (V)
91234_05
0.2
103
ID, Drain Current (A)
12
VDS = 100 V
8
4
For test circuit
see figure 13
0
0
91234_06
20
40
60
80
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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4
1.0
1.2
1.4
1.6
102
10 µs
100 µs
10
1 ms
1
TC = 25 °C
TJ = 150 °C
Single Pulse
10
100
QG, Total Gate Charge (nC)
0.8
Operation in this area limited
by RDS(on)
VDS = 400 V
VDS = 250 V
0.6
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID = 20 A
16
0.4
VSD, Source-to-Drain Voltage (V)
91234_07
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
VGS, Gate-to-Source Voltage (V)
25 °C
1
1
20
150 °C
10
91234_08
10 ms
102
103
104
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
RD
VDS
VGS
ID, Drain Current (A)
20
D.U.T.
RG
+
- VDD
10 V
15
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
10
Fig. 10a - Switching Time Test Circuit
VDS
5
90 %
0
25
50
75
100
125
150
10 %
VGS
TC, Case Temperature (°C)
91234_09
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
1
D = 0.5
0.1
0.2
0.1
0.05
10-2
PDM
0.02
0.01
t1
Single Pulse
(Thermal Response)
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5
10-4
10-3
10-2
0.1
1
t1, Rectangular Pulse Duration (S)
91234_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T.
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
Fig. 12b - Unclamped Inductive Waveforms
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IRFP460A, SiHFP460A
2400
ID
Top
8.9 A
13 A
Bottom 20 A
2000
1600
1200
800
400
0
620
VDSav, Avalanche Voltage (V)
EAS, Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
600
580
560
540
25
50
75
100
125
Starting TJ, Junction Temperature (°C)
91234_12c
0
150
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
8
4
12
16
20
IAV, Avalanche Current (A)
91234_12d
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91234.
Document Number: 91234
S09-1284-Rev. B, 13-Jul-09
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Package Information
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Vishay Siliconix
TO-247AC (High Voltage)
A
A
4
E
B
3 R/2
E/2
7 ØP
Ø k M DBM
A2
S
(Datum B)
ØP1
A
D2
Q
4
4
2xR
(2)
D1
D
1
2
4
D
3
Thermal pad
5 L1
C
L
A
See view B
2 x b2
3xb
0.10 M C A M
4
E1
0.01 M D B M
View A - A
C
2x e
A1
b4
Planting
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D DE
(b1, b3, b5)
Base metal
E
C
(c)
C
c1
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS
DIM.
MIN.
MAX.
A
4.58
5.31
A1
2.21
2.59
A2
1.17
2.49
b
0.99
1.40
b1
0.99
1.35
b2
1.53
2.39
b3
1.65
2.37
b4
2.42
3.43
b5
2.59
3.38
c
0.38
0.86
c1
0.38
0.76
D
19.71
20.82
D1
13.08
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
INCHES
MIN.
MAX.
0.180
0.209
0.087
0.102
0.046
0.098
0.039
0.055
0.039
0.053
0.060
0.094
0.065
0.093
0.095
0.135
0.102
0.133
0.015
0.034
0.015
0.030
0.776
0.820
0.515
-
DIM.
D2
E
E1
e
Øk
L
L1
N
ØP
Ø P1
Q
R
S
MILLIMETERS
MIN.
MAX.
0.51
1.30
15.29
15.87
13.72
5.46 BSC
0.254
14.20
16.25
3.71
4.29
7.62 BSC
3.51
3.66
7.39
5.31
5.69
4.52
5.49
5.51 BSC
INCHES
MIN.
MAX.
0.020
0.051
0.602
0.625
0.540
0.215 BSC
0.010
0.559
0.640
0.146
0.169
0.300 BSC
0.138
0.144
0.291
0.209
0.224
0.178
0.216
0.217 BSC
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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Revision: 08-Feb-17
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Document Number: 91000
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