IRFR210, IRFU210, SiHFR210, SiHFU210
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Vishay Siliconix
Power MOSFET
FEATURES
D
DPAK
(TO-252)
•
•
•
•
•
•
•
•
IPAK
(TO-251)
D
D
G
G
S
G
D S
S
N-Channel MOSFET
DESCRIPTION
PRODUCT SUMMARY
VDS (V)
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU, SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
200
RDS(on) (Ω)
Dynamic dV/dt rating
Repetitive avalanche rated
Surface-mount (IRFR210, SiHFR210)
Straight lead (IRFU210, SiHFU210)
Available in tape and reel
Available
Fast switching
Ease of paralleling
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
VGS = 10 V
Qg max. (nC)
1.5
8.2
Qgs (nC)
1.8
Qgd (nC)
4.5
Configuration
Single
ORDERING INFORMATION
PACKAGE
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
SiHFR210-GE3
SiHFR210TRL-GE3 a
-
SiHFR210TRR-GE3 a
SiHFU210-GE3
Lead (Pb)-free
IRFR210PbF
IRFR210TRLPbF a
IRFR210TRPbF a
IRFR210TRRPbF
IRFU210PbF
Lead (Pb)-free and
halogen-free
IRFR210PbF-BE3 ab
IRFR210TRLPbF-BE3 ab
IRFR210TRPbF-BE3 ab
-
-
Lead (Pb)-free and
halogen-free
Notes
a. See device orientation
b. “-BE3” denotes alternate manufacturing location
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current
Pulsed drain current a
Linear derating factor
Linear derating factor (PCB mount) e
Single pulse avalanche Energy b
Avalanche current a
Repetitive avalanche energy a
Maximum power dissipation
Maximum power dissipation (PCB mount) e
Peak diode recovery dV/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature)d
VGS at 10 V
TC = 25 °C
TC = 100 °C
SYMBOL
LIMIT
VDS
VGS
200
± 20
2.6
1.7
10
0.20
0.020
95
2.7
2.5
25
2.5
5.0
-55 to +150
260
ID
IDM
EAS
IAR
EAR
TC = 25 °C
TA = 25 °C
PD
dV/dt
TJ, Tstg
for 10 s
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 50 V, starting TJ = 25 °C, L = 28 mH, Rg = 25 Ω, IAS = 2.6 A (see fig. 12)
c. ISD ≤ 2.6 A, dI/dt ≤ 70 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
e. When mounted on 1" square PCB (FR-4 or G-10 material)
S21-0373-Rev. F, 19-Apr-2021
Document Number: 91268
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR210, IRFU210, SiHFR210, SiHFU210
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
RthJA
-
-
110
Maximum junction-to-ambient (PCB mount) a
RthJA
-
-
50
Maximum junction-to-case (drain)
RthJC
-
-
5.0
Maximum junction-to-ambient
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VDS
VGS = 0 V, ID = 250 μA
200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.30
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-source leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-source on-state resistance
Forward transconductance
μA
-
-
1.5
Ω
gfs
VDS = 50 V, ID = 1.6 A b
0.80
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
140
-
-
53
-
-
15
-
RDS(on)
ID = 1.6 A b
VGS = 10 V
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
-
-
8.2
-
-
1.8
Qgd
-
-
4.5
td(on)
-
8.2
-
tr
-
17
-
-
14
-
-
8.9
-
-
4.5
-
-
7.5
-
-
-
2.6
-
-
10
td(off)
Fall time
tf
Internal drain inductance
LD
Internal source inductance
LS
VGS = 10 V
ID = 3.3 A, VDS = 160 V,
see fig. 6 and 13 b
VDD = 100 V, ID = 3.3 A,
Rg = 24 Ω, RD = 30 Ω, see fig. 10 b
Between lead,
6 mm (0.25") from
package and center of
die contact
D
G
pF
nC
ns
nH
S
Drain-source body diode characteristics
Continuous source-drain diode current
Pulsed diode forward current a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
G
A
S
TJ = 25 °C, IS = 2.6 A, VGS = 0 V b
TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/μs b
-
-
2.0
V
-
150
310
ns
-
0.60
1.4
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
S21-0373-Rev. F, 19-Apr-2021
Document Number: 91268
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR210, IRFU210, SiHFR210, SiHFU210
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 1 - Typical Output Characteristics, TC = 150 °C
S21-0373-Rev. F, 19-Apr-2021
Fig. 2 - Typical Transfer Characteristics
Fig. 3 - Normalized On-Resistance vs. Temperature
Document Number: 91268
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR210, IRFU210, SiHFR210, SiHFU210
www.vishay.com
Vishay Siliconix
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Maximum Safe Operating Area
S21-0373-Rev. F, 19-Apr-2021
Document Number: 91268
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR210, IRFU210, SiHFR210, SiHFU210
www.vishay.com
Vishay Siliconix
RD
VDS
VGS
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 8 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 9 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
Rg
+
-
I AS
V DD
VDS
10 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
S21-0373-Rev. F, 19-Apr-2021
IAS
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91268
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR210, IRFU210, SiHFR210, SiHFU210
www.vishay.com
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0373-Rev. F, 19-Apr-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91268
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRFR210, IRFU210, SiHFR210, SiHFU210
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
•
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 10 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91268.
S21-0373-Rev. F, 19-Apr-2021
Document Number: 91268
7
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-252AA Case Outline
VERSION 1: FACILITY CODE = Y
E
A
C2
H
D
D1
L3
b3
e
b2
e1
L
gage plane height (0.5 mm)
L4
b
L5
E1
C
A1
MILLIMETERS
DIM.
MIN.
A
2.18
MAX.
2.38
A1
-
0.127
b
0.64
0.88
b2
0.76
1.14
b3
4.95
5.46
C
0.46
0.61
C2
0.46
0.89
D
5.97
6.22
D1
4.10
-
E
6.35
6.73
E1
4.32
-
H
9.40
10.41
e
2.28 BSC
e1
4.56 BSC
L
1.40
1.78
L3
0.89
1.27
L4
-
1.02
L5
1.01
1.52
Note
• Dimension L3 is for reference only
Revision: 03-Oct-2022
Document Number: 71197
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
VERSION 2: FACILITY CODE = N
E
e
A
b3
E1
E1/2
c2
θ
e
L4
L5
L6
H
D
L3
D1
θ
0.25
(3°)
DETAIL "B"
C A B
(3°)
DETAIL "B"
A1
C
L
(L1)
b1
SEATING
C
PLANE
θ
L2
GAUGE
PLANE
H
C
(b)
c1
3x b
2x e
c
2x b2
MILLIMETERS
MILLIMETERS
DIM.
A
MIN.
2.18
MAX.
DIM.
MIN.
2.39
L
1.50
A1
-
0.13
L1
b
0.65
0.89
L2
MAX.
1.78
2.74 ref.
0.51 BSC
b1
0.64
0.79
L3
b2
0.76
1.13
L4
-
1.02
b3
4.95
5.46
L5
1.14
1.49
c
0.46
0.61
L6
0.65
0.85
c1
0.41
0.56
0°
10°
1
0°
15°
2
25°
35°
c2
0.46
0.60
D
5.97
6.22
D1
5.21
-
E
6.35
6.73
E1
4.32
e
H
2.29 BSC
9.94
0.89
1.27
Notes
• Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
• Heat sink side flash is max. 0.8 mm
• Radius on terminal is optional
10.34
ECN: E22-0399-Rev. R, 03-Oct-2022
DWG: 5347
Revision: 03-Oct-2022
Document Number: 71197
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
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3
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Revision: 01-Jan-2022
1
Document Number: 91000