IRFSL9N60A, SiHFSL9N60A
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Vishay Siliconix
Power MOSFET
FEATURES
D
• Low gate charge Qg results in simple drive
requirement
I2PAK (TO-262)
• Improved gate, avalanche, and dynamic dv/dt
ruggedness
G
Available
Available
• Fully characterized capacitance and avalanche
voltage and current
G
D
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
VDS (V)
600
RDS(on) ()
VGS = 10 V
0.75
Qg max. (nC)
49
APPLICATIONS
Qgs (nC)
13
• Switch mode power supply (SMPS)
20
• Uninterruptable power supply
Qgd (nC)
Configuration
Single
• High speed power switching
• This device is only for through-hole application
APPLICABLE OFF LINE SMPS TOPOLOGIES
• Active clamped forward
• Main switch
ORDERING INFORMATION
Package
I2PAK (TO-262)
Lead (Pb)-free and halogen-free
SiHFSL9N60A-GE3
Lead (Pb)-free
IRFSL9N60APbF
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
600
Gate-source voltage
VGS
± 30
Continuous drain current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
Single pulse avalanche
energy b
UNIT
V
9.2
5.8
A
37
1.3
W/°C
mJ
EAS
290
Repetitive avalanche current a
IAR
9.2
A
Repetitive avalanche energy a
EAR
17
mJ
Maximum power dissipation
TC = 25 °C
Peak diode recovery dv/dt c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
For 10 s
PD
170
W
dv/dt
5.0
V/ns
TJ, Tstg
-55 to +150
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 6.8 mH, Rg = 25 , IAS = 9.2 A (see fig. 12)
c. ISD 9.2 A, di/dt 50 A/μs, VDD VDS, TJ 150 °C
d. 1.6 mm from case
S20-0684-Rev. D, 07-Sep-2020
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
(PCB mounted, steady-state)
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
0.75
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS
VGS = 0, ID = 250 μA
600
-
-
V
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 600 V, VGS = 0 V
-
-
25
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
250
Gate-source threshold voltage
μA
-
-
0.75
gfs
VDS = 25 V, ID = 3.1 A b
5.5
-
-
S
Input capacitance
Ciss
1400
-
Coss
-
180
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
Output capacitance
-
7.1
-
Output capacitance
Coss
VDS = 1.0 V, f = 1.0 MHz
-
1957
-
VDS = 480 V, f = 1.0 MHz
-
49
-
VDS = 0 V to 480 V c
-
96
-
-
-
49
Drain-source on-state resistance
Forward transconductance
RDS(on)
ID = 5.5 A b
VGS = 10 V
Dynamic
Effective output capacitance
VGS = 0 V
Coss eff.
pF
Total gate charge
Qg
Gate-source charge
Qgs
-
-
13
Gate-drain charge
Qgd
-
-
20
Turn-on delay time
td(on)
-
13
-
tr
-
25
-
-
30
-
-
22
-
-
-
9.2
-
-
37
-
-
1.5
-
530
800
ns
-
3.0
4.4
μC
Rise time
Turn-off delay time
Fall time
td(off)
VGS = 10 V
ID = 9.2 A, VDS = 400 V,
see fig. 6 and 13 b
VDD = 300 V, ID = 9.2 A,
Rg = 9.1 , RD = 35.5 , see fig. 10 b
tf
nC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current a
Body diode voltage
IS
ISM
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
G
A
S
TJ = 25 °C, IS = 9.2 A, VGS = 0 V b
TJ = 25 °C, IF = 9.2 A, di/dt = 100 A/μs b
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
c. COSS eff. is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 % to 80% VDS
S20-0684-Rev. D, 07-Sep-2020
Document Number: 90362
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.7V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
1
4.7V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
100
10
TJ = 25 ° C
1
0.1
4.0
Fig. 1 - Typical Output Characteristics
I D , Drain-to-Source Current (A)
10
4.7V
20µs PULSE WIDTH
TJ = 150 °C
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
S20-0684-Rev. D, 07-Sep-2020
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.7V
1
5.0
6.0
7.0
8.0
9.0
10.0
Fig. 3 - Typical Transfer Characteristics
TOP
1
V DS = 50V
20µs PULSE WIDTH
VGS , Gate-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
100
TJ = 150 ° C
ID = 9.2A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 90362
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V GS
C is s
C rss
C o ss
C , Capacitance (pF )
2000
=
=
=
=
100
0V,
f = 1M H z
C g s + C g d , Cd s S H O R TE D
C gd
C ds + C gd
ISD , Reverse Drain Current (A)
2400
Vishay Siliconix
C iss
1600
C oss
1200
800
C rss
400
0
10
TJ = 150 ° C
1
TJ = 25 ° C
0.1
0.2
A
1
10
100
1000
V D S , D rain-to-S ource V olta ge (V )
0.7
1.0
1.2
Fig. 7 - Typical Source-Drain Diode Forward Voltage
1000
ID = 9.2A
OPERATION IN THIS AREA LIMITED
BY RDS(on)
400V
VDS = 480V
VDS = 300V
VDS = 120V
16
100
I D , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
0.5
VSD ,Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
V GS = 0 V
12
8
10us
10
100us
1ms
1
10ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
20
30
40
50
Q G , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S20-0684-Rev. D, 07-Sep-2020
0.1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 90362
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IRFSL9N60A, SiHFSL9N60A
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RD
VDS
10.0
VGS
D.U.T.
Rg
+
- VDD
I D , Drain Current (A)
8.0
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
6.0
Fig. 10a - Switching Time Test Circuit
4.0
VDS
90 %
2.0
0.0
25
50
75
100
TC , Case Temperature
125
10 %
VGS
150
( °C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
P DM
0.05
t1
0.02
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.01
0.00001
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S20-0684-Rev. D, 07-Sep-2020
Document Number: 90362
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VDS
tp
15 V
Driver
L
VDS
Rg
D.U.T.
+
A
- VDD
IAS
20 V
tp
IAS
A
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS , Single Pulse Avalanche Energy (mJ)
600
ID
4.1A
5.8A
9.2A
TOP
500
BOTTOM
400
300
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S20-0684-Rev. D, 07-Sep-2020
Fig. 13b - Gate Charge Test Circuit
Document Number: 90362
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90362.
S20-0684-Rev. D, 07-Sep-2020
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Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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